Programmable Timing Control Hub for PII/III

ICS9562 Programmable Timing Control Hub for PII/III Recommended Application: VIA Mobile PL33T and PLE33T Chipsets. Output Features: 2 - CPU clocks @ 2.5V - Pairs of differential CPU clocks @ 3.3V 7 - PCI including free running @ 3.3V 7 - SDRAM @ 3.3V - 48MHz @ 3.3V fixed - 24_48MHz selectable @ 3.3V 2 - REF @ 3.3V, 4.38MHz Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Key Specifications: CPU Output Jitter <2ps CPU Output Skew <75ps PCI to PCI Output Skew <5ps GND *FS2/REF REF Vtt_PWRGD# VDDREF GND 2 VDDPCI *FS4/PCICLK_F *FS3/PCICLK GND PCICLK PCICLK2 PCICLK3 PCICLK4 PCICLK5 SDRAM_IN *CPU_STOP# *PCI_STOP# *PD# **MULTISEL GND SDATA Pin Configuration 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 ICS9562 48 47 46 45 44 43 42 4 4 39 38 37 36 35 34 33 32 3 3 29 28 27 26 25 48-Pin SSOP & TSSOP CPUCLK CPUCLK VDDCPU_2.5 VDDCPU_3.3 CPUCLKT CPUCLKC GND RESET# I REF SDRAM6 GND SDRAM SDRAM VDDSDRAM SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDRAM AVDD48 48MHz/FS* 24_48MHz/FS* SCLK * Internal Pull-up resistor of 2K to VDD ** these inputs have 2K internal pull-down to GND Block Diagram Host Swing Select Functions MULTISEL Board Target Trace/Term Z 5 ohms 5 ohms Reference R, Iref = V /(3*Rr ) D D Rr = 22 %, Iref = 5.mA Rr = 475 %, Iref = 2.32mA Output Current Voh @ Z Ioh = 4* I REF.V @ 5 Ioh = 6* I REF.7V @ 5 469B 2/8/2

ICS9562 General The ICS9562 is a single chip clock solution for VIA Mobile PL33T and PLE33T chipsets. It provides all necessary clock signals for such a system. The ICS9562 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to.mhz increment. With all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple. Pin PIN NUMBER, 6, 2, 23, 32, 38, 42, GND 5, 9, 29, 35 VDD 2 FS2 REF 3 REF PIN NAME 4 Vtt_PWRGD# 7 8 2 TYPE PWR PWR Ground pins for 3.3V supply 3.3V power supply DESCRIPTION I N Logic input frequency select bit. Input latched at power on. O UT 3.3V, 4.38MHz reference clock output. O UT 3.3V, 4.38MHz reference clock output. IN This 3.3V LVTTL input is a level sensitive strobe used are valid and are ready to be sampled (active low) to determine when FS (4:) IN Crystal input, has internal load cap (33pF) and feedback resistor from 2 O UT Crystal output, nominally 4.38MHz. Has internal load cap (33pF) 469B 2/8/2 FS4 PCICLK_F FS3 PCICLK I N Logic input frequency select bit. Input latched at power on. OUT 3.3V PCI clock output I N Logic input frequency select bit. Input latched at power on. OUT 3.3V PCI clock output 7, 6, 5, 4, 3 PCICLK (5:) OUT 3.3V PCI clock outputs 8 SDRAM_IN I N SDRAM buffer input pin. 9 CPU_STOP# IN Stops all CPUCLKs clocks at logic level, when input low 2 PCI_STOP# IN Stops all PCICLKs besides the PCICLK_F clocks at logic level, when input low 2 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 22 MULTSEL I N 3.3V LVTTL input for selecting the current multiplier for CPU outputs. 24 SDATA I/ O 2 Data pin for I C circuitry 5V tolerant 25 SCLK IN 2 Clock pin for I C circuitry 5V tolerant FS I N Logic input frequency select bit. Input latched at power on. 26 48_24MHz OUT Selectable 48 or 24MHz output FS I N Logic input frequency select bit. Input latched at power on. 27 48MHz O UT 3.3V Fixed 48MHz clock output. 28 AVDD48 P WR 3.3V analog power supply for 48 or 24MHz outputs. 3, 3, 33, 34, 36, 37, 39 4 I REF SDRAM (5:, 6) 4 RESET# 43 CPUCLKC 44 CPUCLKT 45 VDDCPU_3. 3 46 VDDCPU_2. 5 47, 48 CPUCLK (:) O UT SDRAM clock outputs. This pin establishes the reference current for the CPUCLK pairs. This pin requires OUT a fixed precision resistor tied to ground in order to establish the appropriate current. OUT Real time system reset signal for frequency value or watchdog timer timeout. This signal is active low. OUT "Complementary" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. OUT "True" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. P WR 3.3V power for CPU differential clocks. P WR 2.5V power for CPU clocks. O UT CPU clock outputs. 2

ICS9562 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N + - *See notes on the following page. 469B 2/8/2 3

ICS9562 Byte : Functionality and frequency select register (Default=) (2:,6:4) 3 7 2 6 5 4 CPUCLK PCICLK FS4 FS3 FS2 FS FS MHz MHz Spread % 2. 33.3 9. 38. 8. 36. 7. 34. 66. 33.2 6. 32. 5. 37.5 45. 36.3 4. 35. 36. 34. 3. 32.5 24. 3. 67.2 33.6.9 33.63 8. 39.3 34.4 33.6 67. 33.5.5 33.5 5. 38.3 33.9 33.47 66.8 33.4.2 33.4. 36.7 33.6 33.4 5. 35. 9. 3. 85. 28.3 78. 39. 66.6 33.3. 33.3 to -.5% down spread 75. 37.5 33.3 33.3 to -.5% down spread - Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable - Watch dog safe frequency will be selected by latch inputs - Watch dog safe frequency will be programmed by Byte bit (4:) Note Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by 3. 469B 2/8/2 4

ICS9562 Byte : Output Control Register ( = enable, = disable) B it Pin# 7 - FS4 Read back 6 - FS3 Read back 5 - FS2 Read back 4 - FS Read back 3 - FS Read back 2 48 CPUCLK 47 CPUCLK 44, 43 CPUCLKT, CPUCLKC Byte 2: Output Control Register ( = enable, = disable) B it Pin# 7 39 SDRAM6 6 PCICLK_ F 5 7 PCICLK5 4 6 PCICLK4 3 5 PCICLK3 2 4 PCICLK2 3 PCICLK PCICLK Byte 3: Output Control Register ( = enable, = disable) B it Pin# 7 - RESET gear shift detect = Enable, = Disable 6 - SEL24_48: = 24, = 48 5 27 48MHz 4 26 24_48MHz 3 - Reserved 2 3, 3 SDRAM (4:5) 34, 33 SDRAM (2:3) 37, 36 SDRAM (:) Byte 4: Output Control Register ( = enable, = disable) B it Pin# 7 - MULTSEL Read back 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved - Reserved - Reserved 469B 2/8/2 5

ICS9562 Byte 5: Output Control Register ( = enable, = disable) B it Pin# 7 - Reserved 6 - Reserved 5 - Reserved 4 - CPUCLK Free running control, = Not free running = Free running 3 - CPUCLK Free running control, = Not free running = Free running 2 - CPUCLKT/C Free running control, = Not free running = Free running 2 REF 3 REF Byte 6: Reserved Register ( = enable, = disable) B it Pin# 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved - Reserved - Reserved Byte 7: Byte Count Read Back Register Name 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Default Byte count read back is 5 Byte. Byte 8: Vendor ID Register Name 7 Revision ID 3 6 Revision ID 2 5 Revision ID 4 Revision ID 3 Vendor ID 3 (Reserved ) 2 Vendor ID 2 (Reserved ) Vendor ID (Reserved ) Vendor ID (Reserved ) Revision ID values will be based on individual device's revision 469B 2/8/2 6

ICS9562 Byte 9: Watchdog Timer Count Register Name 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 6 29ms = 4.64 seconds. Byte : Programming Enable bit 8 Watchdog Control Register Name 7 Programming Enable bit Program = no programming. Frequencies are selected by HW latches or Byte Enable 2 = enable all I C programing. 6 WD Enable Watchdog Enable bit. This bit will over write WDEN latched value. = disable, = Enable. 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits will configure the safe 2 SF2 frequency corrsponding to Byte 2, 7:4 table SF SF Byte : VCO Frequency M Divider (Reference divider) Control Register Name 7 Ndiv 8 N divider bit 8 6 Mdiv 6 5 Mdiv 5 4 Mdiv 4 The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 reference divider value. Default at power up is equal to the 2 Mdiv 2 latched inputs selection. Mdiv Mdiv Byte 2: VCO Frequency N Divider (VCO divider) Control Register Name 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 469B 2/8/2 7

ICS9562 Byte 3: Spread Spectrum Control Register Name 7 SS 7 6 SS 6 5 SS 5 4 SS 4 3 SS 3 2 SS 2 SS SS The Spread Spectrum will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 4: Spread Spectrum Control Register Name 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SS 2 Spread Spectrum 2 3 SS Spread Spectrum 2 SS Spread Spectrum SS 9 Spread Spectrum 9 SS 8 Spread Spectrum 8 469B 2/8/2 8

ICS9562 Absolute Maximum Ratings Supply Voltage........................... 5.5 V Logic Inputs............................. GND.5 V to V DD +.5 V Ambient Operating Temperature............ C to +7 C Case Temperature........................ 5 C Storage Temperature..................... 65 C to +5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS -.3.8 V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 ma I IL2 V IN = V; Inputs with pull-up resistors -2 Operating Supply C L = pf; Select @ 67 MHz I DD3.3OP Current C L =Full load, SDRAM not running 44 28 ma Powerdown Current I DD3.3PD IREF = 2.32 ma 2 IREF = 5 ma 22 37 ma Input Frequency F i V DD = 3.3 V 4.32 MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins 27 45 pf Transition time T trans To st crossing of target frequency 3 ms Settling time T s From st crossing to % target frequency 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target frequency 3 ms Delay t PZH,t PZL Output enable delay (all outputs) ns t PHZ,t PLZ Output disable delay (all outputs) ns Guaranteed by design, not % tested in production. 469B 2/8/2 9

ICS9562 Electrical Characteristics - CPUCLK(T,C) T A = - 7 C; V DD =3.3V +/-5%; loads from Intel CK48B spec, Rev. (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Current Source Output Impedance Z O2A V O = V x 3 Ω Output High Voltage V OH2A.7.2 V V R = 475Ω +%; IREF = 2.32 ma; I OH = 6*IREF Output High Current I OH32A -3.92 ma Rise Time t r2a V OL = -.35V, V OH =.35V 75 22 467 ps Fall Time t f2a V OH =.35V, V OL = -.35V 75 23 467 ps Differential Crossover Voltage V 2A Rs = 33.2Ω, Rp = 63.4Ω to gnd, R T-C = 475Ω 5 7 9 mv Duty Cycle d t2a V T = crossing point 45 49 55 % Skew, CPUT,C to CPU t sk2a V T (CPU) = crossing point, V T (PCI) =.25 V MHz 25 3 33 MHz 7 2 ps Skew, CPUT,C to PCI t sk2a V T (CPU) = crossing point, V T (PCI) =.5 V 2 3.2 4 ns Jitter, Cycle to cycle t jcyc-cyc2a V T = crossing point CPU,SD = MHz 5 2 ps Guaranteed by design, not % tested in production. Electrical Characteristics - CPUCLK(:) T A = - 7 C; V DD =3.3V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH2B I OH = - ma 2 Output Low Voltage V OL2B I OL = ma.4 Output Impedance Output High Current R DSP2B I OH2B V O = V DD *(.5) V OH@MIN =. V, V OH@MA = 2.375 V 3.5-27 45 27 Output Impedance Output Low Current R DSN2B I OL2B V O = V DD *(.5) V OL@MIN =.2 V, V OL@MIN =.3 V 3.5 27 45 3 Ω V V Rise Time t r2b V OL =.4V, V OH = 2.V.7.4 Fall Time t f2b V OH = 2.V V OL =.4V.8.6 ns Duty Cycle d t2b V T = 5% MHz 5 45 33 MHz 54 55 % Skew, CPU to CPU t sk2b V T =.25 V 6 75 ps Skew, CPU to PCI t sk2b V T (CPU) =.25 V, V T (PCI) =.5 V 2 3.2 4 ns V T =.25V CPU,SD = MHz 4 25 Jitter, Cycle to cycle t jcyc-cyc2b CPU,SD = 33 MHz 25 ps CPU =, SD = 33 MHz 22 275 Guaranteed by design, not % tested in production. 469B 2/8/2

ICS9562 Electrical Characteristics - PCICLK T A = - 7 C; V DD =3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O 33.33 MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH V OH@MIN =. V, V OH@MA = 3.35 V -33-33 ma Output Low Current I OL V OL @MIN =.95 V, V OL @MA =.4 V 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2.4 2.5 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2.25 2.5 ns Duty Cycle d t V T =.5 V 45 53 55 % Skew t sk V T =.5 V 22 5 ps Jitter,cycle to cycle t jcyc-cyc V T =.5 V 3 45 ps Guaranteed by design, not % tested in production. Electrical Characteristics - 48MHz, 24_48MHz T A = - 7 C; V DD =3.3V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O3 48 MHz Output Impedance R DSP3 V O = V DD *(.5) 2 55 Ω Output High Voltage V OH3 I OH = - ma 2.4 V Output Low Voltage V OL3 I OL = ma.55 V Output High Current I OH3 V OH@MIN =. V, V OH@MA = 3.35 V -29-23 ma Output Low Current I OL3 V OL @MIN =.95 V, V OL @MA =.4 V 29 27 ma Rise Time t r3a V OL =.4 V, V OH = 2.4 V. 2 ns Fall Time t f3b V OH = 2.4 V, V OL =.4 V.25 2 ns Duty Cycle d t3a V T =.5 V 45 52 55 % Jitter, cycle-to-cycle t jcyc-cyc3 V T =.5 V 2 35 ps Guaranteed by design, not % tested in production. 469B 2/8/2

ICS9562 Electrical Characteristics - SDRAM T A = - 7 C; V DD =3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Impedance R DSP5 Vo=V DD *(.5) 24 Ω Output Impedance R DSN5 Vo=V DD *(.5) 24 Ω Output High Voltage V OH5 I OH = - ma 2.4 V Output Low Voltage V OL5 I OL = ma.4 V Output High Current Output Low Current I OH5 I OL5 V OH@MIN = 2 V -46 V OH@MA = 3.35V -54 V OL@MIN = V 54 V OL@MA =.4V 53 ma ma Rise Time t r5 V OL =.4 V, V OH = 2.4 V.4..6 ns Fall Time t f5 V OH = 2.4 V, V OL =.4 V.4.75.6 ns Duty Cycle d t5 V T =.5 V 45 5 55 % Skew t sk5 V T =.5 V 3 25 ps Propagation delay SDRAM_IN to SDRAM t pdel5 V T =.5 V 2.95 4 ns Guaranteed by design, not % tested in production. Electrical Characteristics - REF T A = - 7 C; V DD =3.3V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O4 4.38 MHz Output Impedance R DSP4 V O = V DD *(.5) 2 6 Ω Output High Voltage V OH4 I OH = - ma 2.4 V Output Low Voltage V OL4 I OL = ma.4 V Output High Current I OH4 V OH@MIN =. V, V OH@MA = 3.35 V -29-23 ma Output Low Current I OL4 V OL @MIN =.95 V, V OL @MA =.4 V 29 27 ma Rise Time t r4 V OL =.4 V, V OH = 2.4 V.85 4 ns Fall Time t f4 V OH = 2.4 V, V OL =.4 V.95 4 ns Duty Cycle d t V T =.5 V 45 55.7 56 % Jitter, cycle-to-cycle t jcyc-cyc4 V T =.5 V 365 55 ps Guaranteed by design, not % tested in production. 469B 2/8/2 2

ICS9562 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 469B 2/8/2 3

ICS9562 Power Down Waveform ns 25ns 5ns VCO Internal 2 CPU MHz 3.3V 66MHz PCI 33MHz APIC 6.7MHz PD# SDRAM MHz REF 4.38MHZ 48MHZ Note. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for MHz 469B 2/8/2 4

ICS9562 INDE AREA N 2 D E A E h x 45 c α L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A 2.4 2.8.95. A.2.4.8.6 b.2.34.8.35 c.3.25.5. D SEE VARIATIONS SEE VARIATIONS E.3.68.395.42 E 7.4 7.6.29.299 e.635 BASIC.25 BASIC h.38.64.5.25 L.5.2.2.4 N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A 3 mil SSOP Package -C- - SEATING PLANE. (.4) C -34 VARIATIONS D mm. D (inch) N MIN MA MIN MA 48 5.75 6..62.63 Reference Doc.: JEDEC Publication 95, MO-8 Ordering Information ICS9562yFT Example: ICS y F - T Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 469B 2/8/2 5

ICS9562 INDE AREA N 2 D E E c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A --.2 --.47 A.5.5.2.6 A2.8.5.32.4 b.7.27.7. c.9.2.35.8 D E SEE VARIATIONS 8. BASIC SEE VARIATIONS.39 BASIC E 6. 6.2.236.244 e.5 BASIC.2 BASIC L.45.75.8.3 N SEE VARIATIONS SEE VARIATIONS α 8 8 aaa --. --.4 A2 A A -C- - VARIATIONS D mm. D (inch) N MIN MA MIN MA 48 2.4 2.6.488.496 Reference Doc.: JEDEC Publication 95, MO-53 e b SEATING PLANE -39 aaa C 6. mm. Body,.5 mm. pitch TSSOP (24 mil) (2 mil) Ordering Information ICS9562yGT Example: ICS y G - T Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 469B 2/8/2 6