Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen

What is Silicon on Insulator (SOI)? SOI silicon on insulator, refers to placing a thin layer of silicon on top of an insulator such as SiO2. The devices will be built on top of the thin layer of silicon. SOI technology first developed in the early 80s with military and power applications. Wider SOI adoption began with high-performance computing applications in the late 90s.

Bulk Silicon MOSFET vs. SOI MOSFET

Fully Depleted(FD) vs. Partially Depleted (PD) SOI Channel thickness decides the SOI type. PD: Thicker top layer, floating body. FD: Thinner top layer, Channel is fully depleted of charges.

Different Manufacturing Methods of SOI Seed Method the topmost Si layer is grown directly on the insulator. SIMOX - Separation by IMplantation of Oxygen uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer. Wafer bonding - the insulating layer is formed by directly bonding oxidized silicon with a second substrate. Smart Cut Method ELTRAN Nano Cleave

Seed Method - Silicon-On-Sapphire (SOS)

Separation by Implanted Oxygen (SIMOX) Typical BOX thickness: 100, 200, 400 nm SOI film thickness varies from ~50-240 nm

Wafer Bonding Smart Cut Method Step 1: Hydrogen implantation through thermal oxide dose ~1-5e16 cm-2 Step 2: Handle wafer B is bonded Step 3: At ~400-600 C wafer A separates from B at H2 peak Step 4: After splitting, SOI wafer (B) is annealed at 1100 C to strengthen the bond, whereas wafer A is reused. Remark: SOI film thickness set by H2 implant energy and BOX thickness.

Wafer Bonding Smart Cut Method

Issues with Bulk MOSFET Limited switching speed Long charging/discharging time on the parasitic capacitors Leakage current path Latch up

Issues with Bulk MOSFET Every time a transistor is turned on, it must first charge all of its internal (parasitic) capacitance before it can begin to conduct. The time it takes to charge up and discharge (turn off) the parasitic capacitance is much longer than the actual turn on and off of the transistor. If the parasitic capacitance can be reduced, the transistor can be switched faster.

Advantages of SOI - Reduce Parasitic Capacitance One of the major source of parasitic capacitance is from the source and drain to substrate junctions. SOI can reduced the capacitance at the source and drain junctions significantly by eliminating the depletion regions extending into the substrate. The thicker the SiO2, the smaller the parasitic capacitance.

Bulk MOS vs. SOI MOS Speed Comparison 37GHz Ring Oscillator SOI MOS is more than X2 faster than bulk MOS 85GHz

Advantages of SOI - Reduce Leakage Current Path The main difference in between Bulk and Depleted (fully or partially) device is the channel isolation.

Bulk MOS vs. SOI MOS Weak Inversion Current Leakage Bulk MOS SOI MOS On Id vs. Vds plot, SOI has order of magnitude of less leakage current in weak inversion region (Vgs<=Vth).

Bulk MOS vs. SOI MOS Latch UP Fig.1. CMOS inverter cross-section. Fig.2. Equivalent PNPN Thyristor. Latch up will be excited with I/V impulse injected into Vin/Vout/gnd pin. In Bulk CMOS, controlling space between each transistor or use guard ring to mitigate latch- up. However, by isolation circuit elements, SOI doesn t have latch up issue.

SOI Application 1. FD-SOI-based global positioning system (GPS) chip in smart watch. Unsurpassed battery life of 35 hours with the GPS turned on. 2. NXP General-purpose processor. Deep-sleep suspended power consumption of 15 µw, 17 times less in comparison to previous low-power bulk devices, 50 percent improvement on dynamic power efficiency.

References http://ece.iisc.ernet.in/~navakant/nano/2007/lecture23.pdf https://www.slideshare.net/kashishgrover3/soi-61262146?from_action=save http://www.csit-sun.pub.ro/courses/vlsi/carte_vlsi/bookch15.pdf https://www.slideshare.net/sindhureddy14/538-34932218 http://userweb.eng.gla.ac.uk/fikru.adamu-lema/chapter_06.pdf https://www.slideshare.net/mehdisimoussa/msmcmossoi http://electroiq.com/blog/2017/04/fd-soi-how-a-pioneering-technology-entered-mainstream-markets/ S. Deb, N. B. Singh, D. Das, A. K. De, and S. K. Sarkar, Analytical I V model of SOI and SON MOSFETs: a comparative analysis, International Journal of Electronics, vol. 98, no. 11, pp. 1465 1481, Nov. 2011. C.-T. Chuang, P.-F. Lu, and C. J. Anderson, SOI for digital CMOS VLSI: design considerations and advances, Proceedings of the IEEE, vol. 86, no. 4, pp. 689 720, Apr. 1998.