EEE5026; 943/U0280 Physical Design for Nanometer ICs 張耀文 Yao-Wen Chang ywchang@ntu.edu.tw http://cc.ee.ntu.edu.tw/~ywchang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Spring 2018 Administrative Matters Time/Location: Thursdays 2:20 pm--5:30 pm; BL-114 Instructor: Yao-Wen Chang E-mail: ywchang@ntu.edu.tw URL: http://cc.ee.ntu.edu.tw/~ywchang Office: BL-428. (Tel) 3366-3556; (Fax) 2364-1972 Office Hours: Wednesdays 4-5pm; other times by appointment Teaching Assistant: Yu-Sheng Lu (yslu@eda.ee.ntu.edu.tw); office hours: 12:30-1:30pm, Wednesdays Prerequisites: data structures, algorithms, and logic design Required Text: Either of the following two books: Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009 Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999 References: Selected reading materials from recent publications Unit 1 2 1
Teaching Assistant Yu-Sheng Lu 呂祐昇 Email: yslu@eda.ee.ntu.edu.tw Office: BL-406; Tel: 3366-3700 # 6406 Office Hours: 12:30-1:30pm, Wednesdays. 2 nd -year Ph.D. student Unit 1 3 Course Objectives Study techniques/algorithms for physical design (converting a circuit description into a geometric description) and their comparisons Study nanometer process/electrical effects and their impacts on the development of physical design tools Study problem-solving (-finding) techniques!!! solution S1 S2 S3 S4 S5 P1 P2 P3 P4 P5 P6 problem Unit 1 4 2
Course Contents VLSI design flow/styles and technology roadmap Physical design processes Partitioning Floorplanning Placement Routing (global, detailed, clock, and power/ground routing) Post-layout optimization Timing: timing modeling, performance-driven design Signal/power integrity: crosstalk, IR drop Design for manufacturability Process variation, optical proximity correction (OPC), chemical mechanical polishing (CMP), multiple pattering, e-beam, extreme ultraviolet (EUV), directed self-assembly (DSA), nanowire, etc. Design for reliability: antenna effect, redundant via, electromigration, thermal, etc. Machine learning based layout optimization Unit 1 5 Grading: Grading Policy Homework assignments + quizzes: 25% Programming assignments + lab: 25% One in-class open-book, open-note exam: 30% (June 28) Final project + presentation + demo: 20% (due June 21) A 1-page project proposal is due in-class on May 24 Could be research work, implementation, and/or literature survey Default project: Problem B, C, or E of the 2018 IC/CAD Contest at http://iccad-contest.org/tw/ (E for domestic undergraduate students) Teamwork is permitted (1--3 persons; preferably 2 persons) Bonus for class participation Homework: 30% per day penalty for late submission WWW: http://cc.ee.ntu.edu.tw/~ywchang/courses/pd/pd.html Academic Honesty: Avoiding cheating at all cost Unit 1 6 3
2018 CAD Contest @ ICCAD Default project: Problem B, C, or E of the 2018 IC/CAD Contest at http://iccad-contest.org/tw/ Teamwork is permitted (1--3 persons; preferably 2 persons) Unit 1 7 Unit 1: Introduction Course contents: Introduction to VLSI design flow/styles Introduction to physical design automation Semiconductor technology roadmap Readings W&C&C: Chapter 1 S&Y: Chapter 1 physical design fabrication Unit 1 8 4
IC Design & Manufacturing Process Unit 1 9 IC Design & Manufacturing Process (cont d) Unit 1 10 5
From Wafer to Chip 2, 4, 6, 8-inch wafers 8-inch vs. 1-inch ignot 12-inch wafer Apple A11 die (iphone 8) TSMC 10nm FinFET; 4.3B transistors; 87.66 mm 2 18-inch wafer Wafer dicing Wire bonding chips Unit 1 11 Apple A9 die for iphone 6s (1.85GHz; 5B+ transistors) Die, Package, and Board TSMC 16nm FinFET 104.5 mm 2 Samsung 14nm FinFET 96 mm 2 packages packages boards 6
IC Design Considerations Several conflicting considerations: Complexity: large number of devices/transistors Power: low-power consumption Performance: high-speed requirements Cost: die area, packaging, testing, etc. Time-to-market: about a 15% gain for early birds Others: manufacturability, reliability, testability, etc. Unit 1 13 Moore s Law: Driving Technology Advances Logic capacity doubles per IC at a regular interval (say, 18 months). G. Moore: Logic capacity doubles per IC every two years (1975). D. House: Computer performance doubles every 18 months (1975) 4Gb Itanium 2 Intel up 4004 8086 80386 PentiumPro Pentium 4 Itanium 2 Unit 1 14 7
Design Productivity Crisis Logic transistors per chip 10,000M 1,000M 100M 10M 1M 0.1M 0.01M 58%/yr compound complexity growth rate Complexity limiter 21%/yr compound productivity growth rate 100,000K 10,000K 1,000K 100K 10K 1K 0.1K Productivity in transistors per staff-month 1980 1985 1990 1995 2000 2005 2010 2015 Human factors may limit design more than technology. Keys to solve the productivity crisis: CAD (tool & methodology), hierarchical design, abstraction, IP reuse, platform-based design, etc. Unit 1 15 Old (1997) Technology Roadmap for Semiconductors Source: International Technology Roadmap for Semiconductors (easier to see the past & trend with the older version; for more recent update, see http://www.itrs2.net/). Deep submicron technology: node (feature size) < 0.25 m. Nanometer Technology: node < 100 nm. 14/16 nm technology was in production in 2015; 10 nm in 2016/2017 (5nm in 2020 by EUV?) Unit 1 16 8
Nanometer Design Challenges Apple A11 (iphone 8): technology node: 10 nm FinFET, P frequency 2.39 GHz, die size 87.66 mm 2, transistor count per chip 4.3B, wiring level 10+ layers, supply voltage < 1.0 V, power consumption < 16 W (?) Feature size : sub-wavelength lithography (impacts of process variation)? reliability? noise? wire coupling? Frequency, dimension : interconnect delay? electromagnetic field effects? timing closure? Chip complexity : large-scale system design methodology? Supply voltage : signal integrity (noise, IR drop, etc)? Wiring level : manufacturability? yield? 3D layout? Power consumption/density : power & thermal issues? Unit 1 17 Design Complexity Increases Dramatically!! Mixed-size Placement Routing & interconnect Unit 1 18 9
High IC Complexity Unit 1 19 Power Is a Key Limiting Factor for IC Design! Power density increases exponentially! Watts/cm 2 1000 100 10 1 Power doubles every 4 years 5-year projection: 200W total, 125 W/cm 2! i386 Hot plate i486 Pentium Nuclear Reactor Pentium Pro Pentium 4 Rocket Nozzle Itanium 2 Pentium III Itanium 2-DC Pentium II Power & Performance trade-off!! Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel. 10
Interconnect Dominates Circuit Performance!! 70 60 50 Worst-case interconnect delay due to crosstalk Delay (ps) 40 30 20 Interconnect delay 10 Gate delay 650 500 350 250 180 150 100 70 (nm) Technology Node Source: Synopsys In 0.18μm wire-to-wire capacitance dominates (C W >>C S ) C S C W Unit 1 21 Manufacturing with Optical Lithography Patterns on a mask are transferred onto a wafer Light source Illumination Lens Mask Projection Lens Immersion (water) R = k 1 λ / NA Wafer 0.25 * 193 nm / 1.35 = 36 nm R: resolution; k 1 : resolution constant (>= 0.25); λ: wavelength NA: numerical aperture = f(lens, refractive index) 22 11
Sub-Wavelength Lithography Gap Sub-wavelength lithography: use light of larger wavelength (193nm) to print features of smaller sizes [S. Borkar, MICRO 04] EUV E-beam 23 Technology Roadmap [Aitken, 2014] EUV + DSA envm NEMS CNT Patterning VNW EUV LELE monolithic Opto Log (complexity) PMOS NMOS Interconnect Transistors Planar CMOS LE, ~ LE, < HKMG Strain LELE FinFET Strong RET SADP LELELE III-V SAQP MLG, CNT HNW TSV EUV We Are Here EUV + DWEB AI wires CU wires 10nm 7nm 5nm 3nm 1975 1985 1995 2005 2015 2025 Source: R. Aitken @ ISPD 14 Keynote & S. Segars @ 2014 Kaufman Award dinner (with revision by ) 24 12
Most Expected Patterning Technologies Multiple patterning lithography (MPL) Extreme ultraviolet lithography (EUVL) Electron beam lithography (EBL) Directed Self- Assembly (DSA) Each technology has different difficulties and requires solutions for a breakthrough Litho-Etch-Litho-Etch (LELE) Double Patterning Pro: Simpler layout decomposition into masks Con: Overlay error with misalignment between masks 40nm 20nm 80nm 20nm 20nm 80nm = + mask 1 mask 2 photoresist mask Target film substrate mask 1 mask 2 1 st exposure-etching process 2 nd exposure-etching process 26 13
Extreme Ultraviolet Lithography (EUVL) EUVL is the most invested next-generation lithography technology Its wavelength is only 13.5 nm Reflective optical components and masks are used Reflective illuminator optics (mirrors) Reflective mask EUV source Reflective projection optics (mirrors) Wafer 27 Electron Beam Lithography (EBL) EBL is a maskless next-generation lithography technology Maskless: no more diffraction limitation of light Can define very fine patterns Mapper Lithography 28 14
Directed Self-Assembly (DSA) Block copolymer DSA for contact/via patterning Groups of contacts/vias are patterned by guiding templates with traditional 193i lithography Self-assembly block copolymer Topographical and chemical patterns Smaller and denser patterns Mask Template Contacts Contact patterning with DSA Contact patterns formed by various DSA templates [Xiao, et al., ASP-DAC 15] Cut/Via Pattering with DSA A large template can be used to pattern multiple close contacts even for sub-7nm nodes Layout close vias Vias 22nm Templates 7nm [Xiao, et al., DAC 14] 15
Reliability Becomes a 1st-Order Effect!! Reliability with 10-layer metal? m5 m1 m2 m3 m4 + + + + + + s g d Si substrate s g d [Courtesy: Dr. Patrick Groeneveld] Unit 1 31 3D IC TSV 3D Integration Adds Complexity! device substrate dielectric routing region heat sink thermal TSV signal TSV inter-layer dielectric metal layer device layer TSV-IO substrate tier 3 tier 2 tier 1 2.5D interposer (Xilinx Virtex-7 FPGA) Unit 1 32 16
Lower leakage power Performance gain at lower voltage Higher drive current 3D Transistor: FinFET 臺大演講網胡正明院士 3 fins Unit 1 33 Traditional VLSI Design Cycles 1. System specification 2. Functional design 3. Logic synthesis 4. Circuit design 5. Physical design 6. Fabrication 7. Packaging Other tasks involved: verification, simulation, testing, etc. Design metrics: area, speed, power dissipation, manufacturability, reliability, testability, design time, etc. Design revolution: interconnect (not gate) delay dominates circuit performance in deep submicron era. Interconnects are determined in physical design. Shall consider interconnections in early design stages. Unit 1 34 17
Traditional VLSI Design Cycle & verification & verification & simulation Unit 1 35 Traditional VLSI Design Flow (Cont'd) design Unit 1 36 18
Physical Design (PD) physical design fabrication PD converts a circuit description into a geometric description. The description is used to manufacture a chip. Physical design cycle: 1. Partitioning 2. Floorplanning 3. Placement 4. Routing (clock, power/ground, signal nets) 5. Post-layout optimization (buffering, sizing, etc.) Others: circuit extraction, timing verification and design rule checking Unit 1 37 Physical Design Flow B*-tree based floorplanning system Routing system Unit 1 38 19
Floorplan Examples Apple A5 with dual ARM cores Intel Pentium 4 A floorplan with interconnections Unit 1 39 VLSI Placement Place objects into a die s.t. no objects overlap with each other & some cost metric (e.g., wirelength) is optimized chip ISPD98 ibm01 842K cells 646 macros 868K nets 12,752 cells 247 macros A max /A min = 8416 wirings among cells/macros are not shown here!! 40 20
Routing Example 0.18um technology, two layers, pitch = 1 um, 8109 nets. Unit 1 41 Modern EDA & Circuit Design Challenges Scalability Multi-dimension Heterogeneity Technology 21
High complexity Millions of objects Example: Modern Placement Scalability Placement constraints Blockage, routability, density, timing, region, etc. Multi-dimension Mixed-size placement Thousands of big macros with millions of small cells Heterogeneity More: 3D IC, datapath, FPGA, etc. Technology TSV 2.5M placeable objects mixed-size design Macros have revolutionized SoC design device TSV dielectric routing region substrate Design Styles Power Others Structure ASIC FPGA SPLD Unit 1 44 22
SSI/SPLD Design Style Unit 1 45 Full-Custom Design Style Designers can control the shape of all mask patterns. Designers can specify the design up to the level of individual transistors. Unit 1 46 23
Terminology Cell: a logic block used to build larger circuits. Pin: a wire (metal or polysilicon) to which another external wire can be connected. Nets: a collection of pins which must be electrically connected. Netlist: a list of all nets in a circuit. nets pin cells Unit 1 47 Standard-Cell Design Style Selects pre-designed cells (typically, of the same height) to implement logic Over-the-cell routing is pervasive in modern designs Modern designs often contain cells of different row heights (esp. with FinFET transistors) Unit 1 48 24
Standard Cell Example Over-the-cell routing is pervasive in modern designs Courtesy of Newton/Pister, UC-Berkeley Unit 1 49 Gate Array Design Style Prefabricates a transistor array Needs wiring customization to implement logic Unit 1 50 25
FPGA Design Style Logic and interconnects are both prefabricated. Illustrated by a symmetric arraybased fieldprogrammable gate array (FPGA) Unit 1 51 FPGA/CPLD Examples Xilinx XC4413 FPGA (0.35 um) Altera Stratix IV FPGA (40 nm) 52 26
FPGA Design Process Illustrated by a symmetric array-based FPGA No fabrication is needed Unit 1 53 Comparisons of Design Styles Full custom Standard Cell Gate array FPGA Cell size variable fixed height fixed fixed Cell type variable variable fixed programmable Cell placement variable in row fixed fixed Interconnection variable variable variable programmable Full custom Standard Cell Gate array FPGA Fabrication time - - - - - + +++ Packing density +++ ++ + - - - Unit cost (large quantity) +++ ++ + - - - Unit cost (small quantity) --- -- - +++ Easy design & simulation --- -- - ++ Easy design change --- -- - +++ Timing simulation accuracy -- - - ++ Chip speed +++ ++ + --- Unit 1 54 27
Design Style Trade-offs 10 4 full custom 10 3 Turnaround Time (Days) 10 2 semicustom 10 SPLD CPLD FPGA 1 SSI optimal solution 1 10 10 2 10 3 10 4 10 5 10 6 10 7 10 8 Logic capacity (Gates) Unit 1 55 Appendix: Structured ASIC Unit 1 56 28
Structured ASIC A structured ASIC consists of predefined metal and via layers, as well as a few of them for customization. The predefined layers support power distribution and local communications among the building blocks of the device. Advantages: fewer masks (lower cost); easier physical extraction and analysis. Popular for engineering change orders (ECO s) A structured ASIC (M5 & M6 can be customized) Faraday s 3MPCA structured ASIC (M4--M6 can be customized) Unit 1 57 Comparisons of Design Styles Full custom Standard Cell Gate array Structure ASIC FPGA Cell size variable fixed height fixed fixed fixed Cell type variable variable fixed fixed programmable Cell placement variable in row fixed fixed fixed Interconnection variable variable variable variable/fixed programmable Full custom Standard Cell Gate array Structure ASIC FPGA Fabrication time - - - - - + ++ +++ Packing density +++ ++ + - - - - Unit cost (large quantity) +++ ++ + - - - - Unit cost (small quantity) --- -- - + +++ Easy design & simulation --- -- - + ++ Easy design change --- -- - + +++ Timing simulation accuracy -- - - + ++ Chip speed +++ ++ + - --- Unit 1 58 29