Digitally Assisted Radio-Frequency Integrated Circuits

Digitally Assisted Radio-Frequency Integrated Circuits by David Stewart A thesis submitted to the Department of Electrical and Computer Engineering in conformity with the requirements for the degree of Master of Applied Science Queen s University Kingston, Ontario, Canada July 2013 Copyright c David Stewart, 2013

Abstract In this thesis, three radio frequency integrated circuits (RFICs) were digitally assisted for varying signal power, frequency or both. Performance paramters were optimized in the sense of obtaining the best performance improvement possible through the methods used. The digital assist method used a lookup table (LUT) of optimal bias points measured through extensive sweeps and linear interpolation to determine the optimal bias point of the chip between measured points. A Gilbert Cell was fabricated in 0.13 µm CMOS. Transistor gate bias voltages were swept with input power to find the optimal bias voltages for intermodulation distortion (IMD) performance. A power detector was on-chip for the digital assist. Linear interpolation was used to optimize biases for any input power between initially measured points. Whereas distortion generally increases with input power, the digitally assisted device reduced the distortion of large signals. The IIP3 was 2.83 dbm from -3.11 dbm, and the P1dB was -3.33 dbm from -12.06 dbm. The RF bandwidth was measured as 1 to 12 GHz and DC power consumption varied from 2.06 to 3.27 mw. A noise cancelling low noise amplifier (LNA) was designed and fabricated in 0.13 µm CMOS. A feedback capacitor was used to boost the gain of the input transistor for lower DC power and better S 11. An on-chip frequency detector was implemented i

for the digital assist. The gain rolled off gradually from 1 GHz until the 3 db cutoff at 7 GHz. The average noise figure was 4.1 db and less than 5 db across the band. With digital assist, the gain curve was flattened at about 15 db with to a broader 8 GHz bandwidth without negatively affecting the noise figure. The S 11 was below -12 db. A power amplifier (PA) previously designed in 0.8 µm Gallium Nitride (GaN) used third order IMD cancellation by derivative superposition effective at a fixed frequency and output power. Digital assist eliminated the extreme sensitivity to variations. Digital assist and bilinear interpolation maintained a 10 db improvement in OIP3 over the entire 1 to 6 GHz band for varying output power between 21 and 24 dbm. ii

Acknowledgments There are a number of people I would like to thank without whom this thesis would not be possible. First and foremost, I would like to thank Professor Carlos Saavedra for all the support and guidance throughout my Master s studies that one could reasonably ask of a supervisor and more. Other big figures: Thanks are due to Professor Al Freundorfer, one of my favourite teachers in undergraduate and graduate studies, a real inspiration. Many thanks are due to Patricia Greig for her special role in helping with measurements and to Greg MacLeod for his help with the computing side of things. I would like to thank all my friends and colleagues for putting up with my insecurities, for their kind encouragement, and for their generous help. Especially, I would like to thank Ahmed El-Gabaly and Shan He for sharing their knowledge and experience having come through before me. I would like to thank my friends and colleagues Jeet Mondal, Fan Jiang, Hao Li, Mahdi Mohsenpour, and Wen Li for the good times together making for an enjoyable time in Kingston. I would like to thank my family, especially my mother and father for all the financial support and encouragement to keep pressing toward the goal. iii

Contents Abstract Acknowledgments Contents List of Tables List of Figures Nomenclature i iii iv vii viii xiii Chapter 1: Introduction 1 1.1 Preliminary Concepts........................... 1 1.2 List of Contributions........................... 4 1.3 Thesis Organization............................ 6 Chapter 2: Literature Review 8 2.1 Introduction................................ 8 2.2 Gilbert Cell................................ 8 2.3 Power Detection.............................. 14 2.4 Noise Cancellation............................ 16 2.5 Distortion Cancellation by Derivative Superposition.......... 18 2.6 Conclusion................................. 20 Chapter 3: Gilbert Cell Mixer With Power Detector and Digital Control 22 3.1 Introduction................................ 22 3.2 Concept of the Mixer and Power Detector............... 24 3.3 Circuit Design............................... 26 3.3.1 Gilbert Cell Mixer........................ 26 3.3.2 Power Detector.......................... 27 iv

3.3.3 Off-Chip Devices......................... 28 3.3.4 Initial Data Gathering...................... 30 3.3.5 Digital Control Algorithm.................... 34 3.4 Experimental Results........................... 37 3.4.1 Experimental Setup........................ 37 3.4.2 Power Detector.......................... 38 3.4.3 Testing for Optimum Bias Voltages............... 39 3.4.4 Baseline Gilbert Cell Performance................ 45 3.4.5 Improvement with Digital Assist................. 50 3.5 Conclusion................................. 52 Chapter 4: Noise Cancelling Amplifier with Frequency Detector and Digital Control 53 4.1 Introduction................................ 53 4.2 Concept of the Noise Cancelling Amplifier and Frequency Detector.. 55 4.3 System Design and implementation................... 56 4.3.1 Noise Cancelling Amplifier.................... 56 4.3.2 Frequency Detector........................ 61 4.3.3 Digital Assist........................... 64 4.4 Experimental Results........................... 66 4.4.1 Fabrication and Experimental Setup.............. 66 4.4.2 Testing for Optimum Bias Voltages............... 67 4.4.3 Test and Measurement...................... 67 4.5 Conclusion................................. 77 Chapter 5: Digitally-Assisted Distortion Cancellation in a Gallium Nitride (GaN) Power Amplifier 78 5.1 Introduction................................ 78 5.2 Implementation of Digital Assist..................... 81 5.2.1 Concept of Digital Assist..................... 81 5.2.2 Bilinear Interpolation....................... 83 5.2.3 Active Low Pass Filters for Digital to Analog Conversion... 87 5.2.4 Efficiency Effect of Digital Assist System............ 88 5.3 Experimental Results........................... 89 5.3.1 Measurement Procedure..................... 89 5.3.2 Testing for Optimum Bias Voltages............... 90 5.3.3 Measured Results......................... 90 5.4 Conclusion................................. 96 Chapter 6: Summary and Conclusions 98 6.1 Summary................................. 98 v

6.2 Future Work................................ 101 Bibliography 103 vi

List of Tables 3.1 Summary of Component Values for the Mixer............. 27 3.2 Summary of Broadband Mixer Performance and Improvement with Digital Assist............................... 51 4.1 Summary of Component Values for the LNA.............. 57 4.2 Summary of LNA Performance and Improvement with Digital Assist 76 5.1 Summary of Broadband PA Characteristics............... 96 vii

List of Figures 1.1 Block diagram of a typical heterodyne receiver............. 2 1.2 Block diagram of a typical heterodyne transmitter........... 3 1.3 Superheterodyne receiver with digital assist.............. 4 2.1 The single balanced mixer........................ 9 2.2 The Gilbert Cell mixer.......................... 12 2.3 Principle diagram showing the concept of the power detector from [1] 16 2.4 Basic noise cancelling circuit schematic................. 17 2.5 The g m3 plot of a basic common source transistor........... 19 2.6 Basic distortion cancellation circuit using the method of derivative superposition................................ 20 3.1 Gilbert Cell mixer schematic....................... 24 3.2 A block diagram of the mixer and bias control system......... 26 3.3 RC LPF used after PWM........................ 28 3.4 Model of the off-chip IF output buffer at the IF frequency used in simulation................................. 29 3.5 The main VI used to automatically vary bias voltages while recording two-tone test IF traces.......................... 30 3.6 Sample trace recorded by the LabVIEW VI.............. 31 viii

3.7 Front panel of the main VI used to automatically sweep bias voltages 31 3.8 Sub VI used to set the DC bias voltages for initial sweeps....... 32 3.9 Sub VI used to record the spectrum analyzer trace showing IF output from initial sweeps............................ 33 3.10 Sub VI used to name each IF output trace recorded from initial sweeps 33 3.11 A graphical depiction of a linear interpolation from measured (X,Y) points represented by circles with Y out as the variable to be interpolated given X in as the input variable...................... 34 3.12 Block diagram of the digital assist algorithm.............. 35 3.13 Photograph of fabricated CMOS mixer and power detector...... 37 3.14 A plot of the output voltage produced by the power detector for varying input power at different frequencies................... 38 3.15 Simulated conversion gain with varying (V B1,V B2 ) and with V LO fixed at 600 mv with -24 dbm RF input power............... 39 3.16 Simulated OIP3 extrapolated from IF and IMD3 value at -24 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 600 mv.. 40 3.17 Simulated conversion gain with varying (V B1,V B2 ) and with V LO fixed at 600 mv with -18 dbm RF input power............... 41 3.18 Simulated OIP3 extrapolated from IF and IMD3 value at -18 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 600 mv.. 42 3.19 Measured conversion gain with varying (V B1,V B2 ) and with V LO fixed at 540 mv with -24 dbm RF input power............... 42 3.20 Measured OIP3 extrapolated from IF and IMD3 value at -24 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 540 mv.. 43 ix

3.21 Measured conversion gain with varying (V B1,V B2 ) and with V LO fixed at 540 mv with -18 dbm RF input power............... 44 3.22 Measured OIP3 extrapolated from IF and IMD3 value at -18 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 540 mv.. 44 3.23 Conversion Gain at -24 dbm input power versus RF frequency.... 46 3.24 Plot of P1dB of the mixer without digital assist at 4 GHz RF.... 46 3.25 Plot of fundamental and IMD3 output power versus input power of uncontrolled mixer at 4 GHz RF..................... 47 3.26 Plot showing the variation of DC power with input power in the range of digitally assisted variation of gate bias................ 48 3.27 The LO to RF isolation versus RF frequency.............. 48 3.28 Differential S 11 of the downconversion mixer.............. 49 3.29 Plot of fundamental and IMD3 output power versus input power of mixer with gain controlled by digital means at 4 GHz RF....... 50 3.30 Plot of P1dB of the mixer with digital control............. 51 4.1 Block diagram of LNA optimization system including the frequency detector and microcontroller....................... 55 4.2 Noise Cancelling Amplifier schematic.................. 57 4.3 Schematic simulation result of the S 21 of the LNA with and without L g3 and L s3................................ 58 4.4 Schematic simulation result of the noise figure of the LNA with and without L g3 and L s3........................... 59 4.5 Schematic simulation result of the S 11 of the LNA with and without L s3 60 4.6 Concept of frequency detection..................... 62 x

4.7 A single differenctial amplifier stage................... 63 4.8 A single 3 differential amplifier section with active feedback..... 63 4.9 Differential input power detector stage in frequency detector..... 64 4.10 Block diagram of LNA digital assist algortihm............. 65 4.11 Chip layout of LNA and frequency detector in Virtuoso........ 68 4.12 Chip photograph of LNA and frequency detector............ 69 4.13 Frequency detector DC voltage output versus frequency........ 70 4.14 S 21 curves of controlled LNA versus constant optimum bias for 4 GHz frequency................................. 70 4.15 S 11 curves of controlled LNA versus constant optimum bias for 4 GHz frequency................................. 71 4.16 S 22 curves of controlled LNA versus constant optimum bias for 4 GHz frequency................................. 72 4.17 Noise figure characteristics of controlled LNA versus constant optimum bias for 4 GHz frequency......................... 73 4.18 P1dB measurement at 4 GHz frequency................. 74 4.19 P1dB measurement up to 8 GHz with 1 GHz spacing between points 74 4.20 IP3 measurement at 4 GHz frequency.................. 75 4.21 OIP3 measurement from 3 to 8 GHz with 1 GHz spacing between points 76 5.1 Schematic of GaN power amplifier proposed in [2]........... 79 5.2 Schematic of GaN power amplifier with distortion cancellation.... 80 5.3 Block diagram of the digital assist.................... 81 5.4 Flow chart showing the control algorithm................ 82 xi

5.5 Known optimal bias voltages on Cartesian coordinates as hollow circles and the interpolated bias voltage for actual (P in, f in ) as a partially filled circle.................................... 84 5.6 Bias voltages linearly interpolated for power with fixed frequencies as solid circles................................ 85 5.7 Optimal bias voltage for (P in, f in ) interpolated linearly for frequency from points previously interpolated for power............. 85 5.8 Schematic of active low pass filter using LM741 op amp........ 88 5.9 Measured OIP3 versus f at 22 dbm with bias voltages optimized for 1 GHz used for DC-PA.......................... 91 5.10 Measured OIP3 versus f at 22 dbm with bias voltages optimized for 6 GHz used for DC-PA.......................... 92 5.11 Measured OIP3 versus P out at 1 GHz with optimum bias voltages at 22 dbm and 1 GHz used for DC-PA................... 93 5.12 Measured OIP3 versus P out at 1.5 GHz with optimum bias voltages at 22 dbm and 1 GHz used for DC-PA................... 93 5.13 Measured OIP3 versus P out at 3 GHz with optimum bias voltages at 22 dbm used for DC-PA......................... 94 5.14 Measured OIP3 versus P out at 6 GHz with optimum bias voltages at 22 dbm used for DC-PA......................... 94 5.15 Measured OIP3 versus P out at 5.5 GHz with optimum bias voltages at 22 dbm used for DC-PA......................... 95 xii

Nomenclature Acronym AC ADC BP F CM OS CP F C CP W DAC DADC P A Meaning Alternating Current Analog to Digital Conversion/Converter Bandpass Filter Complementary Metal Oxide Semiconductor Canadian Photonics Fabrication Centre Coplanar Waveguide Digital to Analog Conversion/Converter Power Amplifier With Digitally Assisted Distortion Cancellation DC DC P A Direct Current Power Amplifier With Constant-Biased Distortion Cancellation DS GaN GSG GSGSG Derivative Superposition Gallium Nitride Ground Signal Ground Ground-Signal-Ground-Signal-Ground xiii

HF ET IC IF IIP 3 IM D IM D3 IP 1dB IP 3 LA LN A LO LP F LU T M OSF ET N F N M OS OIP 3 OP 1dB P 1dB P A P W M RC RF RF IC Heterostructure Field-Effect Transistor Integrated Circuit Intermediate Frequency Input-Referred IP3 Intermodulation Distortion Third Order IMD Input-Referred P1dB Third Order Intercept Point Limiting Amplifier Low Noise Amplifier Local Oscillator Low Pass Filter Look-Up Table Metal Oxide Semiconductor Field-Effect Transistor Noise Figure N-Type Metal Oxide Semiconductor Output-Referred IP3 Output-Referred P1dB 1 db Compression Point Power Amplifier Pulse Width Modulation Resistor-Capacitor Radio Frequency Radio Frequency Integrated Circuit xiv

RM S ROM V I Root Mean Square Read Only Memory (LabVIEW) Virtual Instrument xv

1 Chapter 1 Introduction 1.1 Preliminary Concepts There is a demand for fast, robust, and low-cost wireless devices. Important performance parameters of radio frequency (RF) devices include increased bandwidth to make use of a broader spectrum, low noise figure, improved linearity, and reduced power consumption. Generally, a tradeoff is required to meet these needs, and once an RF integrated circuit (RFIC) chip is fabricated and bias voltages fixed, there is no more finetuning. However, performance parameters after fabrication may still be dependent on either input signal power or frequency. An advantage of processing information such as a signal power or frequency in the digital domain is that there is no loss of information between the digitized input and output. This thesis aims to explore how this could be useful to optimization of analog RF devices in the sense of obtaining the best improvement of a given performance parametric possible through the methods demonstrated. Analog RFICs have certain key performance parameters depending on their role

1.1. PRELIMINARY CONCEPTS 2 Antenna Mixer Demodulator RF Filter LNA Image Reject Filter Channel Select Filter IF Amplifier LO Figure 1.1: Block diagram of a typical heterodyne receiver in the receiving or transmitting path of an RF transceiver. Figure 1.1 shows a typical superheterodyne receiver, which is the most widely used receiver architecture. The low noise amplifier (LNA), for example, is needed to amplify the signal above the noise level for later stages. The noise figure of m cascaded gain stages is given by the following well-known relation: NF total = 1 + (NF 1 1) + NF 2 1 G 1 + + NF m 1 G 1 G m 1 (1.1) Therefore, in order to optimize the effectiveness of the LNA in its role, the gain needs to be high while the noise figure is kept at a minimum. For a broadband system, obviously, the LNA needs to be broadband itself. The first downconversion mixer in the RF receiving path has other concerns. I.e. the effect of intermodulation distortion (IMD) contributed by the mixer, the relative lack of which from here on will be referred to as the mixer linearity, is more critical than that of the LNA. As well, the power amplifier (PA) in the transmitting path

1.1. PRELIMINARY CONCEPTS 3 Mixer Antenna Modulator BPF BPF PA BPF LO Figure 1.2: Block diagram of a typical heterodyne transmitter requires high power gain, power efficiency, and linearity. Because of its role, the placement of the PA is, like the LNA in the receiving path, close to the antenna as shown in the typical superheterodyne transmitter block diagram shown in in Figure 1.2. Much research has been done regarding improvement to the key performance parameters without degrading other important parameters or at least to find the most suitable tradeoff. The best techniques require only a few small additional circuit elements such as transistors rather than large, bulky elements such as on-chip inductors. Such circuits have the advantage of being able to set a gate bias voltage from off-chip in order to manipulate the device characteristics. However, these optimization techniques not only involve tradeoffs, but they often degrade with variations in the signal. This is where digital assist can be useful. The block diagram shown in Figure 1.3 shows an example of how the receiver could be improved by controlling bias voltages for varying signal power and frequency by digital means using a microcontroller.

1.2. LIST OF CONTRIBUTIONS 4 DACs Microcontroller ADCs Bias Voltages Bias Voltages Antenna Frequency Detector Power Detector Demodulator RF Filter LNA Image Reject Filter Mixer Channel Select Filter IF Amplifier LO Figure 1.3: Superheterodyne receiver with digital assist By sensing a characteristic of the RF signal frequency, power, or both the characteristic can be converted into a digital representation and digital assist techniques can be used by varying transistor gate bias voltages. This can be done by using digital to analog conversion (DAC) to output an optimal bias voltage into the analog domain. 1.2 List of Contributions In this thesis, the contributions are mainly to the development of digital assist of RF devices for optimization of key RFIC performance parameters. Each of the devices were assisted by varying transistor gate bias voltages using a single digital microcontroller unit, the PIC18F87J11 by Microchip Technology Inc. In an RF transceiver

1.2. LIST OF CONTRIBUTIONS 5 implementation, this means that the same unit could assist multiple analog devices. In each implementation, an interpolation routine was used in the microcontroller for finding the best bias by doing calculations with the digitized detector outputs. The first contribution presented in this thesis is a mixer demonstrating a reduction in intermodulation distortion through input power detection and digtal assist. The digital assist is implemented with a linear interpolation mechanism and look-up table (LUT), which shows that the bias voltages can be optimally adjusted for any input power. The input-referred third order intercept point (IIP3) was extended from -3.11 dbm to 2.83 and the IP1dB was improved from -12.06 to -3.33 at 4 GHz RF using this method. The second contribution is an amplifier with low noise and good impedance matching over a broad band with a flattened measured gain curve and 1 GHz increased 3 db bandwidth through frequency detection and digital assist without negatively affecting the noise figure. The bandwidth was extended from 7 to 8 GHz while the gain curve was flattened for the entire bandwidth at about 15.2 db while maintaining a low noise figure consistently below 5 db with an average of 4.1 db over the extended bandwidth and a low S 1 1 consistently below -12 db. The third contribution is an optimization of distortion cancelling of a power amplifier for a wide range of input power levels and frequencies such that the otherwise high sensitivity of the derivative superposition technique is mitigated. This greatly extends the usefulness of the derivtive superposition technique for improving linearity. A bilinear interpolation technique has demonstrated that the distortion cancellation can be maximized for any combination of signal power or frequency by computation in the digital device. OIP3 was significantly improved by 10 db for a wide range of

1.3. THESIS ORGANIZATION 6 frequencies from 1 to 6 GHz and output power levels from 21 to 24 dbm. 1.3 Thesis Organization The thesis is organized as follows: Chapter 2 gives a general introduction to relevant MOSFET circuits and techniques that are used to improve key performance parameters. It begins with a description of Gilbert Cells and power detectors in CMOS followed by cancellation techniques for mitigating noise and distortion in transistor amplifiers. Chapter 3 presents a Gilbert Cell downconversion mixer with on-chip power detection and digital assist. The digital assist used with the Gilbert Cell in order to reduce third order intermodulation distortion (IMD3) at high input power levels is described. The linear interpolation technique for determining the optimum gate bias voltage for a variable control signal is introduced. The chapter is concluded with the measured results of both the baseline mixer and the mixer with digital assist. Chapter4 presents a broadband LNA with frequency detection and digital assist. The design of both the LNA and frequency detector are discussed. The digital assist used to control the gain while keeping the noise figure at a minimum to increase the device bandwidth as well as maintain a consistent gain for all frequencies of operation is described in detail. The chapter concludes with a comparison of the LNA with digital assist to the baseline LNA performance. Chapter 5 presents a digital assist technique used to improve the linearity performance of a PA with derivative superposition in 0.8 µm Gallium Nitride (GaN) technology designed by Ahmed M. El Gabaly, a previous member of the group [2]. The bilinear interpolation method used to determine optimal bias voltages for both

1.3. THESIS ORGANIZATION 7 varying frequency and power is described. The measured performance of the PA with distortion cancellation and digital assist is compared to the PA with only distortion cancellation. Chapter 6 is the conclusion to this thesis. A summary of the contents is included along with a discussion of possible improvements and future work.

8 Chapter 2 Literature Review 2.1 Introduction This chapter provides a basic overview of the concepts that will be built upon in later chapters. Since this thesis focuses on digital assist techniques, and since they were used on an active mixer, a low noise amplifier, and a power amplifier all for distinct uses, this chapter will give an overview of these three circuits and their uses. 2.2 Gilbert Cell The Gilbert Cell [3] is a type of frequency mixer. That is to say that, in the time domain, it multiplies two time domain signals to achieve mixing in the frequency domain. Since a linear time invariant system cannot achieve frequency mixing, the CMOS mixers presented here use the nonlinearity of NMOS transistors. Every mixer requires not only an input at the RF input frequency, but a strong local oscillator (LO) frequency as well. In the case of the Gilbert Cell used as a downconversion

2.2. GILBERT CELL 9 V DD V DD R L R L + V - out V LO + - M 2 M 3 M 1 V RF Figure 2.1: The single balanced mixer mixer, the output intermediate frequency (IF) is the difference between the RF and LO frequencies. The Gilbert Cell works by building on the principle of the single balanced mixer [4]. It is good to know how a single balanced mixer functions in order to more easily understand the working of Gilbert Cell. Therefore, it serves here as the first example of the mixing concept that has been briefly described. A schematic diagram of the single balanced mixer is shown in Figure 2.1. The RF transconductor is M 1 while the LO signal is provided to opposite transistors M 2 and M 3. One may notice that the schematic looks very similar to that of a basic

2.2. GILBERT CELL 10 differential amplifier with a current source controlled by the RF signal rather than a DC current source. By using a strong LO signal, such as one with 0 dbm of power, all of the current proportional to the RF signal can be steered through one of the two load resistors with the rate of alternation between them being controlled by the LO signal. This effectively produces an output through multiplication of the RF current by a square wave at the LO frequency: i out (t) = sgn[cos(ω LO t)]{i DC + I RF cos(ω RF t)} (2.1) Since the LO switching effectively multiplies by a square wave, the multiplication involves some odd harmonics on the part of the LO. An ideal squarewave of amplitude 1 centred at zero such as that multiplied by the RF signal in Equation (2.1) can be expanded into the following series showing the odd harmonics comprising the square wave besides the fundamental frequency: sgn[cos(ω LO t)] = 4 π (cos(ω LOt) + frac13 cos(3ω LO t) + frac15 cos(5ω LO t) +...) (2.2) The first term of the series is the dominant one. Therefore, the IF frequency is found by multiplying the first term by the tail current and applying a trigonometric identity: i IF (t) = 4 π cos(ω LOt)I RF cos(ω RF t) = 2I RF π (cos(ω RF t ω LO t) + cos(ω RF t + ω LO t)) (2.3) By recognizing that the current I RF is dependent on the RF voltage at the gate of transistor M 1 through I RF = g m V RF (2.4)

2.2. GILBERT CELL 11 and produces an output voltage with each R L by Ohm s law. The conversion gain of the mixer can be found by using equation 2.1 and it is [5] CG = 2 π g mr L. (2.5) One major disadvantage of the single balanced mixer is that there is poor LO to IF isolation as can be seen from equation (2.1) because the DC current is multiplied by the LO sign at the output as well as the RF current. The LO feedthrough is significantly large due to requirement of a strong LO signal. Therefore, the single balanced mixer may require special filtering to avoid overload of successive stages. The Gilbert Cell builds on the principle of the single balanced mixer. Its schematic diagram is shown in Figure 2.2. It basically consists of two single balanced mixers with a common current source. One obvious advantage of this setup is that, while the IF output currents of the two single balanced mixers complement one another, the LO feedthrough of each opposes the other and they therefore cancel, which mitigates the requirement for special filtering of the LO frequency from the IF output. As well, the Gilbert Cell is a double balanced mixer with fully differential input RF and LO as well as a differential IF output. However, the IMD3 is still a problem, and the noise figure for Gilbert Cells is typically high. The Gilbert Cell shown in Figure 2.2 is the most frequently used mixer in modern RFICs used in telecommunications applications. The design is based on two singlebalanced mixers to cancel the strong LO frequency signal that would appear at the output of a single balanced mixer. Therefore, the Gilbert Cell provides a greatly improved RF to LO isolation from the single balanced mixer.

2.2. GILBERT CELL 12 V DD V DD R L - V out + R L V LO+ M 3 M 4 M 5 M 6 V LO+ V LO- V RF+ M 1 M 2 V RF- I DC Figure 2.2: The Gilbert Cell mixer The conversion gain of the Gilbert Cell can be calculated as the combined conversion gain of the two halves, which are basically single balanced mixers. Each of the currents through the positive and negative connected RF input transistors can be expressed as follows: I RF + = g m V RF + = g m V RF 2 (2.6) I RF = g m V RF = g m V RF 2 (2.7)

2.2. GILBERT CELL 13 By using equation (2.3), each output current can be expressed as the following: i out+ (t) = g mv RF π (cos(ω RF t ω LO t) + cos(ω RF t + ω LO t)) (2.8) i out (t) = g mv RF π (cos(ω RF t ω LO t) + cos(ω RF t + ω LO t)) (2.9) By applying Ohm s law and taking the difference of the two equations, the following output voltage results: V out = 2 π g mr L V RF [(cos(ω RF t ω LO t) + cos(ω RF t + ω LO t))] (2.10) Clearly, the conversion gain as can be seen from this equation as the same as the conversion gain of the single balanced mixer as shown in equation (2.5). Linearity of the Gilbert Cell Active CMOS mixers such as the single balanced and Gilbert Cell mixers described in this chapter provide conversion gain and often improved noise performance compared to passive mixers. However, this comes as a tradeoff with significantly increased intermodulation distortion, the sources of which are the switching pair and the transconductor. It is shown in [6] that the transconductor nonlinearity is the primary contsraint of intermodulation distortion performance especially with low bias current. With regard to the intermodulation distortion contribution of the switching stage, an optimal LO power exists particularly at high frequencies since a strong LO signal makes for faster switching, but too much LO power results in degrading the linearity of the switching stage. No more LO power should be used than what is required to provide reliable switching. One advantage of the Gilbert Cell when it comes to intermodulation distortion is that, unlike the

2.3. POWER DETECTION 14 single balanced mixer, it is balanced at all ports, and so there is cancellation of the even-ordered distortion products. Another advantage that the strong LO component present at the output of a single balanced mixer is cancelled. Gilbert Cell mixers have been in use for decades [3]. Newer variations exist as well. Variations with variable conversion gain have been presented in literature [7] [8]. Even distortion cancellation has been proposed for the Gilbert Cell [9]. A low noise version using thermal noise cancellation in the transconductor stage was presented in [10]. Gilbert Cell designs have been proven to work at very high frequencies and bandwidths with CMOS technology [11] [12] [13]. 2.3 Power Detection Power detection circuits exist that are relatively easy to implement in CMOS and consume little additional power. The following is an overview of the basic principle of the most common amplitude detection method for RF. MOSFET as an Amplitude Detector A transistor in the common source configuration is a nonlinear device that can be used for power detection by measuring the DC offset of the drain voltage caused by the input amplitude. The long channel MOSFET equation is adequate to demonstrate this principle: I D = 1 W 2 k n L (V GS + v gs cos(ωt) V t ) 2 (2.11) = 1 W 2 k n L (V GS) 2 + k n W L (V GS V t )v gs cos(ωt) + 1 W 2 k n L v2 gs cos 2 (ωt) (2.12) The first term of equation (2.12) is dependent only on the DC bias voltage and

2.3. POWER DETECTION 15 not directly on the input power. It is referred to as I bias for simplicity. The second term is dependent on the amplitude of the input signal, but since it is a linear term with no even ordered exponent, it produces no DC offset. Normally, the third term is ignored when deriving a small singal model. However, it does have an effect with the large signals that the transistor would be made to detect. This term depends on the square of the input signal, which has a positive DC average that depends on the magnitude. By using sufficient filtering, the square term of v gs can be used for power detection as can be seen when equation (2.12) is expanded further: I D = I DC + k n W L (V GS V t )v gs cos(ωt) + 1 W 4 k n L v2 gs cos(2ωt) + 1 W 4 k n L v2 gs (2.13) There are two DC terms in the resulting equation and two terms with a DC average of zero. By cancelling or ignoring the DC term caused by the constant gate bias and by filtering the fundamental input RF tone and its second order harmonic, the only term left is DC and depends only on the RF input amplitude. A principle diagram of a basic power detector circuit shown in Figure 2.3 shows how a common source transistor can be used to detect the amplitude of a sensed signal. This type of differential pair-like detector was originally proposed using bipolar transistors by Meyer, and the technique was demonstrated with both root mean square (RMS) and peak detectors [14] [15]. The technique has been applied using the square law behaviour of CMOS transistors as well [1]. The circuit is symmetrical except that the transistor M 2 is for reference to the output of M 1. The output voltage V o is determined by subtracting the reference output of M 2 with the output of M 1. This effectively cancels the DC offset caused by gate bias itself. The result is a V o approximately proportional to the square of v in, the RF signal to the transistor

2.4. NOISE CANCELLATION 16 V DD V DD R D R D v in - V o + - + M 1 C L C M 2 L + + V DC V DC - - Figure 2.3: Principle diagram showing the concept of the power detector from [1] M 1. The load resistors R D and transistors are sized to balance sensitivity, output impedance, and bandwidth. The load capacitances C L are very large to filter out as much of the RF frequency components and harmonics of the output as possible such that the output voltage is made practically DC only. There are a variety of different ways to deal with noise and IMD in ICs. Of particular interest to the possibility of digital control are techniques that involve cancellation using transistors and optimal biasing since digital devices can be used to provide the gate biasing necessary for finetuning. 2.4 Noise Cancellation The noise cancellation method is one way to reduce noise in an amplifier or transconductor. This technique is so called because it involves cancelling the thermal noise contribution of the input transistor [16]. This is done by identifying two nodes for

2.4. NOISE CANCELLATION 17 i out R D M 2 M 1 M 3 R S V S Figure 2.4: Basic noise cancelling circuit schematic which the same noise appears with the same polarity and the signal appears with the opposite polarity. One advantage is that broadband input matching is possible through the use of a common gate transistor. Another is that the technique does not inherently rely on any use of inductors to achieve very low noise figures. Figure 2.4 shows an example of a noise cancelling topology that uses a common gate input transistor. In this case, the two nodes with the signal appearing with opposite polarity and the noise with the same polarity are at the drain and source of M 1. M 3 is large to contribute a lot of transconductance. Transistor M 2 is used to amplify the noise and signal at the drain of M 1 such that the signal is complemented

2.5. DISTORTION CANCELLATION BY DERIVATIVE SUPERPOSITION 18 at i out and the noise is cancelled: R S R D = g m2 g m3 (2.14) This specific example was used as a transconductor in a low noise Gilbert Cell to achieve an average double sideband noise figure of 3.9 db over 1-5.5 GHz [10]. It was used to preceed a low voltage mixer to achieve a total double sideband noise figure of less than 4.8 db [17]. A variation of was used in [18] to achieve a noise figure of 2.6 db and 14.5 db of gain within 0.8-2.1 GHz. A more broadband variation was used in [19] to achieve a noise figure less than 4 db across the range of 3.1-10.6 GHz with 16.6 db of gain. While one can achieve a very good noise figure at a narrow band with noise cancellation, achieving broadband noise figure using noise cancellation is a challenge. The noise figure tends to be higher as the frequency is increased. Additional design techniques may be required to lower the noise figure as frequency increases. 2.5 Distortion Cancellation by Derivative Superposition Derivative superposition (DS) is a technique used to cancel IMD3 [20] [21] [22] [23]. It makes use of the fact that, depending on a transistor s bias, the third order derivative of the transconductance (g m3 ) can be either negative or positive. Figure 2.5 shows a sample curve of the g m3 of an NMOS transistor simulated using Cadence tools as a common source transistor. The g m3 is generally negative when the transistor is

2.5. DISTORTION CANCELLATION BY DERIVATIVE SUPERPOSITION 19 0.8 0.6 0.4 0.2 g m3 (A/V 3 ) 0-0.2-0.4-0.6-0.8-1 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 V GS (V) Figure 2.5: The g m3 plot of a basic common source transistor biased positively in saturation, but when the transistor is biased near cutoff, the g m3 is positive. By biasing the distortion cancelling transistor correctly with the opposite sign of the g m3 as its corresponding transistor, the IMD3 can be significantly reduced by cancelling the resultant out-of-phase third order products. DS is usually done by putting a transistor in parallel with the regular transconductor as is shown in Figure 2.6. Since the transconductor is ususally in saturation, the g m3 is negative, so the cancelling transistor should be biased near pinchoff for a positive g m3. DS has been shown to increase IP3 by 10-20 db compared with the baseline amplifier [24] [25] [26]. Furthermore, it requires only one or a few auxiliary transistors and therefore requires very little additional chip area. This makes it well suited for RFIC applications. However, DS is extremely sensitive to bias conditions. This is

2.6. CONCLUSION 20 V 1 R G V 2 Σ Out In R G Figure 2.6: Basic distortion cancellation circuit using the method of derivative superposition especially a concern for any broadband design as well as any design that must consider variations in signal power. 2.6 Conclusion In this literature review, an overview of typical front-end devices were discussed. In particular, the focus was on integrated circuits with potential for digital assist by adjusting gate biases depending on the detected input signal. The Gilbert Cell,

2.6. CONCLUSION 21 noise cancellation and distortion cancellation through derivative superposition were discussed as well as their advantages and disadvantages. Power detection was covered as well, particularly the use of a nonlinear transistor or nonlinear transistors to achieve a DC output dependent on the RF input amplitude to the device.

22 Chapter 3 Gilbert Cell Mixer With Power Detector and Digital Control 3.1 Introduction The amount of distortion produced by an active mixer depends on both the strength of the input signal and the bias point of the mixer. Generally, once a mixer is fabricated and the bias voltages set, there is no more control over the distortion performance of the mixer. This chapter presents a method to control the level of distortion produced by a mixer by controlling bias voltages based on the sensed power of the input signal to the mixer. The Gilbert Cell is a type of frequency mixer that is one of the most widely used in RF applications [3]. Advantages of the Gilbert Cell mixer include high conversion gain and high port-to-port isolation while using a low to moderate amount of DC power. However, one of the problems with the Gilbert Cell is how to keep the IMD3 low. This is especially important since the first downconversion mixer dominates

3.1. INTRODUCTION 23 the linearity performance of transceivers due to increase in signal power down the receiving path [27]. Since mixers in modern CMOS chips are required to operate with low supply voltages and consume low power, it is relatively difficult to achieve a high linearity in an active mixer [28]. Linearity becomes more of a concern in low power RF tranceivers as the transistor sizes and supply voltages are scaled down. However, it is possible to achieve a good IIP3 even with low voltage operation through specialized design methods [29]. Optimum biasing techniques were used to improve the IIP3 of LNAs in [30] and [31]. Although the devices were not mixers, the technique could be adapted for mixers. While optimum gate biasing is able to produce a high IIP3, it is extremely sensitive to variations as the optimal bias must be very precise. Mixers with distortion cancellation through derivative superposition (DS) using multiple gated transistors have been demonstrated to improve IIP3 significantly [9] [32] [33] [28] [34]. However, the efficacy of the DS method using multiple gated transistors relies on bias voltages optimized for both a particular input power and a particular frequency. Moreover, it is extrememly sensitive to variations. The goal of the experiment was to achieve an improvement of the overall IIP3 of the mixer by changing the gate bias voltage of the first input transistor on the chip to affect the gain and especially the IMD3. This is assuming that the IP3, both input-referred and output-referred, is calculated by following the appropriate section of the curve given by output power versus input power for both the fundamental tone and third order harmonic. Such an achievement would show that, whereas the distortion tends to increase with output signal power, the distortion would be

3.2. CONCEPT OF THE MIXER AND POWER DETECTOR 24 decreased for higher input power levels by reducing the size of the input signal after the first transistor at higher input power levels. The other transistors in the circuit are optimally biased in order to minimize the overall IIP3. 3.2 Concept of the Mixer and Power Detector By using a microcontroller with DAC output capability, one can control the biases on the Gilbert Cell such that it is possible to make improvements in the performance in terms of IP3. By controlling transistor gates strategically placed on the mixer, the V DD V DD V DD VDD V B3 R D R D M 3 V B4 + IF out - V B4 M 4 R B R B C B + M 7 M 8 M 9 M 10 LO IN - C B V B1 C B R B R B V B2 L RF C RF L RF M 5 M 6 C RF + M 1 M 2 RF IN - C B Figure 3.1: Gilbert Cell mixer schematic

3.2. CONCEPT OF THE MIXER AND POWER DETECTOR 25 control biases can be swept within a reasonable range to find how the performance of the device changes with the input power by changing the biases. A power detector can therefore be used to limit the distortion particularly at higher levels of input power as the input referred 1 db compression point (IP1dB) is approached. A schematic of the Gilbert Cell is shown in Figure 3.1. The gain variation with input power was achieved by using an input power detection circuit to signal a digital microcontroller. Each gate bias was controlled by a DAC comprised of a pulse width modulation (PWM) output on the microcontroller followed by an resistancecapacitance (RC) low pass filter (LPF). This bias control would affect the gain of the first transistor, which in turn effects the third order distortion on the output signal. A block diagram of the setup is shown in Figure 3.2. The power level was detected automatically by using an on-chip power detection circuit in combination with the microcontroller analog to digital converter (ADC) input separated by a 741 operational amplifier circuit configured as a unity gain buffer. Optimum DC bias points were obtained from previous measurements using only a DC supply rather than microcontroller PWM and a DC multimeter to measure the power detection output. These measurements were performed at coarse power steps (every 2 db) from -24 dbm to -16 dbm and were programmed into an array in the read-only memory (ROM) of the microcontroller. Using the data stored in the ROM array, the optimum value of the DC bias voltage was found for the measured RF input power level. For input power levels not measured, a linear interpolation method was used to approximate the optimum bias voltage. The PWM duty cycle was set appropriately to produce this optimum bias voltage at the output of the DAC.

3.3. CIRCUIT DESIGN 26 Microcontroller PWM outputs A/D converter Unity Gain Op Amp Buffer RC Low Pass Filter Array Gate Bias Voltages RF Input -3dB 0 180 RF Power Detector Gilbert Cell 0 180 Active IF Buffer IF Output Dummy Detector CMOS Chip LO Input -3dB 0 180 Figure 3.2: A block diagram of the mixer and bias control system 3.3 Circuit Design 3.3.1 Gilbert Cell Mixer A schematic diagram of the Gilbert cell mixer used in this thesis is shown in Figure 3.1. It is a variation of the mixer described in [7]. A summary of the component values used is shown in Table 3.1. A separate transconductor stage is connected through a capacitor to the mixing stage. Transistors at the RF input to the mixer stage conduct current. Whereas the mixer in [7] uses resistors between the intersection of the transconductor and switching stages, the mixer in this thesis uses transistor current sources with variable gate voltages.

3.3. CIRCUIT DESIGN 27 Table 3.1: Summary of Component Values for the Mixer Transistor (W/L) 1,2 (W/L) 3,4 (W/L) 5,6 (W/L) 7,8,9,10 Size (µm) 40/0.12 6/0.12 4/0.12 10/0.12 Component L RF C RF R D C B R B Values 1.54 nh 1.87 pf 8 kω 14.3 pf 50 kω The DC bias control points on the final mixer implementation are (V B1 ), (V B2 ), and (V B3 ). The number of controllable bias voltages were limited by the number of available pins on the DC probe used in measurement and by the fact that at least three pins were required for supply voltage (V DD ), ground (V SS ), and the power detector output. Since V B4 could not be available for control in the final implementation, it was tied to a constant DC voltage produced on-chip by V DD. The DC bias of the RF input, V B1 is completely isolated from the mixing stage. However, the biases of the LO transistors and the current sources interact by changing the level between the drain of the current sources and the source of the LO transistors. 3.3.2 Power Detector The on-chip power detector design selected was a low power self-biased design [35]. Besides providing the power detection voltage for the microcontroller, the design was meant to provide the impedance matching of the RF input. In the final chip layout, two power detectors were used, one for each of the differential inputs, so that symmetry would be maintained at the RF input. In the end, only one of the power detectors was actually used while the other was a dummy to balance the input. The output from the first power detector was taken by one of the pins on the DC probe.

3.3. CIRCUIT DESIGN 28 3.3.3 Off-Chip Devices Operational Amplifier Buffer to ADC The power detector output was connected to an LM741 operational amplifier circuit configured as a unity gain buffer. This was to prevent the impedance of the input pin to the microcontroller ADC from loading the power detector and affecting the results. As a result, the power detector output was connected to high input impedance of the buffer, and the output impedance of the buffer to the ADC pin was very low. DAC Filters Variation of bias voltages required a DAC. The PWM outputs on the microcontroller followed by an array of passive LPFs were used for this purpose. Since the maximum output of the PWM was 3.3 V, it was possible to achieve more fine resolution of steps using the 10 bits of the PWM by using a voltage divider in the filter to reduce that maximum voltage by half. This is acceptable since the supply voltage of the CMOS chip, 1.2 V, is less than half of 3.3 V. Figure 3.3 shows a schematic of the simple voltage dividing passive RC LPF. In order to achieve maximum filtering of AC from the PWM output, R and C had to be very large. Each DC voltage was connected to a transistor gate, which is a high impedance. These same filters were R V PWM V DC R C Figure 3.3: RC LPF used after PWM

3.3. CIRCUIT DESIGN 29 used with the setup for digital assist of the CMOS chip in chapter 4. Active Output Buffer Since the drain resistors at the output of the Gilbert Cell were very large (8 kω) compared to the input resistance of the spectrum analyzer to be used in measurement (50 Ω), the spectrum analyzer would have significantly loaded the output of the Gilbert Cell such that the output voltage would have been significantly reduced. This would have affected the final results and significantly reduced the output power sensed by the spectrum analyzer. Therefore, an active differential to single-ended buffer was required to maintain the output voltage while providing the output of the mixer with a high impedance load. The MAX4444 chip by Maxim Integrated served this purpose. Figure 3.4 shows a schematic diagram of the buffer model at the IF frequency. The MAX4444EVKIT evaluation board was used, but some modification was required for use with the mixer chip. In order that the input to the MAX4444 be very large, 50 Ω resistors on the unmodified board in parallel with the inputs were removed, and an inductor was placed in parallel with each differential input to cancel the input capacitance at the desired IF of 202 MHz. The resulting input impedance can be modeled as an 82 kω resistor between outputs. 50 Ω + V out V IF 82 kω + - 2V IF - Figure 3.4: Model of the off-chip IF output buffer at the IF frequency used in simulation

3.3. CIRCUIT DESIGN 30 3.3.4 Initial Data Gathering In order to gain some improvement from digital assist, optimal bias voltages must be chosen. In this thesis chapter, the main performance parameters of the mixer for which improvement was sought were conversion gain and IIP3. To this end, the trend of conversion gain and IMD variation with changing bias voltages needed to be found. Initial data was gathered by doing automated two-dimensional sweeps of V B1 and V B2 at a time using LabVIEW while varying V LO and the RF input power (P RF ) manually. LabVIEW was used to speed up the measurement to make it more efficient because each two-dimensional sweep included many points (almost 200). Figure 3.5 shows the LabVIEW program or virtual instrument (VI) used to do the automatic sweeps. It read the spectrum analyzer trace and saved it into.tdm file, which could be read by Microsoft Excel. A sample trace that was measured at Figure 3.5: The main VI used to automatically vary bias voltages while recording two-tone test IF traces

3.3. CIRCUIT DESIGN 31-10 -20 Spectrum Analyzer Output (dbm) -30-40 -50-60 -70-80 -90 199 200 201 202 203 204 205 206 IF Frequency (MHz) Figure 3.6: Sample trace recorded by the LabVIEW VI 4 GHz RF frequency, -24 dbm RF power, and all of V B1, V B2, and V LO set to 540 mv is shown in Figure 3.6. The peaks at the IF frequencies and the third order intermodulation frequencies were read and managed using the spreadsheet. Figure 3.7: Front panel of the main VI used to automatically sweep bias voltages

3.3. CIRCUIT DESIGN 32 Figure 3.8: Sub VI used to set the DC bias voltages for initial sweeps Figure 3.7 shows the front panel of the main VI used to set the variables for the automated sweeps. Controllable fields include the start voltage, the interval of each voltage step in the sweep, and the number of steps in the sweep of each of V B1 and V B2 as well as the filename to save each trace to. The actual bias voltages read from the DC supplies and trace after each read are displayed on the LabVIEW front. Three sub VIs were used in the main VI: one for setting the DC voltages (Figure 3.8), one for writing each spectrum analyzer trace (Figure 3.9), and one for naming each saved trace (Figure 3.10). Once the initial data were gathered, the approximate bias points for very good performance with the input RF power was known. The more finely tuned points for improved performance were then found manually with ease and recorded in the microcontroller to be automatically adjusted with input power.

3.3. CIRCUIT DESIGN 33 Figure 3.9: Sub VI used to record the spectrum analyzer trace showing IF output from initial sweeps Figure 3.10: Sub VI used to name each IF output trace recorded from initial sweeps

3.3. CIRCUIT DESIGN 34 3.3.5 Digital Control Algorithm The gate bias voltages of the Gilbert Cell mixer are controlled by an algorithm on an off-chip microcontroller unit. This unit uses and analog to digital converter (ADC) in order to read the power detector output. The microcontroller is programmed to use the digitized power detector reading in order to estimate the actual input power level and adjust the gate bias voltages using linear interpolation. The linear interpolation concept is shown in Figure 3.11. The circles on the plot represent measured data points (X,Y) of a dependent variable Y and an independent variable X. The arrowheads show how an interpolated Y out is determined by an input X in and the nearest high and low measured data points. Dependent Variable (Y) Yout X low X in X high Independent Variable (X) Figure 3.11: A graphical depiction of a linear interpolation from measured (X,Y) points represented by circles with Y out as the variable to be interpolated given X in as the input variable

3.3. CIRCUIT DESIGN 35 Start Read input power level Estimate input power using linear interpolation Estimate optimum gate bias from array of measurements Ouptut optimum bias Figure 3.12: Block diagram of the digital assist algorithm For measurements of the Gilbert Cell chip with the digital assist, the power detector provided input power as the independent X variable, and the Y variables were the bias voltages modified for reduced distortion. The microcontroller made use of the recorded data by first using linear interpolation to measure the input power that was output by the power detector. Once the input power level was properly read, the optimum points for controllable bias voltages for IP3 were interpolated using a similar process using the LUT of measured values. The estimated optimum bias voltages were then output from the DACs. A block diagram visually representing the control algorithm is shown in Figure 3.12. Initially, the input power must be read from the power detection circuit before any calculation of the optimum bias can be made. The microcontroller ADC is used for this. The microcontroller program includes an array of the voltages measured at certain known input power levels as well as an array of the optimum bias points for those power levels. Once the ADC is read, the 10-bit integer is translated into an actual voltage by using the linear interpolation equation V read = V refl + K V 1023 V refh (3.1) where V refl and V refh are the lowest and highest respectively for which a 10-bit ADC

3.4. EXPERIMENTAL RESULTS 36 read between 0 and 1023 are given. In the experiment, these numbers were specified using a digital DC supply as 0 and 1.2 V respectively. K V is the value of the 10-bit ADC read. The optimal bias voltage was also calculated using linear interpolation by using V bias = K P (V 2 V 1 ) + V 1 (3.2) where V 2 and V 1 are the optimal bias voltages at the next higher and lower known points respectively. K P is a factor determined by applying the measured V read into the following equation where V lowp and V highp are respectively the next lowest and highest power detector DC voltage outputs from input powers recorded in ROM from initial measurements: K P = V read V lowp V highp V lowp (3.3) The PIC18F87J11 microcontroller uses 10 bits to determine the duty cycle of the PWM outputs. The maximum and minimum duty cycles are therefore 0 and 2 10 1 respectively. The duty cycle required for each PWM to produce V bias at the output of the DAC is determined using measured values of the output bias voltage at maximum (δ max ) and minimum duty cycles (δ min ) as follows: δ = (2 10 1) V bias V δmin V δmax V δmin ; (3.4)

3.4. EXPERIMENTAL RESULTS 37 3.4 Experimental Results 3.4.1 Experimental Setup Figure 3.13 shows the Gilbert Cell and input power detector fabricated in 0.13 µm CMOS. The measurements were made on-wafer using a Wentworth probe station, two GGB Industries ground-signal-ground-signal-ground (GSGSG) probes, a Cascade Microtech GSGSG probe, and a six-pin GGB DC probe. IP3 measurements were conducted using two Anritsu MG3694A function generators passed through a coupler and by reading the third order IMD products in comparison with the fundamental tones on an Agilent E4446A spectrum analyzer. The extra LO signal for the IP3 Figure 3.13: Photograph of fabricated CMOS mixer and power detector

3.4. EXPERIMENTAL RESULTS 38 measurements was provided by one of ports of an Agilent 8510C vector network analyzer. Three Agilent digital DC supplies were used to set the transistor gate bias voltages, two of the E3631A and one E3648A. Bias voltage sweeps were done using LabVIEW as described in 3.3.4. All measurements were set up in accord with Figure 3.2. 3.4.2 Power Detector Figure 3.14 shows the characteristic of the power detector. There is a smooth curve that shows a clear output voltage variation for varying input. This is the most important function of the power detector since the linear interpolation algorithm is used to find the input power between any two measured outputs corresponding to specific input power levels recorded in ROM. 650 600 2GHz 4GHz 8GHz Output Voltage (mv) 550 500 450 400-30 -25-20 -15 Input Power (dbm) Figure 3.14: A plot of the output voltage produced by the power detector for varying input power at different frequencies

3.4. EXPERIMENTAL RESULTS 39 Although there is some variation of the output voltage dependent on the frequency, a complete system would include both a power detector and frequency detector which could be used to get better power readings by interpolating over frequency since the frequency detector shown in chapter 4 has a very small output variation versus input power. 3.4.3 Testing for Optimum Bias Voltages Optimal bias voltages were found through initial two-tone testing using LabVIEW without the use of the microcontroller by sweeping all bias voltages to be controlled within a reasonable range. Preliminary simulation was conducted using the Cadence design environment, Virtuoso, Spectre, and Assura. The simulation sweeps were done with V B1 ranging from 430 mv to 580 mv and V B2 ranging from 470 mv to 560 mv 20 Simulated Conversion Gain (db) 15 10 5 0-5 0.65 0.6 0.55 V B1 (V) 0.5 0.45 0.4 0.46 0.48 0.5 0.52 V B2 (V) 0.54 0.56 0.58 Figure 3.15: Simulated conversion gain with varying (V B1,V B2 ) and with V LO fixed at 600 mv with -24 dbm RF input power

3.4. EXPERIMENTAL RESULTS 40 each with steps of 10 mv. Measurement sweeps were done with V B1 from 430 mv to 580 mv and with V B2 from 480 mv to 580 mv each with steps of 10 mv. This would produce an array of measured fundamental and IMD3 output tones for each bias voltage at a particular input power level. The bias voltages to be output by the microcontroller at each input power level were selected based on this array of measured data and programmed into the microcontroller ROM. The trend looks similar for high and low powers alike, but as expected, the OIP3 and CG are generally lower across all bias voltages for higher powers. Figure 3.15 shows the simulated conversion gain result as V B1 and V B2 are varied with an RF input power level of -24 at 4 GHz frequency. The conversion gain peaks at 16.7 db when V B1 is 550 mv and when V B2 is 520 mv. The V LO in these simulation results was set to 600 mv. The OIP3 that would normally be extracted from the fundamental 12 Simulated OIP3 (dbm) 10 8 6 4 2 0 0.65 0.6 0.55 V B1 (V) 0.5 0.45 0.4 0.46 0.48 0.5 0.52 V B2 (V) 0.54 0.56 0.58 Figure 3.16: Simulated OIP3 extrapolated from IF and IMD3 value at -24 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 600 mv

3.4. EXPERIMENTAL RESULTS 41 16 Simulated Conversion Gain (db) 14 12 10 8 6 4 2 0-2 0.65 0.6 0.55 V B1 (V) 0.5 0.45 0.4 0.46 0.48 0.5 0.52 V B2 (V) 0.54 0.56 0.58 Figure 3.17: Simulated conversion gain with varying (V B1,V B2 ) and with V LO fixed at 600 mv with -18 dbm RF input power and IMD3 output power at -24 dbm input power as it varies in simulation with V B1 and V B2 is shown in Figure 3.16. The V B1 and V B2 required for maximum conversion gain do not correspond exactly to the optimal V B1 and V B2 required for optimal IMD3 performance. Maximum OIP3 would have been achieved when V B1 is 450 mv and when V B2 is 510 mv. However, the conversion gain at this point would be reduced to 13.1 db. Figures 3.17 and 3.18 show the simulated conversion gain and OIP3 result respectively as V B1 and V B2 are varied at 4 GHz frequency and a higher input power of -18 dbm. At this input power level, the maximum conversion gain would have been 14.936 db, which happens to be beyond the simulated P1dB point of the uncontrolled mixer. The measured results showed trends similar in shape to the simulated trends.

3.4. EXPERIMENTAL RESULTS 42 10 Simulated OIP3 (dbm) 8 6 4 2 0 0.65 0.6 0.55 V B1 (V) 0.5 0.45 0.4 0.46 0.48 0.5 0.52 V B2 (V) 0.54 0.56 0.58 Figure 3.18: Simulated OIP3 extrapolated from IF and IMD3 value at -18 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 600 mv 7 6 Conversion Gain (db) 5 4 3 2 1 0-1 0.65 0.6 0.55 V B1 (mv) 0.5 0.45 0.4 0.48 0.5 0.52 V B2 (mv) 0.54 0.56 0.58 Figure 3.19: Measured conversion gain with varying (V B1,V B2 ) and with V LO fixed at 540 mv with -24 dbm RF input power

3.4. EXPERIMENTAL RESULTS 43 OIP3 (dbm) 5 4 3 2 1 0-1 -2-3 -4 0.65 0.6 0.55 V B1 (mv) 0.5 0.45 0.4 0.48 0.5 0.52 V B2 (mv) 0.54 0.56 0.58 Figure 3.20: Measured OIP3 extrapolated from IF and IMD3 value at -24 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 540 mv Figure 3.19 shows the measured conversion gain result as V B1 and V B2 are varied with an RF input power level of -24 at 4 GHz frequency. In the measurement, the maximum conversion gain was achieved when V LO was 540 mv. As the figure shows, the maximum measured conversion gain was 6.7 db, with V B1 and V B2 set to 540 mv and 550 mv respectively. The OIP3 at this point would normally be 3.1 dbm. At the lowest input power level, the maximum conversion gain was automatically aimed for by setting V B1 and V B2 accordingly. This is different than the bias voltages for maximum OIP3 as shown in Figure 3.20. Figures 3.21 and 3.22 show the measured conversion gain and OIP3 result respectively as V B1 and V B2 were swept at 4 GHz frequency and a higher input power of -18 dbm. At higher power levels, rather than maximum conversion gain, maximum linearity was sought. Therefore, the bias was changed to effect this result gradually

3.4. EXPERIMENTAL RESULTS 44 6 5 Conversion Gain (db) 4 3 2 1 0-1 -2 0.65 0.6 0.55 V B1 (mv) 0.5 0.45 0.4 0.48 0.5 0.52 V B2 (mv) 0.54 0.56 0.58 Figure 3.21: Measured conversion gain with varying (V B1,V B2 ) and with V LO fixed at 540 mv with -18 dbm RF input power 4 3 2 OIP3 (dbm) 1 0-1 -2-3 -4 0.65 0.6 0.55 V B1 (mv) 0.5 0.45 0.4 0.48 0.5 0.52 V B2 (mv) 0.54 0.56 0.58 Figure 3.22: Measured OIP3 extrapolated from IF and IMD3 value at -18 dbm RF input power with varying (V B1,V B2 ) and with V LO fixed at 540 mv

3.4. EXPERIMENTAL RESULTS 45 as the bias voltage was increased such that the power level of the fundamental output tone was at least linearly proportional to the input RF power over the range of variation. The maximum measured conversion gain of 5.5 db was achieved with V B1, V B2, and V LO all set to 540 mv. As with the lower input power, this is different than the bias voltages for maximum OIP3. However, the gain was sacrificed at higher input power levels for IMD performance. At -18 dbm input power, the microcontroller was programmed to output a V B1 of 479 mv and a V B2 of 540 mv for a conversion gain of 4.9 and an OIP3 extrapolated from the two points of 3.7 dbm. Once the general trend was established, a manual search was done for optimal bias voltages to program into the microcontroller around what was indicated by the initial sweeps. In the end, V B2 and V LO remained fixed at 540 mv since their optimal value changed only little and was not very sensitive to variation. However, V B1 had the greatest effect and was varied from 542mV at low RF input power to 478 mv at high RF input power power between RF input power levels of -24 dbm and -16 dbm. The trends that the conversion gain and IMD examined in terms of OIP3 follow as biases are varied are not so sensitive or complicated that they become difficult to work with. In fact, they are quite well behaved. This indicates that linear interpolation with an LUT of bias outputs at a few specific input power levels is more than adequate for manipulating the biases in order to improve the IMD performance of the mixer. 3.4.4 Baseline Gilbert Cell Performance The baseline Gilbert Cell was measured using the bias voltages set for maximum conversion gain. The mixer shows a conversion gain of 6±1 db in a bandwidth of 12 GHz as can be seen in Figure 3.23. Although the frequency response shows the same

3.4. EXPERIMENTAL RESULTS 46 10 9 8 7 Conversion Gain (db) 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 Frequency (GHz) Figure 3.23: Conversion Gain at -24 dbm input power versus RF frequency 0-2 -4 (-12.06,-6.56) -6 Output Power (dbm) -8-10 -12-14 -16-18 -20-25 -20-15 -10-5 Input Power (dbm) Figure 3.24: Plot of P1dB of the mixer without digital assist at 4 GHz RF

3.4. EXPERIMENTAL RESULTS 47 shape as the simulated result using the Cadence tools, the conversion gain itself is much lower. This is thought to be due to the output IF buffer used in measurement. Figure 3.24 shows that the input referred 1 db compression point (P1dB) of the baseline mixer is -12.06 dbm while the output referred P1dB is -6.56 dbm. The IP3 plot of the baseline mixer is shown in Figure 3.25. The measured IIP3 is -3.11 dbm, and the corresponding OIP3 is 1.81 dbm. Since the DC gate biases were varied based on the RF input power measured by the power detector, it is expected that some variation in DC consumption occurs within the range of input powers for which the biases were varied. This effect is shown in the plot of DC power consumption versus input power over the range of bias control in Figure 3.26. The DC power consumption was actually reduced as the 10 0-10 (-3.11,1.81) Output Power (dbm) -20-30 -40-50 Fund IMD3-60 -25-20 -15-10 -5 0 Input Power (dbm) Figure 3.25: Plot of fundamental and IMD3 output power versus input power of uncontrolled mixer at 4 GHz RF

3.4. EXPERIMENTAL RESULTS 48 5 4.5 4 DC Power Consumption (mw) 3.5 3 2.5 2 1.5 1 0.5 0-24 -23-22 -21-20 -19-18 -17-16 -15-14 Input Power (dbm) Figure 3.26: Plot showing the variation of DC power with input power in the range of digitally assisted variation of gate bias 0-10 -20 LO to RF Isolation (db) -30-40 -50-60 -70-80 -90-100 0 2 4 6 8 10 12 14 Frequency (GHz) Figure 3.27: The LO to RF isolation versus RF frequency

3.4. EXPERIMENTAL RESULTS 49 RF power was increased. The DC power consumption was between 2.06 mw and 3.27 mw. Figure 3.27 shows the port-to-port isolation from the LO port to the RF port. It is consistently less than -53 db. The measured input reflection coefficient is affected mostly by the input RF transistor and the power detector. It was measured as shown in Figure 3.28 and agrees very well with Cadence simulation results. Lastly, the double sideband noise figure measured at 4 GHz RF was found to be 28 db, which is a deviation from the simulated result of between 14.8 and 15.6 db within a 1 to 10 GHz bandwidth. However, this coincides with a deviation from the simulation of the measured conversion gain of almost 10 db as previously noted. Figure 3.28: Differential S 11 of the downconversion mixer

3.4. EXPERIMENTAL RESULTS 50 3.4.5 Improvement with Digital Assist The resulting output versus input power curve of the mixer with digital assist in Figure 3.29 shows an improvement in the IIP3 by 5.94 db and a smaller increase in the OIP3. This is expected since the IMD3 was reduced by reducing the gain of the first transistor for higher input power levels. In effect, this pushes the IP3 point to the right on the cartesian axes. However, the distortion for strong signals is decreased while the output is at least still proportional to the input. This achieves the goal of the experiment. In addition, the P1dB was increased from -12 dbm to almost -3 dbm as shown in Figure 3.30. The overall IMD3 of a system such as an RF front end could be reduced while maintaining a P out versus P in slope of 1 by varying the slope before another more 10 0-10 (2.83,2.56) Output Power (dbm) -20-30 -40-50 Fund IMD3-60 -25-20 -15-10 -5 0 5 Input Power (dbm) Figure 3.29: Plot of fundamental and IMD3 output power versus input power of mixer with gain controlled by digital means at 4 GHz RF

3.4. EXPERIMENTAL RESULTS 51 0-1 -2-3 Output Power (dbm) -4-5 -6-7 -8-9 -10 (-3.33,-2.78) -11-12 -13-14 -15-20 -18-16 -14-12 -10-8 -6-4 -2 0 Input Power (dbm) Figure 3.30: Plot of P1dB of the mixer with digital control linear and less critical stage in terms of IMD3. A table summarizing the results from measurement both with and without digital assist is shown in Table 3.2. Table 3.2: Summary of Broadband Mixer Performance and Improvement with Digital Assist Characteristic With Digital Assist Without Digital Assist DC Power (mw) 2.06 3.27 3.27 1 RF Frequency (GHz) 1 12 1 12 Conversion Gain (db) 3 7 6±1 IP 1dB (dbm) -3.33-12.06 IIP3 (dbm) 2.83-3.11 LO to RF (db) < 53 < 53 1 Includes DC power of both mixer and power detector

3.5. CONCLUSION 52 3.5 Conclusion In this chapter, a low power broadband Gilbert Cell mixer and power detector system fabricated in 0.13µm CMOS for use with off-chip digital assist of gate bias voltage was discussed. Varied bias voltages were used to reduce the total distortion at high input power levels by reducing the slope of the output power versus input power curve in the operating range of the mixer. While the OIP3 was the same, the caluculated IIP3 based on the slopes of the fundamental and third order tones was improved by approximately 6 db, proving the usefulness of the power detector and microcontrollerbased digital assist.

53 Chapter 4 Noise Cancelling Amplifier with Frequency Detector and Digital Control 4.1 Introduction Low noise amplifiers are useful in reducing the overall noise figure of a cascade of RF devices. Noise cancelling is one method that is used in amplifiers to achieve a low noise figure [10]. The advantage of noise cancelling is that few or no inductors are required for the cancelling to achieve a very low noise figure at certain frequencies. The noise cancelling method was particularly attractive for experimentation with bias control because of the transistor gates that must be biased separately to achieve good gain and noise cancellation. However, inductors may be required to optimize the amplifier s noise figure performance since wideband noise cancelling amplifiers tend not to have flat noise figure with varying frequency. The noise figure in such circuits

4.2. CONCEPT OF THE NOISE CANCELLING AMPLIFIER AND FREQUENCY DETECTOR 54 tends to increase with frequency. Also, depending on how the amplifier design is realized, the amplifier may not have a flat gain within the full bandwidth of interest. These problems are addressed in this chapter by introducing a digital assist technique to minimize the noise figure versus frequency while maintaining a flat gain across the bandwidth. This is accomplished by finding the combinations of bias voltages at various transistor gates that would produce the minimum noise figure at a given frequency while maintaining a specific gain that would be the same at all frequencies. To accomplish this, the signal frequency must be measured at all times. Therefore, a frequency detector with a measurable DC output independent of signal input power is required. The frequency detector taps the output of the LNA rather than the input since the gain of the LNA helps the frequency detector to work as described in this chapter. After a buffer, a microcontroller uses the measured frequency to determine the optimal bias points for noise figure and gain, which it outputs back to the LNA transistor gates. This chapter introduces a noise cancelling amplifier system with an on-chip frequency detector sensed by a microcontroller, which controls the bias voltages for optimum noise figure and gain. The concept and design of the system and of the fabricated chip in 0.13 µm CMOS is described in detail. A description of the linear interpolation using frequency as an input variable is covered. Lastly, the benefits of the system are demonstrated by examining measured results.

4.2. CONCEPT OF THE NOISE CANCELLING AMPLIFIER AND FREQUENCY DETECTOR 55 4.2 Concept of the Noise Cancelling Amplifier and Frequency Detector The concept of using digital control to enhance the performance of an LNA involves the use of the PIC18F87J11 microcontroller with analog inputs for analog-to-digital conversion as well as a number of PWM outputs to provide biasing. An LUT of optimum bias voltages for varying frequency is recorded in ROM based on measured data points. A block diagram of the system is shown in Figure 4.1. In order for the PWM outputs Microcontroller A/D converter RC Low Pass Filter Array Unity Gain Op Amp Buffer RF input Noise- Cancelling Amplifier Gate bias voltages DC output Frequency Detector RF output Figure 4.1: Block diagram of LNA optimization system including the frequency detector and microcontroller

4.3. SYSTEM DESIGN AND IMPLEMENTATION 56 microcontroller to determine which bias outputs to send through the PWM modules, the microcontroller needs to read a value from a frequency detector. The frequency detector was designed on-chip and provides an analog output dependent on frequency, which is read by the microcontroller ADC. Once the microcontroller has the frequency reading, linear interpolation is used in order to get the optimum bias voltages even at frequencies for which the optimum bias points were not specifically recorded in ROM. 4.3 System Design and implementation 4.3.1 Noise Cancelling Amplifier The amplifier used in the experiment is based on the principles of noise cancellation discussed in the relevant section of the literature review contained in chapter 2. It was designed using Cadence tools and simulated using Virtuoso, Spectre, and Assura before fabrication. Figure 4.2 shows the schematic of the noise cancelling LNA used for digitally assisted optimization based on the concept shown in [19]. Table 4.1 shows a summary of the component values used in the final LNA design. The input matching is provided by the transistor M 1 which can be modeled as a common gate transistor circuit. The feedback circuit used allows a smaller transistor with a smaller input capacitance and power consumption to provide the input matching. Tranistors M 2 and M 3 provide the noise cancelling of noise generated by M 1. They are scaled according to the following: g m2 R d1 = g m3 R sig (4.1)

4.3. SYSTEM DESIGN AND IMPLEMENTATION 57 V dd V dd L d4 L d5 V dd V b2 R d4 C 3 R d5 C 4 V b4 M 4 v out R d1 R g2 M 5 M 2 R g5 C 2 V b1 M 1 R g1 V b5 C 1 C f L g3 v in M 3 R s1 L s3 Figure 4.2: Noise Cancelling Amplifier schematic Table 4.1: Summary of Component Values for the LNA Transistor (W/L) 1 (W/L) 2 (W/L) 3,4 (W/L) 5 Size (µm) 22/0.12 14/0.12 160/0.12 100/0.12 Resistor R s1 R g1,g2,g5 R d1 R d4 R d5 Values (Ω) 1.7 k 20 k 800 70 30 Capacitor C 1,4 C 2,3 C f Values (pf) 12 2.4 4.8 Inductor L g3 L s3 L d4,d5 Values (ph) 1089 145 769

4.3. SYSTEM DESIGN AND IMPLEMENTATION 58 24 22 L g3 =0,L s3 =0 L g3 =1.1nH,L s3 =145pH 20 S 21 (db) 18 16 14 12 10 1 2 3 4 5 6 7 8 9 10 11 Frequency (GHz) Figure 4.3: Schematic simulation result of the S 21 of the LNA with and without L g3 and L s3 Bandwidth Extension To cover a wider bandwidth, inductive peaking is used in three different places. At the input of transistor M 3, inductor L g3 is used for inductive peaking. The bandwidth improvement from including a 1.1 nh L g3 can be clearly seen in Figure 4.3. The case without L g3 was simulated without L s3 because the purpose of L s3, which is explained shortly, was added to counter a side effect of L g3. In addition to the noise cancelling method, the inductor reduces the noise figure by reducing the noise contribution of M 3 at higher frequencies. The combined result is a more flattened noise figure across the intended bandwidth even before digital control is applied as shown in Figure 4.4. This inductor, however, resonates in series with the

4.3. SYSTEM DESIGN AND IMPLEMENTATION 59 10 9 L g3 =0,L s3 =0 L g3 =1.1nH,L s3 =145pH 8 7 Noise Figure (db) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 Frequency (GHz) Figure 4.4: Schematic simulation result of the noise figure of the LNA with and without L g3 and L s3 parasitic capacitance at the gate of M 3, which negatively affects the S 11 input match of the amplifier. To counter this effect, a small inductance L s3 is placed at the source of M 3, just enough to keep the S 11 reasonably low. Its effect is clearly demonstrated in the simulation result shown in Figure 4.5. Inductive peaking is used in combination with a cascode transistor at the output of the noise cancelling circuit, and in the common source output buffer to extend the bandwidth. In order to reduce the input capacitance of the common gate transistor at the input of the amplifier, a smaller transistor is used with a feedback connection to the output of the noise cancelling

4.3. SYSTEM DESIGN AND IMPLEMENTATION 60 0-5 -10-15 S 11 (db) -20-25 -30-35 L s3 =0 L s3 =145pH -40 1 2 3 4 5 6 7 8 9 10 11 Frequency (GHz) Figure 4.5: Schematic simulation result of the S 11 of the LNA with and without L s3 circuit. The feedback boosts the transconductance of the common gate transistor so that a smaller transistor can be used with the same effective transconductance in order to keep the S 11 low. Controlled Bias Voltages The controlled bias voltages Vb1, Vb2, Vb4, and Vb5 can be easily pointed out in Figure 4.2. Four were designed and selected due to the four available DC inputs besides V SS and V DD on the fabricated chip. The first voltage that affected all three of gain, noise figure, and input match was V b1. V b2 was the next to be controlled as it has a direct influence on the noise figure being the gate voltage of one of the noise cancelling transistors. The third voltage to be controlled

4.3. SYSTEM DESIGN AND IMPLEMENTATION 61 was the common source output buffer s gate voltage V b5, which was expected to have a minimal effect on noise figure due to being at the output and to have a relatively large influence on the overall gain. The fourth voltage to be controlled was the gate voltage of the cascode transistor V b4. This transistor was expected to affect both of the noise-cancelling transistors, and so it had an influence mostly on the gain and noise figure of the LNA. 4.3.2 Frequency Detector The frequency detector design is based on a cascade of a limiting amplifier (LA) followed by an RC LPF and then a power detector. A block diagram is shown in Figure 4.6 with examples of the input and output waveforms of each block to demonstrate the frequency detector concept. The LA uses cascaded gain stages with active feedback for high gain and bandwidth [36]. It should have enough gain to take even a relatively low power output signal from the LNA to achieve maximum output power by clipping so that the frequency detector output is independent of input power within the operating range of the LNA. The RC filter has a steady roll off from the low frequency (1 GHz) to a high frequency (10 GHz). The LA was basically a number of cascaded differential amplifiers with active feedback. Each differential amplifier stage of the cascade is identical and is shown in Figure 4.7. The LA begins with a basic differential amplifier with one input transistor reading the output of the noise cancelling amplifier and the other grounded. Following it were three sections each with three differential amplifiers and active feedback as shown in Figure 4.8. With the high gain of the stages so far, a final differential amplifier was incuded as a buffer with its output filtered by an added

4.3. SYSTEM DESIGN AND IMPLEMENTATION 62 RF Input Limiting Amplifier Power Detector RC LPF A B C A 2 D DC output (a) Block diagram of the frequency detector Voltage Voltage Time (b) RF input (A) Time (c) Unfiltered limiting amp output (B) Voltage Voltage Time (d) Filtered limiting amp output (C) Time (e) Frequency detector output (D) Figure 4.6: Concept of frequency detection output capacitance (the RC filter shown in Figure 4.6(a)). The LA was simulated using cadence tools and was found to sufficiently clip signals as low as -40 dbm at the input to the LNA independent of frequency up to 10 GHz. However, because there are so many differential amplifier stages using active feedback, the DC power consumption is rather high. Simulation results showed the DC power consumed by the frequency detector to be 45.59 mw out of a total simulated DC power of 82.72

4.3. SYSTEM DESIGN AND IMPLEMENTATION 63 V dd V dd R d1 v inv o+ v o- R d2 v in+ M 1 M 2 V c3 M 3 Figure 4.7: A single differenctial amplifier stage v in+ Diff Amp Diff Amp Diff Amp v o+ v in- v o- M 1f M 2f V cf M 3f Figure 4.8: A single 3 differential amplifier section with active feedback mw. The RC filter is realized by placing a small capacitance in parallel at the output of the final stage of the LA in combination with the parasitic capacitance. The power detector was realized using the configuration shown in Figure 4.9. The DC output change is produced as described in the relevant section of the literature review of chapter 2 by using the square behaviour of the common source transistor

4.3. SYSTEM DESIGN AND IMPLEMENTATION 64 V dd V dd V dd R 1a R d V out R 1a v in+ M 1 M 2 C d v in- R 1b R 1b Figure 4.9: Differential input power detector stage in frequency detector and filtering out the AC components. Because the RC filtered output of the LA is differential, the power detector could further reduce AC using a single smaller capacitance by connecting the drain nodes together. This is because the odd harmonics at the output of the transistors, including the fundamental tone have opposite phases whereas the even harmonics are complemented. (v in+ ) 2n = (v in ) 2n, n = 0, 1, 2... (4.2) (v in+ ) 1+2n = (v in ) 1+2n, n = 0, 1, 2... (4.3) 4.3.3 Digital Assist The digital assist was used to optimize the noise figure for maximum, flat gain across the amplifier bandwidth by using a programmable microcontroller with DAC outputs and ADC inputs. Figure 4.10 shows the digital assist algortihm. First, the LNA gain and noise figure were measured while sweeping the gate biases. The data from these initial measurements were then stored in the microcontroller memory, and an

4.3. SYSTEM DESIGN AND IMPLEMENTATION 65 Start Read Frequency Detector with ADC Interpolate to find the exact frequency from a list of measured values Interpolate optimum biases for NF using table of measured values Output Optimum biases to PWM Figure 4.10: Block diagram of LNA digital assist algortihm algorithm was used to find the optimum biases at various frequencies for which noise figure is minimized for the maximum, flat gain. The optimum biases were recorded in a LUT in ROM. The frequency detector output was measured for the same frequencies for which the optimum bias points or the LNA were measured. These measured voltages were recorded in an array in ROM as well. In this experiment, a method of linear interpolation was used. The concept was previously discussed in chapter 3.3.5, and Figure 3.11 shows the concept graphically. For measurements of the LNA chip with the digital assist, the frequency detector provided frequency as the X variable, and the Y variables were the optimal bias voltages. The microcontroller made use of the recorded data by first using linear interpolation to obtain digital frequency representation closer to the actual frequency that was read by the frequency detector. The interpolated frequency was then used to find the best bias voltages for each of the controllable bias voltages using the LUT of measured values. The estimated optimum bias voltages were then output from the PWM through low pass filters with extremely low cutoff frequencies in order to produce the steady DC bias voltages.

4.4. EXPERIMENTAL RESULTS 66 4.4 Experimental Results 4.4.1 Fabrication and Experimental Setup The first set of measurements taken were the gain and noise figure measurements versus frequency for various combinations of bias voltages using the Agilent E4446a spectrum analyzer and the DC output voltage of the frequency detector versus frequency using a DC multimeter. Once the optimal bias points were found for optimal operation at each frequency, the microcontroller was used to control the bias voltages based on the DC output of the frequency detector. It was impossible to do a single noise figure measurement using the E4446a for this experiment because the frequency detector needed a tone to detect in order to choose which bias voltages to output from the microcontroller PWM. This was achieved by using a switch and a pause button on the microcontroller. The switch was set to allow signals from either the signal generator to input a tone for the frequency detector or a noise source for noise figure measurements. First, the former was selected. Once the input frequency was detected, the pause button on the microcontroller was pressed to maintain the bias voltages output by the microcontroller, and the input was switched to that of the noise source. Once noise figure measurements were complete for the input frequency, the input was switched back to the signal generator to detect the next frequency. The same method was used to measure the P1dB using the E4446a again. The S-parameter measurements were conducted using an Agilent 8510C Vector Network Analyzer.

4.4. EXPERIMENTAL RESULTS 67 4.4.2 Testing for Optimum Bias Voltages Optimal bias voltages in terms of gain and noise figure were found manually by exhaustively adjusting the biases and observing how each of the noise figure and gain varied. As expected, V b1 and V b2 as shown in the schematic diagram of Figure 4.2, which varied from 1.26 and 0.72 V respectively at low frequencies to 1.18 and 0.66 V at high frequencies, were the most sensitive in terms of noise figure. The least sensitive in terms of noise figure but most in terms of gain was V b5, which was varied from 0.568 to 0.8 V. The least all-around sensitive bias was V b4, which varied between 1.26 V at low frequencies to 1.16 V at high frequencies. 4.4.3 Test and Measurement A layout of the LNA and frequency detector chip is shown in Figure 4.11. The LNA and frequency detector were fabricated using a standard 0.13 µm CMOS process which has 8 metal layers including 3 thin, 2 thick, and 3 RF metal layers. The total area of the on-chip LNA and frequency detector excluding bondpads was 643 µm 573 µm and the area including bondpads was 1 mm 1 mm. Figure 4.12 shows a picture of the fabricated chip. Measured power supply current of the controlled system was between 46 and 54 ma from a 1.5 V supply with a total DC consumption of 69 to 81 mw depending on the frequency. This number corresponds well to the simulated DC power consumption of 82.72 mw of which 45.59 mw is due to the inclusion of a frequency detector. The high DC power consumption was primarily due to the many stages in the LA of the frequency detector. On-wafer testing was done using two ground-signal-ground (GSG) single-ended GGB microtech coplanar waveguide (CPW) RF probes with a pitch size of 100 µm

4.4. EXPERIMENTAL RESULTS 68 Figure 4.11: Chip layout of LNA and frequency detector in Virtuoso and two GGB DC probes with a pitch of 150 µm on a Wentworth probe station. DC voltages were supplied using Agilent E3631A and E3648A digital DC supplies. RF signals were generated using two Anritsu MG3694A sources. The second was used with a 180 hybrid coupler at the RF input for the two-tone test. The output spectrum and noise figure were examined using an Agilent E4446A spectrum analyzer. Finally, S-parameters were examined using an Agilent 8510C vector network analyzer (VNA) for which a full two-port SOLT calibration was done using a Cascade Microtech 101-190C ISS. A Wenteq ABP1200-01-1825 amplifier was used at the output of the LNA

4.4. EXPERIMENTAL RESULTS 69 Figure 4.12: Chip photograph of LNA and frequency detector when doing noise figure measurements with the spectrum analyzer in order to have greater accuracy. The measured frequency detector characteristic is shown in Figure 4.13. There is a clear increase in output DC voltage of the frequency detector with signal frequency such that each frequency is detectable suffiently accurately by linear interpolation with the microcontroller. Only this smooth, clear trend that was measured is important since any slight change in the slope of the output is compensated by the interpolation algorithm used when measuring the frequency with the microcontroller.

4.4. EXPERIMENTAL RESULTS 70 1.1 1 DC Output Voltage (V) 0.9 0.8 0.7 0.6 0.5 0.4 0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 4.13: Frequency detector DC voltage output versus frequency Each of the S-parameter measurements are shown with both fixed bias voltages without digital assist and controlled bias voltages with digital assist for comparison. In the controlled case, the gain curve is flattened and the bandwidth improved without Figure 4.14: S 21 curves of controlled LNA versus constant optimum bias for 4 GHz frequency

4.4. EXPERIMENTAL RESULTS 71 Figure 4.15: S 11 curves of controlled LNA versus constant optimum bias for 4 GHz frequency significantly affecting the noise figure or S 11. Figure 4.14 shows the gain of the original amplifier without control using the same biases that were optimal for 4 GHz frequency along with the gain of the amplifier with optimized controlled biases for each 1 GHz frequecy in the passband with linear interpolation. In the uncontrolled case, it can be seen that the gain starts above 17 db and decreases until the 3 db cutoff frequency just below 7 GHz. In the controlled case, the gain curve is flattened out to 8 GHz. In each case, the gain is slightly less than 16 db across the bandwidth of the amplifier. The variation starts low at 1 GHz, but the curve has less variation after 2 GHz than in the uncontrolled case. Figure 4.15 shows the S 11 curves of the original amplifier without control and the amplifier with digital control. The controlled case shows little variation from the uncontrolled case with even some improvement around 1 GHz. The S 11 is consistently below 10 db. The result was excellent since a very low S 11 was achieved across a very

4.4. EXPERIMENTAL RESULTS 72 Figure 4.16: S 22 curves of controlled LNA versus constant optimum bias for 4 GHz frequency wide bandwidth. Figure 4.16 shows the S 22 curves of the original amplifier without control and the amplifier with digital control. S 22, like S 11, shows little variationfrom the uncontrolled case and even some improvement near 1 GHz. The S 22 is consistently below 10 db. The noise figure of the device was measured using the Agilent E4446A spectrum analyzer in noise figure mode. At first, the noise figure for each frequency and set of biases were measured to find the optimal biases for each frequency. However, the frequency detector could not detect the frequency from a noise source. Therefore, a switch was used in the setup to select between a single tone input and the noise source. A pause button was programmed into the microcontroller to maintain the biases sent out from the microcontroller based on the frequency detector output when detecting the single tone even when that tone was removed. This would then allow the input to be switched from the signal source to the noise source while maintaining