Enhancement Mode Power Transistor, V R DS(on), mω, A G D S EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last years. GaN s exceptionally high electron mobility and low temperature coefficient allows very low R DS(on), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE UNIT Drain-to-Source Voltage (Continuous) Drain-to-Source Voltage (up to, ms pulses at C) 8 Continuous (T A = C, R θja = 9 C/W) Pulsed ( C, T PULSE = µs) 7. Gate-to-Source Voltage Gate-to-Source Voltage T J Operating Temperature to T STG Storage Temperature to V A V C egan FETs are supplied only in passivated die form with solder bars Die Size:. mm x.8 mm Applications Ultra High Speed DC-DC Conversion RF Envelope Tracking Wireless Power Transfer Game Console and Industrial Movement Sensing (LiDAR) Benefits Ultra High Efficiency Ultra Low R DS(on) Ultra Low Q G Ultra Small Footprint www.epc-co.com/epc/products/eganfets/.aspx Static Characteristics (T J = C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BS Drain-to-Source Voltage = V, = µa V SS Drain-Source Leakage = V, = V µa Gate-to-Source Forward Leakage = V I GSS Gate-to-Source Reverse Leakage = - V (TH) Gate Threshold Voltage =, =. ma.8.. V R DS(on) Drain-Source On Resistance = V, =. A 8 mω V SD Source-Drain Forward Voltage I S =. A, = V. V Specifications are with substrate shorted to source where applicable. µa Thermal Characteristics PARAMETER TYP UNIT R JC Thermal Resistance, Junction-to-Case 8. R JB Thermal Resistance, Junction-to-Board R JA Thermal Resistance, Junction-to-Ambient (Note ) 8 Note : R θja is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR board. See http://epc-co.com/epc/documents/product-training/appnote_thermal_performance_of_egan_fets.pdf for details C/W EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
C ISS Dynamic Characteristics (T J = C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Capacitance C OSS Reverse Transfer Capacitance = V, = V pf C RSS Output Capacitance.8. R G Gate Resistance. Ω Q G Total Gate Charge 7 Q GS Gate-to-Source Charge = V, = V, = A Q GD Gate-to-Drain Charge 7 8 pc Q G(TH) Gate Charge at Threshold 9 Q OSS Output Charge = V, = V 9 Q RR Source-Drain Recovery Charge Specifications are with substrate shorted to source where applicable. 8 7 Figure : Typical Output Characteristics at C = = V = GS = 8 7 Figure : Transfer Characteristics C C = V Drain Current (A) Drain Current (A)... Drain-to-Source Voltage (V)..... Figure : R DS(ON) vs for Various Drain Currents Figure : R DS(ON) vs for Various Temperatures Drain-to-Source Resistance (mω) =. A = A =. A = A R DS(ON) Drain-to-Source Resistance (mω) C C = A...... EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
Figure : Capacitance (Linear Scale) Figure A: Capacitance (Log Scale) Capacitance (pf) C C OSS + C SD C ISS + C GS C RSS Capacitance (pf) C C OSS + C SD C ISS + C GS C RSS - Drain-to-Source Voltage (V) Drain-to-Source Voltage (V) Figure : Gate Charge 8 Figure 7: Reverse Drain-Source Characteristics V G Gate Voltage (V) = A = V I SD Source-to-Drain Current (A) 7 C C Q G Gate Charge (pc)..... V SD Source-to-Drain Voltage (V).8 Figure 8: Normalized On Resistance vs Temperature Figure 9: Normalized Threshold Voltage vs Temperature Normalized On-State Resistance R DS(ON)... = A = V Normalized Threshold Voltage (V)....9.8.7 =. ma.8 7 T J Junction Temperature ( C). 7 T J Junction Temperature ( C) EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
. egan FET DATASHEET.. Figure : Gate Current C C Figure : Smith Chart S-Parameter Characteristics VGSQ =.8 V, VDSQ = V, Q =. A Pulsed Measurement, Heat-Sink Installed, Z = Ω I G Gate Current (ma).8.........7.8 GHz.9.... S Gate Reflection S Drain Reflection.8..... 8........7.8.9.....8...... 8... RF Café.....7 MHz MHz..8.... All measurements were done with substrate shortened to source..8.9.. Figure : Gain Chart Figure : Device Reflection Amplitude [db] Frequency (MHz) Gmax Z GS Z DS Figure : Taper and Reference Plane details Device Connection Frequency Gate (Z GS ) Drain (Z DS ) [MHz] [Ω] [Ω]. j8.7.7 j..7 j.8.78 j7.. + j..98 j.. + j.. j.7. + j.7.9 j.98.8 + j8.. + j.7.7 + j..9 + j.8. + j.7.7 + j. S-Parameter Table - Download S-parameter files at www.epc-co.com Micro-Strip design: -layer ½ oz (7. µm) thick copper mil thick RO substrate Device Outline Gate Circuit Reference Plane 7 9 7 9 9 All dimensions in µm Drain Circuit Reference Plane EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
Figure : Transient Thermal Response Curves Z θjb Normalized Thermal Impedance Duty Factors:.... -..... Single Pulse Junction-to-Board - - - - t p Rectangular Pulse Duration (s) P DM t p Notes: Duty Factor = t p /T Peak T J = P DM x Z θjb x R θjb + T B T Z θjc Normalized Thermal Impedance. Duty Factors:.... Junction-to-Case... Notes: Single Pulse Duty Factor = t p /T Peak T J = P DM x Z θjc x R θjc + T C. - - - - - - P DM t p Rectangular Pulse Duration (s) t p T Figure : Safe Operating Area - Drain Current (A) Limited by R DS(on) Pulse Width ms ms ms µs.. Drain Voltage (V) T J = Max Rated, T C = + C, Single Pulse EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
TAPE AND REEL CONFIGURATION mm pitch, 8mm wide tape on 7 reel d e f g Loaded Tape Feed Direction 7 reel b Die orientation dot a c 8 YYYY ZZZZ Gate pad bump is under this corner (note ) Dimension (mm) target min max a 8. 7.9 8. b.7..8 c (see note)... d..9. e..9. f (see note)..9. g... Die is placed into pocket solder bump side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Gate Pad bump is under this corner 8 YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking line Lot_Date Code Marking Line 8 YYYY ZZZZ DIE OUTLINE Solder Bar View B C d g x e A h e i X i f j Dim Micrometers Min Nominal Max A 8 B 8 8 88 C 8 d e f g 7 h 7 i 7 j Side View (8) 8 Max Pad no. is Gate Pad no. is Source Return for Gate Driver Pad no. and are Source Pad no. is Drain Pad no. is Substrate Seating Plane +/- EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
RECOMMENDED LAND PATTERN (measurements in µm) The land pattern is solder mask defined. Solder mask opening is µm smaller per side than bump. 7 8 9 9 9 RECOMMENDED STENCIL DRAWING (measurements in µm) Recommended stencil should be mil ( μm) thick, must be laser cut, openings per drawing. 9 R 7 8 Intended for use with SAC Type solder, reference 88.% metals content. Additional assembly resources available at: http://epc-co.com/epc/designsupport/assemblybasics.aspx 7 7 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. egan is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/aboutepc/patents.aspx Information subject to change without notice. Revised June, 8 EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8 7