Off-line high volage converers Feaures 800 V avalanche rugged power secion PWM operaion wih frequency jiering for low EMI Operaing frequency: 60 khz for L ype 115 khz for H ype Sandby power < 50 mw a 265 Vac Limiing curren wih adjusable se poin Adjusable and accurae over volage proecion On-board sof-sar Safe auo-resar afer a faul condiion Hysereic hermal shudown Applicaion Adapers for PDA, camcorders, shavers, cellular phones, videogames Auxiliary power supply for LCD/PDP TV, moniors, audio sysems, compuer, indusrial sysems, LED driver, No el-cap LED driver SMPS for se-op boxes, DVD players and recorders, whie goods Descripion The device is an off-line converer wih an 800 V rugged power secion, a PWM conrol, wo levels of over curren proecion, over volage and overload proecions, hysereic hermal proecion, sof-sar and safe auo-resar afer any faul condiion removal. Burs mode operaion and device very low consumpion help o mee he sandby energy saving regulaions. Advance frequency jiering reduces EMI filer cos. Brown-ou funcion proecs he swich mode power supply when he recified inpu volage level is below he normal minimum level specified for he sysem. The high volage sar-up circui is embedded in he device. Figure 1. SO16 narrow SO-16 + DC inpu high volage wide range - Typical opology DIP-7 + DC Oupu volage - DRAIN DRAIN BR VIPER17 GND VDD CONT FB Table 1. Device summary Order codes Package Packaging VIPER17LN / VIPER17HN DIP-7 Tube VIPER17HD / VIPER17LD VIPER17HDTR / VIPER17LDTR SO16 narrow Tube Tape and reel July 2009 Doc ID 14419 Rev 6 1/32 www.s.com 32
Conens VIPER17 Conens 1 Block diagram.............................................. 3 2 Typical power............................................... 3 3 Pin seings................................................ 4 4 Elecrical daa.............................................. 5 4.1 Maximum raings............................................ 5 4.2 Thermal daa............................................... 5 4.3 Elecrical characerisics....................................... 6 5 Typical elecrical characerisics.............................. 10 6 Typical circui............................................. 13 7 Operaion descripions...................................... 14 7.1 Power secion and gae driver................................. 14 7.2 High volage sarup generaor................................. 14 7.3 Power-up and sof-sar up.................................... 15 7.4 Power down operaion....................................... 17 7.5 Auo resar operaion........................................ 17 7.6 Oscillaor................................................. 17 7.7 Curren mode conversion wih adjusable curren limi se poin....... 18 7.8 Over volage proecion (OVP)................................. 18 7.9 Abou CONT pin............................................ 20 7.10 Feed-back and over load proecion (OLP)....................... 20 7.11 Burs-mode operaion a no load or very ligh load.................. 23 7.12 Brown-ou proecion........................................ 24 7.13 2nd level over curren proecion and hiccup mode................. 26 8 Package mechanical daa.................................... 27 9 Revision hisory........................................... 31 2/32 Doc ID 14419 Rev 6
Block diagram 1 Block diagram Figure 2. Block diagram BR VDD VDD Vcc DRAIN 0.45V - + Vin_OK Inernal Supply bus & Reference Volages SUPPLY & UVLO HV_ON Isar-up CONT 15uA SOFT START. OCP BLOCK + - OCP UVLO BURST OSCILLATOR TURN-ON LOGIC S THERMAL SHUTDOWN OTP Q OVP LOGIC + - PWM LEB R1 R2 OVP 6uA Ref + - 2nd OCP LOGIC OLP OVP OTP BURST-MODE LOGIC BURST Rsense FB GND 2 Typical power Table 2. Typical power Par number 230 V AC 85-265 V AC Adaper (1) Open frame (2) Adaper (1) Open frame (2) VIPER17 9 W 12 W 5 W 7 W 1. Typical coninuous power in non venilaed enclosed adaper measured a 50 C ambien. 2. Maximum pracical coninuous power in an open frame design a 50 C ambien, wih adequae hea sinking. Doc ID 14419 Rev 6 3/32
Pin seings VIPER17 3 Pin seings Figure 3. Connecion diagram (op view) Noe: The copper area for hea dissipaion has o be designed under he DRAIN pins. Table 3. Pin descripion Pin N. Name DIP-7 SO16 Funcion 1 1...4 GND This pin represens he device ground and he source of he power secion. 2 5 VDD 3 6 CONT 4 7 FB 5 10 BR 7,8 13...16 DRAIN Supply volage of he conrol secion. This pin also provides he charging curren of he exernal capacior during sar-up ime. Conrol pin. The following funcions can be seleced: 1. curren limi se poin adjusmen. The inernal se defaul value of he cycleby-cycle curren limi can be reduced by connecing o ground an exernal resisor. 2. oupu volage monioring. A volage exceeding 3 V shus he IC down reducing he device consumpion. This funcion is srobed and digially filered for high noise immuniy. Conrol inpu for duy cycle conrol. Inernal curren generaor provides bias curren for loop regulaion. A volage below 0.5 V acivaes he burs-mode operaion. A level close o 3.3 V means ha we are approaching he cycle-bycycle over-curren se poin. Brownou proecion inpu wih hyseresis. A volage below 0.45 V shus down (no lach) he device and lowers he power consumpion. Device operaion resars as he volage exceeds 0.45 V plus hyseresis volage. I can be conneced o ground when no used. High volage drain pin. The buil-in high volage swiched sar-up bias curren is drawn from his pin oo. Pins conneced o he meal frame o faciliae hea dissipaion. 4/32 Doc ID 14419 Rev 6
Elecrical daa 4 Elecrical daa 4.1 Maximum raings Table 4. Absolue maximum raings Symbol Pin (DIP7) Parameer Min Value Max Uni V DRAIN 7, 8 Drain-o-source (ground) volage 800 V E AV 7, 8 Repeiive avalanche energy (limied by T J = 150 C) 2 mj I AR 7, 8 Repeiive avalanche curren (limied by T J = 150 C) 1 A I DRAIN 7, 8 Pulse drain curren 2.5 A V CONT 3 Conrol inpu pin volage (wih I CONT = 1 ma) -0.3 Self limied V V FB 4 Feed-back volage -0.3 5.5 V V BR 5 Brown-ou inpu pin volage (wih I BR = 0.5 ma) -0.3 Self limied V V DD 2 Supply volage (I DD = 25 ma) -0.3 Self limied V I DD 2 Inpu curren 25 ma P TOT Power dissipaion a T A < 60 C (SO16N) 1 W Power dissipaion a T A < 40 C (DIP-7) 1 W T J Operaing juncion emperaure range -40 150 C T STG Sorage emperaure -55 150 C 4.2 Thermal daa Table 5. Thermal daa Symbol Parameer Max value SO16N Max value DIP7 Uni R hjp R hja Thermal resisance juncion pin (Dissipaed power = 1 W) Thermal resisance juncion ambien (Dissipaed power = 1 W) R hja Thermal resisance juncion ambien (1) (Dissipaed power = 1 W) 35 40 C/W 90 110 C/W 80 90 C/W 1. When mouned on a sandard single side FR4 board wih 100 mm 2 (0.155 sq in) of Cu (35 μm hick) Doc ID 14419 Rev 6 5/32
Elecrical daa VIPER17 4.3 Elecrical characerisics (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Table 6. Power secion Symbol Parameer Tes condiion Min Typ Max Uni V BVDSS I OFF R DS(on) C OSS Break-down volage OFF sae drain curren Drain-source on sae resisance Effecive (energy relaed) oupu capaciance I DRAIN = 1 ma, V FB = GND T J = 25 C V DRAIN = max raing, V FB = GND I DRAIN = 0.2 A, V FB = 3 V, V BR = GND, T J = 25 C I DRAIN = 0.2 A, V FB = 3 V, V BR = GND, T J = 125 C 800 V 60 μa 20 24 Ω 40 48 Ω V DRAIN = 0 o 640 V 10 pf Table 7. Supply secion Symbol Parameer Tes condiion Min Typ Max Uni Volage V DRAIN_START Drain-source sar volage 60 80 100 V V DRAIN = 120 V, V BR = GND, V FB = GND, -2-3 -4 ma I DDch Sar up charging curren V DD = 4 V V DRAIN = 120 V, V BR = GND, V FB = GND, V DD = 4 V afer faul. -0.4-0.6-0.8 ma V DD Operaing volage range Afer urn-on 8.5 23.5 V V DDclamp V DD clamp volage I DD = 20 ma 23.5 V V DDon V DDoff V DD(RESTART) Curren V DD sar up hreshold V DD under volage shudown hreshold V DD resar volage hreshold V DRAIN = 120 V, V BR = GND, V FB = GND V DRAIN = 120 V, V BR = GND, V FB = GND 13 14 15 V 7.5 8 8.5 V 4 4.5 5 V I DD0 I DD1 I DD_FAULT I DD_OFF Operaing supply curren, no swiching Operaing supply curren, swiching Operaing supply curren, wih proecion ripping Operaing supply curren wih V DD < VDD_off V FB = GND, F SW = 0 khz, V BR = GND, V DD = 10 V V DRAIN = 120 V, F SW = 60 khz V DRAIN = 120 V, F SW = 115 khz 0.9 ma 1.8 ma 2 ma 400 μa V DD = 7 V 270 μa 6/32 Doc ID 14419 Rev 6
Elecrical daa Table 8. Conroller secion (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Symbol Parameer Tes condiion Min Typ Max Uni Feed-back pin V FBolp Over load shu down hreshold 4.5 4.8 5.2 V V FBlin Linear dynamics upper limi 3.2 3.3 3.4 V V FBbm Burs mode hreshold Volage falling 0.4 0.5 0.6 V V FBbmhys Burs mode hyseresis Volage rising 50 mv I FB Feed-back sourced curren V FB = 0.3 V -150-200 -280 ua 3.3 V < V FB < 4.8 V -3 ua R FB(DYN) Dynamic resisance V FB < 3.3 V 14 19 kω H FB ΔV FB / ΔI D 4 9 V/A CONT pin VCONT_l Low level clamp volage I CONT = -100 μa 0.5 V Curren limiaion I Dlim Max drain curren limiaion V FB = 4 V, I CONT = -10 µa T J = 25 C 0.38 0.4 0.42 A SS Sof-sar ime 8.5 ms T ON_MIN Minimum urn ON ime 220 400 480 ns d Propagaion delay 100 ns LEB Leading edge blanking 300 ns I D_BM Peak drain curren during burs mode V FB = 0.6 V 90 ma Oscillaor secion VIPER17L F OSC VIPER17H V DD = operaing volage range, V FB = 1 V 54 103 60 115 66 127 khz khz FD Modulaion deph VIPER17L ±4 khz VIPER17H ±8 khz FM Modulaion frequency 250 Hz D MAX Maximum duy cycle 70 80 % Doc ID 14419 Rev 6 7/32
Elecrical daa VIPER17 Table 8. Conroller secion (coninued) (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Symbol Parameer Tes condiion Min Typ Max Uni Over curren proecion (2 nd OCP) I DMAX Second over curren hreshold 0.6 A Over volage proecion V OVP T STROBE Over volage proecion hreshold Over volage proecion srobe ime 2.7 3 3.3 V 2.2 μs Brown ou proecion V BRh Brown ou hreshold 0.41 0.45 0.49 V Volage hyseresis above V BRhys Volage falling 50 mv V BRh I BRhys Curren hyseresis 7 10 μa V BRclamp Clamp volage I BR = 250 µa 3 V V EN Brown ou enable volage 150 mv V DIS Brown ou disable volage 50 mv Thermal shudown T SD T HYST Thermal shudown emperaure Thermal shudown hyseresis 150 160 C 30 C 8/32 Doc ID 14419 Rev 6
Elecrical daa Figure 4. Minimum urn-on ime es circui Figure 5. Brown ou hreshold es circuis Figure 6. OVP hreshold es circuis (The OVP proecion is riggered afer four consecuive oscillaor cycles) Doc ID 14419 Rev 6 9/32
Typical elecrical characerisics VIPER17 5 Typical elecrical characerisics Figure 7. Curren limi vs T J Figure 8. Swiching frequency vs T J Figure 9. Drain sar volage vs T J Figure 10. HFB vs T J Figure 11. Brown ou hreshold vs T J Figure 12. Brown ou hyseresis vs T J 10/32 Doc ID 14419 Rev 6
Typical elecrical characerisics Figure 13. Brown ou hyseresis curren Figure 14. Operaing supply curren vs T J (no swiching) vs T J Figure 15. Operaing supply curren Figure 16. curren limi vs R LIM (swiching) vs T J Figure 17. Power MOSFET on-resisance Figure 18. Power MOSFET break down vs T J volage vs T J Doc ID 14419 Rev 6 11/32
Typical elecrical characerisics VIPER17 Figure 19. Thermal shudown T J T SD T HYST V DD V DD ON V DD OFF V DD RESTART V DS 12/32 Doc ID 14419 Rev 6
Typical circui 6 Typical circui Figure 20. Min-feaures flyback applicaion D3 Vou AC IN BR C1 C2 R1 C5 AC IN D1 GND R2 D2 R3 BR VVcc DD DRAIN OPTO R5 C3 CONT CONTROL FB SOURCE GND U2 R4 C6 C4 R6 Figure 21. Full-feaures flyback applicaion D3 Vou AC IN BR C1 Rh C2 R1 C5 AC IN Rl D1 Rovp Daux GND R2 D2 R3 BR VVcc DD DRAIN OPTO R5 C3 CONT CONTROL FB SOURCE GND U2 R4 C6 Rlim C4 R6 Doc ID 14419 Rev 6 13/32
Operaion descripions VIPER17 7 Operaion descripions VIPER17 is a high-performance low-volage PWM conroller chip wih an 800 V, avalanche rugged Power secion. The conroller includes: he oscillaor wih jiering feaure, he sar up circuis wih sof-sar feaure, he PWM logic, he curren limi circui wih adjusable se poin, he second over curren circui, he burs mode managemen, he brown-ou circui, he UVLO circui, he auo-resar circui and he hermal proecion circui. The curren limi se-poin is se by he CONT pin. The burs mode operaion guaranies high performance in he sand-by mode and helps in he energy saving norm accomplishmen. All he faul proecions are buil in auo resar mode wih very low repeiion rae o preven IC's over heaing. 7.1 Power secion and gae driver The power secion is implemened wih an avalanche ruggedness N-channel MOSFET, which guaranees safe operaion wihin he specified energy raing as well as high dv/d capabiliy. The Power secion has a BV DSS of 800 V min. and a ypical R DS(on) of 20 Ω a 25 C. The inegraed SenseFET srucure allows a virually loss-less curren sensing. The gae driver is designed o supply a conrolled gae curren during boh urn-on and urnoff in order o minimize common mode EMI. Under UVLO condiions an inernal pull-down circui holds he gae low in order o ensure ha he Power secion canno be urned on accidenally. 7.2 High volage sarup generaor The HV curren generaor is supplied hrough he DRAIN pin and i is enabled only if he inpu bulk capacior volage is higher han V DRAIN_START hreshold, 80 V DC ypically. When he HV curren generaor is ON, he IDD_ch curren (3 ma ypical value) is delivered o he capacior on he V DD pin. In case of Auo Resar mode afer a faul even, he IDD_ch curren is reduced o 0.6 ma, yp. in order o have a slow duy cycle during he resar phase. 14/32 Doc ID 14419 Rev 6
Operaion descripions 7.3 Power-up and sof-sar up If he inpu volage rises up ill he device sar level (V DRAIN_START ), he V DD volage begins o grow due o he IDD_ch curren (see Table 7 on page 6) coming from he inernal high volage sar up circui. If he V DD volage reaches V DDon hreshold (~14 V) he power MOSFET sars swiching and he HV curren generaor is urned OFF. See Figure 23 on page 16. The IC is powered by he energy sored in he capacior on he VDD pin, C VDD, unil when he self-supply circui (ypically an auxiliary winding of he ransformer and a seering diode) develops a volage high enough o susain he operaion. C VDD capacior mus be sized enough o avoid fas discharge and keep he needed volage value higher han V DDoff hreshold. In fac, a oo low capaciance value could erminae he swiching operaion before he conroller receives any energy from he auxiliary winding. The following formula can be used for he V DD capacior calculaion: Equaion 1 I C DDch SSaux VDD = ---------------------------------------- V DDon V DDoff The SSaux is he ime needed for he seady sae of he auxiliary volage. This ime is esimaed by applicaor according o he oupu sage configuraions (ransformer, oupu capaciances, ec.). During he converer sar up ime, he drain curren limiaion is progressively increased o he maximum value. In his way he sress on he secondary diode is considerably reduced. I also helps o preven ransformer sauraion. The sof-sar ime lass 8.5 ms and he feaure is implemened for every aemp of sar up converer or afer a faul. Figure 22. Sar up I DD curren I DD V DS = 120V F SW = 0 khz 2 ma AFTER FAULT 1 ma IDD0 I DD_FAULT IDD_OFF IDS_CH_FAULT -1 ma V DDresar V DDoff V DDon V DD -2 ma -3 ma IDS_CH -4 ma Doc ID 14419 Rev 6 15/32
Operaion descripions VIPER17 Figure 23. Timing diagram: normal power-up and power-down sequences Vin V Sar V DD Vcc V Vcc DD ON V Vcc DD OFF regulaion is los here V Vcc DD resar V DRAIN IDD_CH I charge 3 ma Power -on Normal operaion Power - off Figure 24. Sof-sar: iming diagram IDRAIN ss IDLIM VFB V FB OLP V FB_lin 16/32 Doc ID 14419 Rev 6
Operaion descripions 7.4 Power down operaion A converer power down, he sysem loses regulaion as soon as he inpu volage is so low ha he peak curren limiaion is reached. The V DD volage drops and when i falls below he V DDoff hreshold (8 V ypical) he power MOSFET is swiched OFF, he energy ransfers o he IC inerruped and consequenly he V DD volages decreases, Figure 23 on page 16. Laer, if he V IN is lower han V DRAIN_START (80 V ypical), he sar up sequence is inhibied and he power down compleed. This feaure is useful o preven converer s resar aemps and ensures monoonic oupu volage decay during he sysem power down. 7.5 Auo resar operaion If afer a converer power down, he V IN is higher han V DRAIN_START, he sar up sequence is no inhibied and will be acivaed only when he V DD volage drops down he V DDresar hreshold (4.5 V ypical). This means ha he HV sar up curren generaor resars he V DD capacior charging only when he V DD volage drops below V DDresar. The scenario above described is for insance a power down because of a faul condiion. Afer a faul condiion, he charging curren is 0.6 ma (yp.) insead of he 3 ma (yp.) of a normal sar up converer phase. This feaure ogeher wih he low V DDresar hreshold (4.5 V) ensures ha, afer a faul, he resar aemps of he IC has a very long repeiion rae and he converer works safely wih exremely low power hroughpu. The Figure 25 shows he IC behavioral afer a shor circui even. Figure 25. Timing diagram: behavior afer shor circui Shor circui occurs here V DD V DDON V DD OFF V DDres VDS Trep < 0.03Trep IDD_CH IDD_CH 0.6 ma FB Pin 4.8 V 3.3 V Doc ID 14419 Rev 6 17/32
Operaion descripions VIPER17 7.6 Oscillaor The swiching frequency is inernally fixed o 60 khz or 115 khz. In boh case he swiching frequency is modulaed by approximaely ±4 khz (60 khz version) or ±8 khz (115 khz version) a 250 Hz (ypical) rae, so ha he resuling spread-specrum acion disribues he energy of each harmonic of he swiching frequency over a number of sideband harmonics having he same energy on he whole bu smaller ampliudes. 7.7 Curren mode conversion wih adjusable curren limi se poin The device is a curren mode converer: he drain curren is sensed and convered in volage ha is applied o he non invering pin of he PWM comparaor. This volage is compared wih he one on he feed-back pin hrough a volage divider on cycle by cycle basis. The VIPER17 has a defaul curren limi value, I DLIM, ha he designer can adjus according he elecrical specificaion, by he R LIM resisor conneced o he CONT see Figure 16 on page 11. The CONT pin has a minimum curren sunk needed o acivae he I DLIM adjusmen: wihou R LIM or wih high R LIM (i.e. 100 KΩ) he curren limi is fixed o he defaul value (see I DLIM, Table 8 on page 7). 7.8 Over volage proecion (OVP) The device can monior he converer oupu volage. This operaion is done by CONT pin during power MOSFET OFF-ime, when he volage generaed by he auxiliary winding racks converer's oupu volage, hrough urn raio N -------------- AUX See Figure 26. In order o perform he oupu volage monior, he CONT pin has o be conneced o he aux winding hrough a resisor divider made up by R LIM and R OVP (see Figure 21 and Figure 27). If he volage applied o he CONT pin exceeds he inernal 3 V reference for four consecuive imes he conroller recognizes an over volage condiion. This special feaure uses an inernal couner; ha is o reduce sensiiviy o noise and preven he lach from being erroneously acivaed. see Figure 26 on page 20. The couner is rese every ime he OVP signal is no riggered in one oscillaor cycle. Referring o he Figure 21, he resisors divider raio k OVP will be given by: Equaion 2 N SEC k OVP N AUX N SEC V OVP = -------------------------------------------------------------------------------------------------- -------------- ( V OUTOVP + V DSEC ) V DAUX 18/32 Doc ID 14419 Rev 6
Operaion descripions Equaion 3 k OVP = R --------------------------------- LIM R LIM + R OVP Where: V OVP is he OVP hreshold (see Table 8 on page 8) V OUT OVP is he converer oupu volage value o acivae he OVP (se by designer) designer N AUX is he auxiliary winding urns N SEC is he secondary winding urns V DSEC is he secondary diode forward volage V DAUX is he auxiliary diode forward volage R OVP ogeher R LIM make he oupu volage divider Than, fixed R LIM, according o he desired I DLIM, he R OVP can be calculaing by: Equaion 4 1 k OVP R OVP = R LIM ---------------------- k OVP The resisor values will be such ha he curren sourced and sunk by he CONT pin be wihin he raed capabiliy of he inernal clamp. Doc ID 14419 Rev 6 19/32
Operaion descripions VIPER17 Figure 26. OVP iming diagram V DS VAUX 0 CONT (pin 4) 3V STROBE 2 µs 0.5 µs OVP COUNTER RESET COUNTER STATUS FAULT 0 0 0 0 1 1 2 2 0 0 0 1 1 2 2 3 3 4 NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE 7.9 Abou CONT pin Referring o he Figure 27, hrough he CONT PIN, he below feaures can be implemened: 1. Curren Limi se poin 2. Over volage proecion on he converer oupu volage The Table9 on page21 referring o he Figure 27, liss he exernal resisance combinaions needed o acivae one or plus of he CONT pin funcions. Figure 27. CONT pin configuraion Daux Rovp CONT SOFT START Curr. Lim. BLOCK Curren Limi OCP Comparaor - + To PWM Logic Auxiliary winding Rlim OVP DETECTION LOGIC From SenseFET To OVP Proecion 20/32 Doc ID 14419 Rev 6
Operaion descripions Table 9. CONT pin configuraions Funcion / componen R LIM (1) R OVP D AUX I Dlim reducion See Figure 8 No No OVP 80 KΩ See Equaion 4 Yes I Dlim reducion + OVP See Figure 8 See Equaion 4 Yes 1. R LIM fixed before R OVP 7.10 Feed-back and over load proecion (OLP) The VIPER17 is a curren mode converer: he feedback pin conrols he PWM operaion, conrols he burs mode and acives he overload proecion of he device. Figure 28 on page 23 and Figure 29 show he inernal curren mode srucure. Wih he feedback pin volage beween V FBbm and V FBlin, (respecively 0.5 V and 3.3 V, ypical values) he drain curren is sensed and convered in volage ha is applied o he non invering pin of he PWM comparaor. This volage is compared wih he one on he feedback pin hrough a volage divider on cycle by cycle basis. When hese wo volages are equal, he PWM logic orders he swich off of he power MOSFET. The drain curren is always limied o I DLIM value. In case of overload he feedback pin increases in reacion o his even and when i goes higher han V FBlin he drain curren is limied or o he defaul I DLIM value or he one imposed hrough a resisor a he CONT pin (using he R LIM, see Figure 16 on page 11); he PWM comparaor is disabled. A he same ime an inernal curren generaor sars o charge he feedback capacior (C FB ) and when he feedback volage reaches he V FBolp hreshold, he converer is urned off and he sar up phase is acivaed wih reduced value of I charge o 0.6 ma. During he firs sar up phase of he converer, afer he sof-sar up ime (ypical value is 8.5 ms) he oupu volage could force he feedback pin volage o rise up o he V FBolp hreshold ha swiches off he converer iself. To avoid his even, he appropriae feedback nework has o be seleced according o he oupu load. More he nework feedback fixes he compensaion loop sabiliy. The Figure 28 on page 23 and Figure 29 show he wo differen feedback neworks. The ime from he over load deecion (VFB = V FBlin ) o he device shudown (VFB = V FBolp ) can be calculaing by C FB value (see Figure 28 on page 23 and Figure 29), using he formula: Equaion 5 V FBolp V FBlin T OLP delay = C FB --------------------------------------- 3μA In he Figure 28, he capacior conneced o FB pin (C FB ) is used as par of he circui o compensae he feedback loop bu also as elemen o delay he OLP shu down owing o he ime needed o charge he capacior (see equaion 5). Doc ID 14419 Rev 6 21/32
Operaion descripions VIPER17 Afer he sar up ime, 8.5 ms yp value, during which he feedback volage is fixed a V FBlin, he oupu capacior could no be a is nominal value and he conroller inerpreer his siuaion as an over load condiion. In his case, he OLP delay helps o avoid an incorrec device shu down during he sar up. Owing o he above consideraions, he OLP delay ime mus be long enough o by-pass he iniial oupu volage ransien and check he over load condiion only when he oupu volage is in seady sae. The oupu ransien ime depends from he value of he oupu capacior and from he load. When he value of he C FB capacior calculaed for he loop sabiliy is oo low and canno ensure enough OLP delay, an alernaive compensaion nework can be used and i is showed in Figure 29 on page 23. Using his alernaive compensaion nework, wo poles (f PFB, f PFB1 ) and one zero (f ZFB ) are inroduced by he capaciors C FB and C FB1 and he resisor R FB1. The capacior C FB inroduces a pole (f PFB ) a higher frequency han f ZB and f PFB1. This pole is usually used o compensae he high frequency zero due o he ESR (Equivalen Series Resisor) of he oupu capaciance of he fly-back converer. The mahemaical expressions of hese poles and zero frequency, considering he scheme in Figure 29 are repored by he equaions below: Equaion 6 f ZFB 1 = 2 π C FB1 R FB1 Equaion 7 f PFB R = 2 π C FB(DYN) FB + R FB1 ( R R ) FB(DYN) FB1 Equaion 8 f PFB1 = 2 π C FB1 ( R + R ) FB(DYN) The R FB(DYN) is he dynamic resisance seen by he FB pin. The C FB1 capacior fixes he OLP delay and usually C FB1 resuls much higher han C FB. The Equaion 5 can be sill used o calculae he OLP delay ime bu C FB1 has o be considered insead of C FB. Using he alernaive compensaion nework, he designer can saisfy, in all case, he loop sabiliy and he enough OLP delay ime alike. 1 FB1 22/32 Doc ID 14419 Rev 6
Operaion descripions Figure 28. FB pin configuraion PWM CONTROL From sense FET PWM To PWM Logic + - Cfb BURST-MODE REFERENCES BURST-MODE LOGIC BURST OLP comparaor + To disable logic 4.8V - Figure 29. FB pin configuraion PWM CONTROL From sense FET PWM To PWM Logic + - Rfb1 Cfb1 Cfb BURST-MODE REFERENCES BURST-MODE LOGIC BURST OLP comparaor + To disable logic 4.8V - 7.11 Burs-mode operaion a no load or very ligh load When he volage on feedback pin falls down 50 mv below he burs mode hreshold, V FBbm, power MOSFET is no more allowed o be swiched on. I can be swiched on again if he volage on feedback pin exceeds V FBbm. The volage on PWM comparaor non invering inernal inpu, conneced o feedback pin hrough a resisive volage divider, is lower clamped o a cerain value leading o a minimum value, of 90 ma (yp.) for he drain peak curren. When he load decrease he feedback loop reacs lowering he feedback pin volage. As he volage goes 50 mv below V FBbm MOSFET sops swiching. Afer he MOSFET sops, as a resul of he feedback reacion o he energy delivery sop, he feedback pin volage increases and exceeding V FBbm hreshold MOSFET he power device sar swiching again. Figure 30 shows his behavior called burs mode. Sysems alernaes period of ime where power MOSFET is swiching o period of ime where power MOSFET is no swiching. The power delivered o oupu during swiching periods exceeds he load power demands; he excess of power is balanced from no swiching period where no power is processed. The advanage of burs mode operaion is an average swiching frequency much lower hen he Doc ID 14419 Rev 6 23/32
Operaion descripions VIPER17 normal operaion working frequency, up o some hundred of herz, minimizing all frequency relaed losses. Figure 30. Burs mode iming diagram, ligh load managemen FB VFBbm 100 50 mv hyser. I DS Normal - mode Burs-mode Normal - mode 7.12 Brown-ou proecion Brown-ou proecion is a no-lached shudown funcion acivaed when a condiion of mains under volage is deeced. The Brown-ou comparaor is inernally referenced o V BRh,0.45 V yp value, and disables he PWM if he volage applied a he BR pin is below his inernal reference. Under his condiion he power MOSFET is urned off. Unil he Brown ou condiion is presen, he VDD volage coninuously oscillaes beween he V DDon and he UVLO hresholds, as shown in he iming diagram of Figure 31 on page 25. A volage hyseresis is presen o improve he noise immuniy. The swiching operaion is resared as he volage on he pin is above he reference plus he before said volage hyseresis. See Figure 31. The Brown-ou comparaor is provided also wih a curren hyseresis, I BRhys.Wih his approach is possible o se he V INon hreshold and V INoff hresholds separaely, by properly choosing he resisors of he divider connec o he BR pin. 24/32 Doc ID 14419 Rev 6
Operaion descripions Figure 31. Brown-ou proecion: BR exernal seing and iming diagram HV Inpu bus VinON VinOFF BR V DD Vcc 0.45V HV Inpu bus VinOK Rh BR 0.1V 0.45V + - + - AC_OK Disable VinOK IBRhys 15 µa V DD Vcc (pin 3) Rl 10u VDS Vou Fixed he V INon and he V INoff levels, wih reference o Figure 31, he following relaionships can be esablished for he calculaion of he resisors R H and R L : Equaion 9 VBRhys VINon VINoff VBRhys V R L = + I V V I BRhys INoff BRh BRh BRhys Equaion 10 V R = H INon V I INoff BRhys V BRhys R L + R V I L BRhys BRhys For a proper operaion of his funcion, V IN on mus be less han he peak volage a minimum mains and V IN off less han he minimum volage on he inpu bulk capacior a minimum mains and maximum load. The BR pin is a high impedance inpu conneced o high value resisors, hus i is prone o pick up noise, which migh aler he OFF hreshold when he converer operaes or gives origin o undesired swich-off of he device during ESD ess. I is possible o bypass he pin o ground wih a small film capacior (e.g. 1-10 nf) o preven any malfuncioning of his kind. If he brown-ou funcion is no used he BR pin has o be conneced o GND, ensuring ha he volage is lower han V DIS (see Table 8). In order o enable he brown-ou funcion he BR pin volage has o be higher han V EN (see Table 8) Doc ID 14419 Rev 6 25/32
Operaion descripions VIPER17 7.13 2 nd level over curren proecion and hiccup mode The VIPER17 is proeced agains shor circui of he secondary recifier, shor circui on he secondary winding or a hard-sauraion of fly-back ransformer. Such as anomalous condiion is invoked when he drain curren exceed 0.6 A ypical. To disinguish a real malfuncion from a disurbance (e.g. induced during ESD ess) a warning sae is enered afer he firs signal rip. If in he subsequen swiching cycle he signal is no ripped, a emporary disurbance is assumed and he proecion logic will be rese in is idle sae; oherwise if he 2 nd OCP hreshold is exceeded for wo consecuive swiching cycles a real malfuncion is assumed and he power MOSFET is urned OFF. The shudown condiion is lached as long as he device is supplied. While i is disabled, no energy is ransferred from he auxiliary winding; hence he volage on he V DD capacior decays ill he V DD under volage hreshold (V DDoff ), which clears he lach. The sar up HV curren generaor is sill off, unil V DD volage goes below is resar volage, V DDres. Afer his condiion he V DD capacior is charged again by 600 µa curren, and he converer swiching resar if he V DDon occurs. If he faul condiion is no removed he device eners in auo-resar mode. This behavioral, resuls in a low-frequency inermien operaion (Hiccup-mode operaion), wih very low sress on he power circui. See he iming diagram of Figure 32. Figure 32. Hiccup-mode OCP: iming diagram V DD Vcc V DD ON V DD OFF Secondary diode is shored here V Vccres DD IDRAIN IDmax VDS 26/32 Doc ID 14419 Rev 6
Package mechanical daa 8 Package mechanical daa In order o mee environmenal requiremens, ST offers hese devices in differen grades of ECOPACK packages, depending on heir level of environmenal compliance. ECOPACK specificaions, grade definiions and produc saus are available a: www.s.com. ECOPACK is an ST rademark. Table 10. Dim. DIP-7 mechanical daa mm Typ Min Max A 5,33 A1 0,38 A2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 D 9,27 9,02 10,16 E 7,87 7,62 8,26 E1 6,35 6,10 7,11 e 2,54 ea 7,62 eb 10,92 L 3,30 2,92 3,81 M (6)(8) 2,508 N 0,50 0,40 0,60 N1 0,60 O (7)(8) 0,548 1- The leads size is comprehensive of he hickness of he leads finishing maerial. 2- Dimensions do no include mold prorusion, no o exceed 0,25 mm in oal (boh side). 3- Package ouline exclusive of meal burrs dimensions. 4- Daum plane H coinciden wih he boom of lead, where lead exis body. 5- Ref. POA MOTHER doc. 0037880 6- Creepage disance > 800 V 7- Creepage disance 250 V 8- Creepage disance as shown in he 664-1 CEI / IEC sandard. Doc ID 14419 Rev 6 27/32
Package mechanical daa VIPER17 Figure 33. Package dimensions 28/32 Doc ID 14419 Rev 6
Package mechanical daa Table 11. SO16 narrow mechanical daa Dimensions Ref. Daabook (mm.) Min Typ. Max A 1.75 A1 0.1 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 0.1 Doc ID 14419 Rev 6 29/32
Package mechanical daa VIPER17 Figure 34. Package dimensions 30/32 Doc ID 14419 Rev 6
Revision hisory 9 Revision hisory Table 12. Documen revision hisory Dae Revision Changes 14-Feb-2008 1 Iniial release 19-Feb-2008 2 Updaed: Figure 1 on page 1, Figure 3 on page 4 21-Jul-2008 3 Added new SO16 package 30-Sep-2008 4 Updaed Equaion 9, Equaion 10 16-Jan-2009 5 Updaed Chaper 7.13 on page 26 20-Jul-2009 6 Updaed applicaion paragraph in coverpage and Table 8 on page 7 Doc ID 14419 Rev 6 31/32
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