Dokic: A Review on Energy Efficient CMOS Digital Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 55 A Review on Energy Efficient CMOS Digitl Logic Brnko L. Dokić University of Bnj Luk Fculty of Electricl Engineering Ptre 5, 78000 Bnj Luk Bosni nd Herzegovin dokic@etfl.net Astrct Autonomy of power supply used in portle devices directly depends on energy efficiency of digitl logic. This mens tht digitl systems, eside high processing power nd very complex functionlity, must lso hve very low power consumption. Power consumption depends on mny fctors: system rchitecture, technology, sic cells topology-speed, nd ccurcy of ssigned tsks. In this pper, review nd comprison of CMOS topologies techniques nd operting modes is given, s CMOS technology is expected to e the optimum choice in the ner future. It is shown tht there is full nlogy in the ehvior of digitl circuits in su-threshold nd strong inversion. Therefore, synthesis of digitl circuits is the sme for oth strong nd wek operting modes. Anlysis of the influence of the technology, MOS trnsistor threshold voltge ( t ) nd power supply voltge ( dd ) on digitl circuit power consumption nd speed for oth operting modes is given. It is shown tht optiml power consumption (minimum power consumption for given speed) depends on optiml choice of threshold, nd power supply voltge. Multi dd / t techniques re nlyzed s well. A review nd nlysis of lterntive logicl circuit's topologies pss logic (PL), complementry pss logic (CPL), push-pull pss logic (PPL) nd ditic logic is lso given. As shown, ditic logic is the optimum choice regrding energy efficiency. Keywords: topology; technology; power consumption; logic dely; CMOS; strong nd wek inversion; sttic nd dynmic chrcteristics; pss logic; ditic logic; PL; CPL; PPL; ECRL I. INTRODUCTION Designers of digitl circuits re confronted with two often conflicting demnds: how to chieve higher operting speeds nd lower energy consumption. Usully, the sme circuit fmily could not stisfy oth demnds t the sme time, i.e. high-speed circuits hve high level of consumption nd vice vers. Tht s how series of integrted circuits clled low-power circuits or high-speed circuits were creted. Optimlly designed digitl system includes vriety of different series of the sme integrted circuits' fmily. Tody, s the whole digitl system is mnufctured s single integrted circuit, the designing prolem is reduced to the choice of design tht cn ensure mximum energy efficiency. Tht implies the design with minimum power consumption inside the specified frequency rnge or mximum operting speed for given energy consumption level. The usge of low-power sources of power supply, which collect their primry energy from the environment, hs incresed ltely. Thus, the rt of design of low power circuits is rought down to the selection of optiml (intelligent) solutions tht will reduce the speed of informtion processing s much s possile, without violting certin system chrcteristics. Such n optiml project implies the decomposition of the system rchitecture, good choice of the circuit topology tht will provide the optiml synthesis of different functions in the defined rchitecture, nd good choice of the circuit design technology. This requires the designer to e fmilir with components, circuits nd systems. Consumption of ech system is determined using the following five guidelines of ech project: given tsk, technology, circuit topology, operting speed nd ccurcy. Since these five guidelines cn e plced on the fingers of one hnd, they re known s low-power hnd [1]. Therefore, optimiztion of energy consumption is multidimensionl prolem tht requires tking into considertion the level of consumption t ech stge of the LSI integrted circuit design. The iggest svings of electricl energy consumption (10 to 0 times), with lest wste of time (t the level of minute) is done in the erly stges of designing, in which the project is presented s set of strct communiction tsks []. The ppliction of optimiztion techniques nd consumption provides n estimtion t ech project stge, leding to optiml consumption project [3]. At lower levels of the design (trnsistor, deployment nd connectivity), possile energy svings re significntly lower (10 to 0%), nd time estimtion cn lst for dys, ecuse the project is presented with ll detil. Thus, it is necessry to process very lrge mount of dt [3]. CMOS digitl circuits technology sed on silicon will most likely e dominnt for the next twenty yers or more [4, 5, 6], with stndrd low power consumption, technology for reducing the trnsistor size to scle of out ten nnometers nd operting speed in the GHz domin. During the lst ten yers, more ttention from reserchers s well s mnufcturer of integrted circuits is pid to digitl CMOS circuits operting in the su-threshold (wek inversion) regime. Supply voltge in this regime is lower thn the threshold voltge t of MOS trnsistors ( dd < t ) nd is out few hundred millivolts. Thnks to tht fct, the dynmic consumption level is significntly reduced in regrd to CMOS circuits operting in the strong inversion regime. Since the operting re in the su-threshold regime is overlpped with the re of disconnected trnsistors in strong inversion regime, current rtio in on nd off the stte hs een significntly reduced. Consequently, CMOS circuit logic dely www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 553 in the su-threshold regime is severl orders of mgnitude higher. Designers of CMOS digitl devices, especilly portle ones, hve chllenging requirement: how to ensure high processing power nd very complex functionlity long with low power consumption. Certinly prt of the solution is proper choice of CMOS technology s well s wek nd strong inversion regime operting res. Although MOS trnsistor sttic chrcteristics in wek inversion nd strong inversion regimes re functionlly very different, it will e shown tht there is n solute nlogy in the ehvior nd functionl dependency of CMOS circuit prmeters in those regimes. Thnks to tht, design techniques of more complex CMOS circuits re the sme in su-threshold nd strong inversion regime. This fct considerly fcilittes designer's work of CMOS circuit in su-threshold regime nd enles fster development. Optiml consumption generlly does not men miniml consumption. Miniml consumption nd miniml logic dely re mutully opposite requirements. Tking into ccount only the minimiztion of consumption, project with uncceptle logic dely could e delivered. The consumption s well s the logic dely of CMOS circuit depends on MOS trnsistor threshold voltge t nd supply voltge dd. Becuse of tht, one prt of this pper is devoted to consumption optimiztion techniques in systems with multiple levels of t nd dd. Specific prt of this pper refers to the ig toe of lowpower hnd topologies. Review of topologies of CMOS logic series tht ensure low-power within the specified rnge of operting frequencies is given, which implies their use in oth strong nd wek inversion regimes. The nlysis is sed on simplified current-voltge models of MOS trnsistors nd PSPICE softwre using prmeters of 180 nm technology. II. CMOS OPERATING IN THE WEAK INERSION REGIME In essence, there re three res of MOS trnsistor sttic chrcteristics [7]. Figure 1 shows the logrithmic dependence of nmos trnsistor drin current s function of gte-source voltge ( gs ), t constnt drin-source voltge ( ds ) nd source-sustrte voltge ( s ). In the literture, the smllest ttention is pid to the medium (moderte) re which is mostly considered s prt of strong inversion threshold re [8, 9]. In digitl circuits, it is ssumed tht gs > t, where t is MOS trnsistor s threshold voltge, trnsistor is operting in strong inversion regime, nd for gs < t in the su-threshold (wek inversion) regime. Therefore, from tody s ppliction point of view, it cn e sid tht t is gte-source voltge on order etween the wek nd the strong inversion regime. It is well-known fct tht the I d ( ds, gs ) chrcteristic in the strong inversion regime hs two res: non-sturted nd sturted. In the non-sturted re, it holds tht I d ~ gs nd I d ~ ds, while in sturted re I d ~ gs nd I d f( ds ), tht is I d const s function of ds. MOS trnsistor chrcteristics in the wek inversion regime re defined s follows: gs t nϕ ϕ t ds/ t I0e ( e ) ds < Dsu = gs t nϕt I0e ds > ϕt I where 1, 3 ϕ, non-sturted re t ( ), 3, sturted re, 1 W I = µ C ( n 1) ϕ 0 0 ox t L is drin current on order etween wek nd strong inversion. Fig. 1. log I d chrcteristic s function of gs t constnt ds nd s The mening of the prmeters in (1) nd () re the following: µ 0 is moility of mjor chrge crriers (electrons nd holes in nmos to pmos trnsistor), C ox = ε ox / t ox is gte cpcitnce (ε ox is dielectric constnt, t ox is thickness of the gte oxide), W nd L re the width nd length of the chnnel, respectively, φ t =kt/q is therml potentil (φ t =6 m t T=300K), where n=1+c d /C ox 1.5 is grdient fctor. For ds >3φ t, drin current is lmost independent of the voltge ds (Figure ), so tht the re nlogous to strong inversion regime, cn e treted s sturted re. In this re it holds ~ gs I e. For d ds <3φ t, t gs =const., ds I d ~ e, trnsistor is in the non-sturted re. Thnks to the nlogy in the field of MOS trnsistor chrcteristics, there is n pproprite nlogy of opertion nd CMOS logic circuit chrcteristics [8]. Thus, for exmple, voltge nd current sttic chrcteristics in the wek inversion regime (Figure 3) hve the sme shpe s in the strong inversion regime. Even inverter threshold voltge Tsu is () www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 554 otined in the sme wy equting of nmos nd pmos drin currents in the sturted re of chrcteristics. 300m 00m 100m 1 5 8/3 9 ) 0 150pA () Tsu ) 100pA I ddmsu 50pA 5 8/3 1 SEL>> 0A 50m 100m 150m 00m 50m ID(Mn) vin1 9 Fig.. I d( gs, ds) in wek inversion regime It results with inverter threshold voltge Tsu in the suthreshold regime [8]: Tsu nϕ = ln I ddsu t on, Iop nd mximl current from the voltge source: where Iop I = I e ddmsu on I on ddsu/ t nϕt, (3) (4) Fig. 3. () PSPICE voltge nd () current trnsfer chrcteristic of CMOS inverter in the su-threshold regime, for chnnel width rtios W p /W n={1, 8/3, 5, 9} t equl chnnel length (L n=l p) nd ddsu = 300 m Considering the ehvior nlogy nd CMOS inverter chrcteristics in the wek nd strong inversion regime, there is n nlogy even t synthesis of more complex circuits. In oth regimes, more complex digitl circuits consist of dul nmos nd pmos trnsistor networks (Figure 4). Dulity implies tht seril connection of nmos trnsistors is corresponding to prllel connection of pmos trnsistors nd vice vers. 3ϕ t < ddsu < t = tn = tp (5) is supply voltge, tn nd tp threshold voltges, nd I on nd I op currents on the order etween wek nd strong inversion of nmos nd pmos trnsistors, respectively. For symmetric inverter (I on =I op ), threshold voltge is, just like in strong inversion regime, Tsu = ddsu /. Miniml supply voltge, ccording to [7] is ddmin =3φ t =78 m. For ddsu >3φ t, the I d ( gs, ds ) chrcteristic hs oth sturted nd non-sturted res, which is necessry for stisfying the qulity of digitl circuit trnsfer chrcteristic o ( i ). However, logic circuits cn operte even t dd <3φ t. Thus, for exmple, some uthors [9] stte constrints dd >57 m, while others [10] clim tht dd >48 m. As in strong inversion regime, threshold voltge Tsu nd mximl current I ddmsu in the su-threshold regime oth depend on nmos nd pmos trnsistor geometry (Figure 3), except tht I ddmsu ~(W n /W p ) -1/ nd Tsu ~ln(w n /W p ), where W n nd W p re the chnnel widths of nmos nd pmos trnsistors, respectively. Fig. 4. Topology of the circuit with logicl function + dul networks: + c (nmos) nd ( + ) c consisted of c (pmos) In oth regimes, logic circuit trnsfer chrcteristic depends on the numer of inputs nd numer of ctive inputs [8]. Figure 5 shows the trnsfer chrcteristics of NOR3 logic circuit with ll inputs ctivted, nd when the ctivted input is the one pplied to the gte of pmos trnsistor whose source is connected on power-supply line dd. www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 555 out [] out [] 0.3 0.5 0. 0.15 0.1 0.05 0 0.05 0.1 0.15 0. 0.5 in [] 0.3 0.5 0. 0.15 0.1 0.05 i 0 0.05 0.1 0.15 0. 0.5 in [] Fig. 5. PSPICE trnsfer chrcteristics of () NOR3 nd () NAND circuits in the wek inversion regime, with ll inputs ctivted, nd when the ctivted input is the one pplied on the gte of seril trnsistor whose source connected on power supply line. In NAND circuits, the highest threshold voltge is otined when ll inputs re ctive, nd the lowest when the ctive input is only the one pplied to the gte of nmos trnsistors, whose source is connected to the ground (Figure 5). Optiml trnsistor geometry of m-input NAND nd NOR circuits is the sme in oth regimes nd is defined s follows [1]: III. i ) 1 ) www.etsr.com NIm: NILIm: W / L µ n n p = m W / L µ p p n W / L 1 µ n n p =. W / L m µ p p n CMOS CIRCUIT POWER CONSUMPTION Electric power consumption consists of two components: sttic nd dynmic (6) P = P + P. (7) D DS DD Sttic consumption is result of existing MOS trnsistor currents in sttic sttes nd is defined s: P = I, (8) DS S dd where I S represents the sttic current in totl. There re four min sources of sttic current in CMOS circuits: Tunneling current through the gte (I g ), Su-threshold drin current (I dsu ), i i Inverse polrized p-n junction current (I DSS ), Hot chrge crrier injection gte current (I H ). The first three components hve dominnt influence on CMOS circuit sttic consumption level. Scling of the dimensions of MOS trnsistors decreses oxide thickness elow the gte (t ox ). Therefore, the electric field through gte oxide increses, which leds to the tunneling effect of chrge crriers from gte to sustrte or from sustrte to gte. The gte current hs four components: gte-chnnel (I gc ), gte-drin (I gd ), gte-source (I gs ) nd gte-se (I g ) (Fig. 6). The totl gte current is: Fig. 6. DD I = I + I + I + I. (9) g gd g gs gc + DD o=0 Igd I g I gc I gs I sg Ig I cg Idg + DD o = DD Gte lekge currents of () nmos nd () pmos trnsistor Gte currents depend on supply voltge dd nd on the employed technology (Tle I) [11]. Thus, for exmple, when incresing the supply voltge level from dd =0. to dd =1., the gte current increses from I g 1. na to I g 1.7 µa. The increse rtio is pproximtely 1.4 10 3 times. When reducing the trnsistor dimensions, gte current increses s well. For nmos trnsistor, ccording to Tle I, tht increse for 45 nm in regrd to 65 nm CMOS technology, depending on dd, is pproximtely 7 (t dd =1. ) to 14 (t dd =0. ) times. TABLE I. NMOS TRANSISTOR GATE CURRENT AS A FUNCTION OF SUPPLY OLTAGE FOR TWO DIFFERENT TECHNOLOGIES dd [] 45 nm tech. 65 nm tech. 0. 1.1996 na 85.506 pa 0.4 14.58 na 1.376 pa 0.6 66.954 na 6.5488 na 0.8 5.97 na 5.44 na 1.0 647.38 na 8.378 na 1. 1.6811 µa 43.1 na The nmos trnsistor lekge current is greter thn in pmos, ecuse the proility of holes tunneling is greter thn the proility of electrons tunneling through the gte oxide. Tht increse, depending on supply voltge is 40 times [11]. The su-threshold lekge current is cutoff trnsistor ( gs =0) drin to source current (Figure 7) nd it is given s: Dokic: A Review on Energy Efficient CMOS Digitl Logic I g

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 556 I ddsu o dd t nϕt η = I e (10) where η is the DIBL (Drin Induced Brrier Lowering) fctor [9]. This current vlues depend on the supply voltge, the dimensions of elements (technology) nd the temperture. In Tle II, comprtive vlues of gte current nd su-threshold drin current s function of supply voltge dd nd temperture re given, for 45 nm technology. It is evident tht the dependency of I g on dd nd in function of temperture dependency of I dsu is more expressed. On the other hnd, t temperture of 5 C it holds dd 0.6, I g <I dsu, while for dd >0.6, I g >I dsu. Thus, for exmple, for dd =1. holds tht I g 13I dsu. Fig. 7. TABLE II. + DD DD I dnsu DD + DD I dpsu Su-threshold currents of () nmos nd () pmos trnsistors in CMOS inverter GATE AND SUB-THRESHOLD DRAIN CURRENT OF NMOS TRANSISTOR AS A FUNCTION OF DD AND TEMPERATURE dd [] Gte current I g [na] Su-threshold current I dsu [µa] 5 C 110 C 5 C 110 C 0. 1.1996 1.689 40.999 0.88086 0.4 14.58 15.776 56.437 1.1586 0.6 66.954 75.437 7.47 1.4401 0.8 5.97 56.33 89.397 1.7334 1.0 647.38 736.31 107.4.048 1. 1681.1 1914.3 17.1.3785 Inverse sturtion current Idss of the p-n junction of turned off trnsistor depends on the p-n junction surfce nd temperture. For 0.5 µm technology, it is etween 10 nd 100 pa/µm t 5 C temperture per re unit. In nnometer technologies, this current is less thn I g nd I dsu, nd cn e ignored. Dynmic consumption consists of two components: switching consumption nd trnsition (short-circuits) consumption. Switching consumption is the result of chrging nd dischrging of lod cpcitor nd in oth regimes is defined s: P = P = C f, (11) d ddsu L dd where C L is the effective output prsite cpcitnce, nd f is the switching stte frequency of the CMOS logic circuit. 0 Trnsition consumption occurs due to conduction of oth trnsistors or trnsistor networks (nmos or pmos) during switching sttes (trnsition re) (Figure 3). In strong inversion regime, trnsition consumption is defined with [1] nd is: where I 1 P = I ( )( t + t ) f, (1) dp ddm DD t r f 3 ddm C W ox n = µ n Ln 1+ ( DD t ) µ W / L n n n µ W / L p p p (13) is the mximl voltge supply current in trnsition re, nd t r nd t f re the rise time nd fll time input signls. In su-threshold regime, dissiption power of trnsition is defined with [8] : ( ) P = nϕi t + t f, (14) dpsu t ddmsu r f where I ddmsu is defined with (4), nd f is n input signl frequency. Usully, dynmic dissiption power is clculted (estimted) in regrd to clock frequency. Nmely, most numer of logic circuits does not chnge their stte during every cycle of clock signl. Therefore, expressions for dynmic consumption hve to e multiplied with ctivity fctor α 1, regrding to clock frequency, so tht: IddM P = αf C + αf ( )( t + t ), dd c L dd c dd t r f 3 ( ) P = αf C + αf nϕi t + t. ddsu c L ddsu c t ddmsu r f (15) Product αf c, where f c is the clock frequency, is the ctivity of the circuit indicting the numer of stte chnges. Mostly, ctivity fctor is α<0.5. It is determined empiriclly tht sttic CMOS digitl circuits hve α 0.1 [13]. I. LOW POWER DESIGN TECHNIQUES Optiml project implies compromise etween operting speed nd low power, which ll design levels tke into ccount []. In this section, we will spek out the optiml project considering the choice of trnsistor threshold voltge t nd system power supply voltge dd. In the previous prgrph, it ws shown tht oth sttic nd dynmic consumptions re decresed with the reduce of dd. Dynmic switching consumption in oth regimes is proportionl to dd. Trnsition consumption in the strong inversion regime is P dp ~( dd - t ) 3, nd in su-threshold regime / ~ dd P e t dpsu. Sttic currents, depends on supply voltge s well (Tles I nd II), so tht P S ~ dd n, where n is usully in the rnge of 1<n<4. www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 557 Logic dely lso depends on dd nd t. Nmely, in the strong inversion regime, cpcitor chrging/dischrging current is I d ~( dd - t ) in the sturted re, nd I d ~ ( dd - t ) o in the non-sturted re (Figure 8). In the su-threshold regime tht dd ( t t dd ) current is I ~ e = e (Figure 8). Thus, reduction dsu of dd increses the logic dely in oth regimes. In order to mintin the logic dely t lower dd, threshold voltge t should e reduced. Over long period of time, CMOS digitl circuit's performnce incresing scenrio ws conducted in the process of reduction of element's dimensions, y lowering dd nd t. However, reduction of t elow 00 m leds to exponentil increse of su-threshold current s shown in (4). This my cuse the sttic consumption to e higher thn the dynmic. Consequently, it cn e sid tht the reduction of threshold voltge is limited to pproximtely tmin =00 m. the sme time [15]. The stte of the pmos trnsistors is then controlled with the SL signl, nd of the nmos with the SL signl. The rtio etween the consumption nd the speed of dt processing is optimized using severl power supplies in the sme design. Logic circuits over criticl dely pths re supplied with higher ddh, nd circuits whose dely is not criticl with lower voltge ddl (Figure 10). The numer of voltge levels cn e greter, ut it turns out tht the lrgest effect is chieved using two power supplies [16]. It should e noted tht the trnsition from logic with ddl to logic with ddh power supply is chieved using logic voltge level converters. This s well limits the numer of power supply levels. Fig. 9. MTCMOS lock digrm with gted voltge supply Fig. 8. Dischrge currents of cpcitor C L in the strong nd wek inversion regime. MULTI DD /T OPTIMIZATION TECHNIQUES A compromise etween low power nd sufficient speed cn e chieved using trnsistors with different threshold voltges. This technique is known s the multi-threshold technique or MTCMOS [14, 15]. Criticl signl pth is designed using logic with lower threshold voltges. Trnsistors with higher t re used where dely is not criticl. The second pproch with the MTCMOS technique is sed on the so-clled gted voltge supply (Figure 9). In sttic sttes, reltively in time of logic inctivity (Stndy Mode), voltge supply is turned off using trnsistors with high threshold voltge. Thus, the smll suthreshold current is secured, long with low sttic dissiption. Logic lock trnsistors re designed with low t so tht the needed speed is preserved. Using control wke up signl SL (Sleep), over pmos trnsistor with high t, the connection etween true dd nd virtul power supply dd is controlled. While M p is turned off, cpcitor C B mintins the virtul power supply of the logic lock. Reduction of the lekge currents of inctive components cn e chieved using nmos trnsistors etween the logic lock nd the ground, or with pmos nd nmos trnsistors t Fig. 10. Two registers connected with different dely pths Often in the sme digitl system, techniques with severl power supplies nd severl threshold voltges hve een used multi dd / t techniques [16, 17]. Optiml operting point ( ddopt, topt ) is determined on dd - t plne with constnt power consumption lines (equi-power) nd speed lines (equi-speed) (Fig. 11). These lines depend on technologicl process nd project rchitecture. The choice of the optiml ( ddopt, topt ) pir depends on technologicl process constrints. Let sy tht those constrints re: dd =3.3±10% nd t =0.55 ±0.1. The re of llowed vlues for these limittions is shown in Figure 11, with lrger rectngle. For ll vlues of dd nd t inside this rectngle, system fulfills ll given specifictions. In A corner, system will hve the highest dely, nd in B corner the highest energy consumption. Constnt speed nd constnt consumption lines re normlized t points A nd B y normliztion fctors k s nd k p, respectively. Bsed on tht, we determine the influence www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 558 of position chnges nd the rectngle size in dd - t plne, onto consumption nd system speed. For exmple, smller rectngle on Figure 11 is defined with constrints dd =.1 ±5% nd t =0.18 ±0.05, nd consumption is 60% (k p =0.4) lower for the sme operting speed (k s =1). t () I. CMOS LOW POWER TOPOLOGIES Stndrd CMOS comintionl logic demnds CMOS trnsistor pir per every input. However, vrious lterntive topologies with the lower numer of trnsistors hve een developed. Besides, the increse of scle of function integrtion in LSI integrted circuit, hs led to reduce of consumption or increse of speed t the sme consumption level. Among the first lterntive CMOS digitl logics is the trnsmission-gte logic. Unlike stndrd logic where the sic cell is the inverter, in trnsmission-gte logic, the sic cell is the trnsmission gte. While in stndrd logic circuits, output signls re seprted from the inputs, here the input signl is trnsferred to the output vi the trnsfer gte. Figure 1 shows /1 multiplexer (/1 MUX) in trnsmission-gte logic. Since the complementry signls re needed for trnsmission gte control, inverters re integrl prt of the network s well. The /1 MUX in Figure 1 consists of only three CMOS trnsistor pirs, while stndrd logic needs seven pirs. Fig. 11. dd- t plin with constnt power consumption nd dely lines From ll possile dd - t comintions tht meet given time constrints, only one comintion ( ddopt, topt ) gurntees miniml consumption. Shuster et. l. [18] proposed n eqution, sed on the trnsistor lph model, for the clcultion of totl system consumption with the optiml ( ddopt, topt ) pir. Nevertheless, it should e stted tht the continul chnge of ddopt nd topt is unprcticl. Designers re mostly llowed to choose etween severl discrete ( ddopt, topt ) vlues. By pplying the multi dd technique, dynmic consumption cn e reduced from 10%, up to 50%, wheres y pplying the multi t technique, sttic consumption cn e reduced for 50%, even up to 80% [3]. In [16], the optiml rtio etween dd nd t is given (Tle III). TABLE III. OPTIMAL RATIO OF DD AND T CONSIDERING CONSUMPTION ( dd1, dd): ( dd1, dd, dd3): ddi, i=1,,3,4, t=const dd t = 0.5+ 0.5 dd1 dd1 = = 0.6+ 0.4 dd dd3 t dd1 dd dd1 Fig. 1. MUX /1 in trnsmission-gte logic Trnsmission gte logic cn e dditionlly simplified y pplying signls nd to the inverter power line s in the exmple of XOR nd XNOR circuit synthesis shown in Figure 13. The inverters with the (M n, M p ) trnsistor pir re powered y nd signls. In the synthesis of logicl functions in trnsmission-gte logic, it must e tken into ccount tht etween the output nd t lest one input, contour of smll resistnce exists. Otherwise, output would e in the stte of high impednce with the undefined logic level. ( dd1, dd, dd3, dd4): = = = 0.7+ 0.3 dd dd3 dd4 t dd1 dd dd3 dd1 ti, i=1,,3,4, dd=const ( t1, t): t=0.1 dd+ t1 ( t1, t, t3): ( t1, t, t3, t4): t=0.06 dd+ t1 t3=0.07 dd+ t t=0.04 dd+ t1 t3=0.05 dd+ t t4=0.06 dd+ t3 Fig. 13. () XOR nd () XNOR circuits As trnsmission gte, insted of CMOS pir, only nmos trnsistors cn e used (Fig. 14). The numer of trnsistors is hlved nd the sttic consumption nd the prsite www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 559 cpcitnce re reduced s well, which significntly increses the scle of function integrtion in LSI circuit. d0 d 1 DD dd ) d d 3 Fig. 14. MUX 4/1 in pss-trnsistor nmos logic with true nd complementry output The prolem with the nmos pss-trnsistor logic is tht the mximl voltge vrition on one nmos trnsistor is dd - tn nd lower, for threshold voltge tn compring to the CMOS trnsmission gte. Tht limits the numer of seril trnsistors. Therefore, nmos trnsistors with very low (NTL- on Threshold Logic) or zero threshold voltge (ZTT-Zero Threshold Logic) hve een used. The prolem of mentioned logics lies in the low noise immunity. Reduction of logic mplitude in nmos trnsmission-gte logic is especilly prolem when nmos network ends with n inverter. Tht prolem cn e solved using pmos trnsistor M p s shown in Figure 16. When z = 0, M p is on nd mintins the vlue of nmos network output voltge t dd. Low threshold trnsistors re used in the so-clled CPL (Complementry Pss-Trnsistor Logic). This logic consists of two nmos trnsistor networks with common control nd complementry trnsfer signls (Figure 15). PPL (Push-pull Pss-trnsistor Logic) [19] lso hve two trnsistor networks: one nmos nd the other pmos (Figure 16). The control signls re common, nd inputs re complementry. Output logic levels hve een restored to dd nd 0 y trnsistors M p nd M n, respectively. Tle I shows full dder comprtive chrcteristics using different logics, implemented in 0.8 µm technology t dd =3.3. Although pmos trnsistors re slower thn nmos, logic dely of PPL is pproximtely like CPL, ut the consumption is significntly lower. TABLE I. FULL ADDER COMPARATIE CHARACTERISTICS Prmeter CMOS CPL PPL Logic dely [ns] 1.57 0.84 0.83 Cons. [mw/100hz] 1.90 1.33 0.4 P t d (normlized) 1 0.38 0.1 z z Fig. 15. + + ) c) + + AND/NAND (), OR/NOR () i XOR/XNOR (c) logic circuits in CPL Fig. 16. PPL lock sheme II. ADIABATIC LOGIC The Term ditic descries thermodynmic processes in which the mount of het remins constnt (there is no exchnge of energy with the environment). Aditic logic in the idel sense, designte digitl circuits without loss (dissiption) of electricl energy. In prctice, it denotes the logic with miniml consumption of electricl energy during the switching of sttes. Aditic switching stte shifting is chrge/dischrge mechnism which returns ccumulted www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 560 energy to the source inside the lod cpcitor using the dynmic power supply. Dynmic power supply or clocked power hs very importnt role in ditic logic, ecuse eside power supply, it provides energy recovery. Nowdys, there re mny techniques of ditic logic [0-5]. Energy recovery process will e explined on the exmple of ECRL (Efficient Chrge Recovery Logic) inverter (Figure 17). Power supply PC is with trpezoidl pulses. 0 dd PC Accumultion ( chrging C L ) M p1 M p Energy recovery (dischrging C L ) Q Q s C L C L M n1 M n s s s { fn } network { fn } network Fig. 17. ECRL inverter scheme ) In the initil stte holds =1, nd the M n1 is conducting (Q=0). While PC rises from 0 to dd, over conductive trnsistor M p the output Q follows the vrition of PC. When PC reches the dd vlue, then it holds Q =1, nd Q =0 nd those conditions re vlid logic sttes t inputs of next stge. During the fll of PC from dd to zero, the right cpcitor C L dischrges over the conductive M p nd PC, nd therefore recovers ccumulted energy to the PC supply. More complex ECRL circuits hve two complementry nmos trnsistor networks with complementry excittions (Figure 18), insted of M n1 nd M n trnsistors. Complementry networks re otined y complementing input signls nd switching of logic opertors s function of f n nmos network. For exmple, f n /1 multiplexer function is f = ( s+ s) nd the function of complementry network n is f = ( s+ )( s + ) (Figure 18). n Other ditic topologies should e mentioned s well: PAL (Pss-trnsistor Aditic Logic) [1], CPAL (Complementry PAL), PFAL (Positive Feedck Aditic Logic) [0] etc. Reduced energy consumption compring to stndrd CMOS logic is round 50 to 90%. Fig. 18. () Block scheme of complex ECRL circuit () with MUX/1 network III. CONCLUSION f nd n To enle the design of energy-efficient digitl systems, designers must tke into ccount the electricl energy consumption through ll design phses, from functionl description to trnsistor level. The iggest energy sving (10 to 0 times) with the lest time needed for consumption nlysis is cquired on the system design level. In the su-threshold regime, consumption is severl orders of mgnitude lower, ut operting speed is lowered y nerly the sme mount in comprison to the strong inversion regime. Rescling of trnsistor dimensions increses gte current I g which is very dependent on power supply. Multi t / dd design techniques provide the reduction of consumption to scle of out ten percent t the sme operting speed. Digitl systems with two power supplies nd/or two threshold voltges re optiml s well. Using two threshold voltges, sttic consumption cn e reduced up to 80%. Alterntive topologies provide lrger scle of function integrtion per single LSI circuit, lower consumption level nd higher-speed rte. The trnsfer logic hs the widest ppliction in LSI digitl circuit design wheres ditic logic ensures the gretest energy sving (up to 90%). f n REFERENCES [1] R. Srpeshkr, Universl principles for ultr low power nd energy efficient design, IEEE Trnsctions on Circuits nd Systems II: Express Briefs, ol. 59, No.4, pp. 193-198, 01 [] J. Rey, Low power design essentils, Springer-erlg, New York, 009 www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic

ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 561 [3] B. Jovnovic, Anlytic model for dynmic consumption evlution of rithmetic circuits implemented on FPGA, PhD thesis, Elektronski fkultet Niš, 013 [4] S. R. Nssif, Witing for the Post-CMOS Godot, Int. ACM Gret Lkes Symposium on LSI, Lusnne, Switzerlnd, 011 [5] K. Itoh, A Historicl Review of low-power, low-voltge digitl MOS circuits development, IEEE Solid-Stte Circuits Mgzine, ol. 5, No. 1, pp 7-39, 013 [6] T. Mkimoto, The Age of the Digitl Nomd: Impct of CMOS innovtion, IEEE Solid-Stte Circuits Mgzine, ol. 5, No. 1,pp 40-47, 013 [7] Y. Tsividis, C. McAndrew, Operting nd modeling o the MOS trnsistor, Oxford University Press, 011 [8] B. Dokic, A. Pjknovic, Suthreshold operted CMOS nlytic model, INDEL 01, IX Symposium on Industril Electronics, Bnj Luk, Bosni nd Herzegovin, 01 [9] A. Wng, B. H. Clhoun, A. P. Chndrksn, Su-threshold design for ultr low-power systems, Springer, 006 [10] L. Nzhndli, B. Zhi, J. Olson, A. Reeves, M. Minuth, R. Helfnd, S. Pnt, T. Austin, D. Bluw, Energy optimiztion of suthresholdvoltge sensor network processes, ISCA 05, Proc. of the 3nd Int. Symp. on Computer Architecture, Mdison, Wisconsin USA, 005 [11] A. Mishr, R. A. Mishr, Lekge current minimiztion in dynmic circuits using sleep switch, SCES 01, Students Conference on Engineering nd Systems, pp. 1-6, Allhd, Uttr Prdesh, Indi, 01 [1] B. L. Dokic, Integrted circuits digitl nd nlog, Gls Srpski, 1999 [13] P. M. Petkovic, Design of CMOS integrted circuits with mixed signls, Elektronski fkultet Niš, 009 [14] M. Amis, S. Areii, M. Elmsry, Design nd optimistion of multithreshold CMOS (MTCMOS) circuits, IEEE Trnsctions on Computer-Aided Design of Integrted Circuits nd Systems, ol., No 10, pp. 134 134, 003 [15] S. Shigemtsu, S. Mutoh, Y. Mtsuy, Y. Tne, J. Ymd, A 1- High-Speed MTCMOS Circuit Scheme for Power-Down Appliction Circuits, IEEE Journl of Solid-Stte Circuits, ol. 3 No. 6, pp. 861 869, 1997 [16] M. Hmd, Y. Ootguro, T. Kurod, Utilizing surplus supplies timing for power reduction, IEEE Conference on Custom Integrted Circuits, pp. 89-9, Sn Diego, USA, 001 [17] C. Piguet, C. Schuster, J. Ngel Sttic nd Dynmic Power Reduction y Architecture Selection, Integrted Circuit nd System Design. Power nd Timing Modeling, Optimiztion nd Simultion. Lecture Notes in Computer Science, ol. 4148, pp. 659-668, 006 [18] C. Schuster, J. L. Ngel, C. Piguet, P. A. Frine, Architecturl nd Technology Influence on the Optiml Totl Power Consumption, Proceedings of Design, Automtion nd Test in Europe (DATE '06), pp 13-19, Munich, 006 [19] W. H. Pik, H. J. Ki, S. W. Kim Low power logic design using pushpull pss-trnsistor logics, Interntionl Journl of Electronics, ol. 84, No. 5, pp. 467-478, 1998 [0] R. K. Ydv, A. K. Rn, S. Chuhn, D. Rnk, K. Ydv, Aditic technique for energy efficient logic circuits design, Interntionl Conference on Emerging Trends in Electricl nd Computer Technology (ICETECT 011), pp 776-780, Tmil Ndu, 011 [1]. G. Oklodzij, D. Mksimovic, L. Fengcheng, Pss-trnsistor ditic logic using single power-clock supply, IEEE Trnsctions on Circuits nd Systems II: Anlog nd Digitl Signl Processing, ol. 44, No. 10, pp. 84-846, 1997. [] A. K. Mury, G. Kumr, Energy efficient ditic logic for low power LSI pplictions, Interntionl Conference on Communiction Systems nd Network Technologies (CSNT 011), pp. 460-463, Ktr, Jmmu, 011 [3] J. Hu, Q. Chen, Modelling nd ner-threshold computing of powergting ditic logic circuits, Przegląd Elektrotechniczny (Electricl Review), ol. 88, No. 76, pp. 77-80, 01 [4] D. Mrkovic, C. C. Wng, L. P. Alrcon, L. Tsung-Te, J. M. Rey, Ultrlow-power design in wer-threshold region, Proceedings of the IEEE, ol. 98, No., pp. 37-5, 010 [5] A. Pjknovic, T. J. Kzmierski, B. L. Dokic: Aditic Digitl Circuits Bsed on Su-threshold Opertion of Pss-trnsistor nd Slowly Rmping Signls, Proceedings of Smll Systems Simultion Symposium, pp 48-53, Niš, 01 www.etsr.com Dokic: A Review on Energy Efficient CMOS Digitl Logic