Low Dropou Linear Volage Regulaor TLS820F1ELV50 TLS820F1ELV50 Linear Volage Regulaor Daa Shee Rev. 1.0, 2016-04-28 Auomoive Power
Table of Conens Table of Conens 1 Overview....................................................................... 3 2 Block Diagram................................................................... 5 3 Pin Configuraion................................................................ 6 3.1 Pin Assignmen TLS820F1ELV50.................................................... 6 3.2 Pin Definiions and Funcions TLS820F1ELV50.......................................... 6 4 General Produc Characerisics.................................................... 8 4.1 Absolue Maximum Raings......................................................... 8 4.2 Funcional Range................................................................. 9 4.3 Thermal Resisance.............................................................. 10 5..................................... 11 5.1 Volage Regulaion............................................................... 11 5.2 Typical Performance Characerisics Volage Regulaor.................................. 13 5.3 Curren Consumpion............................................................. 16 5.4 Typical Performance Characerisics Curren Consumpion................................ 17 5.5 Enable......................................................................... 18 5.6 Typical Performance Characerisics Enable........................................... 19 5.7 Rese......................................................................... 20 5.8 Typical Performance Characerisics Rese............................................ 24 5.9 Sandard Wachdog.............................................................. 25 5.10 Typical Performance Characerisics Sandard Wachdog................................ 30 6 Applicaion Informaion.......................................................... 31 6.1 Applicaion Diagram.............................................................. 31 6.2 Selecion of Exernal Componens................................................... 31 6.2.1 Inpu Pin...................................................................... 31 6.2.2 Oupu Pin.................................................................... 31 6.3 Thermal Consideraions........................................................... 32 6.4 Reverse Polariy Proecion........................................................ 33 6.5 Furher Applicaion Informaion...................................................... 33 7 Package Oulines............................................................... 34 8 Revision Hisory................................................................ 35 Daa Shee 2 Rev. 1.0, 2016-04-28
Low Dropou Linear Volage Regulaor TLS820F1ELV50 1 Overview Feaures Wide Inpu Volage Range from 3.0 V o 40 V Fixed Oupu Volage 5 V Oupu Volage Precision ±2 % Oupu Curren Capabiliy up o 200 ma Ulra Low Curren Consumpion yp. 40 µa Very Low Dropou Volage yp. 70 mv @100 ma Sable wih Ceramic Oupu Capacior of 1 µf Delayed Rese a Power-On wih 2 Programmable Delay Times 8.5 ms / 16.5 ms Adjusable Rese Threshold down o 2.50 V Wachdog wih flexible imings: 16 ms / 32 ms / 48 ms / 96 ms Enable, Undervolage Rese, Overemperaure Shudown Oupu Curren Limiaion Wide Temperaure Range Green Produc (RoHS complian) AEC Qualified Figure 1 PG-SSOP-14 Daa Shee 3 Rev. 1.0, 2016-04-28
Overview Funcional Descripion The TLS820F1ELV50 is a high performance very low dropou linear volage regulaor for 5 V supply in a PG- SSOP-14 package. Wih an inpu volage range of 3 V o 40 V and very low quiescen of only 40 µa, hese regulaors are perfecly suiable for auomoive or any oher supply sysems conneced o he baery permanenly. The TLS820F1ELV50 provides an oupu volage accuracy of 2 % and a maximum oupu curren up o 200 ma. The new loop concep combines fas regulaion and very good sabiliy while requiring only one small ceramic capacior of 1 µf a he oupu. A currens below 100 ma he device will have a very low ypical dropou volage of only 70 mv. The operaing range sars already a inpu volages of only 3 V (exended operaing range). This makes he TLS820F1ELV50 also suiable o supply auomoive sysems ha need o operae during cranking condiion. The device can be swiched on and off by he Enable feaure as described in Chaper 5.5. The oupu volage is supervised by he Rese feaure, including Undervolage Rese, delayed Rese a Power-On and an adjusable lower Rese Threshold, more deails can be found in Chaper 5.7. In addiion, a Wachdog circui wih flexible imings is inegraed o monior he microconroller s operaion. Inernal proecion feaures like oupu curren limiaion and overemperaure shudown are implemened o proec he device agains immediae damage due o failures like oupu shor circui o GND, over-curren and over-emperaures. Choosing Exernal Componens An inpu capacior C I is recommended o compensae line influences. The oupu capacior C Q is necessary for he sabiliy of he regulaing circui. TLS820F1ELV50 is designed o be also sable wih low ESR ceramic capaciors. Type Package Marking TLS820F1ELV50 PG-SSOP-14 820F1V50 Daa Shee 4 Rev. 1.0, 2016-04-28
Block Diagram 2 Block Diagram I Q EN Curren Limiaion Rese RO Enable RADJ WI Temperaure Shudown Bandgap Reference DT1 DT2 Wachdog WO GND Figure 2 Block Diagram TLS820F1ELV50 Daa Shee 5 Rev. 1.0, 2016-04-28
Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen TLS820F1ELV50 I n.c. EN n.c. GND n.c. WI 1 2 3 4 5 6 7 SSOP-14 14 13 12 11 10 9 8 Q n.c. WO RO DT2 DT1 RADJ Figure 3 Pin Configuraion 3.2 Pin Definiions and Funcions TLS820F1ELV50 Pin Symbol Funcion 1 I Inpu I is recommended o place a small ceramic capacior (e.g. 100 nf) o GND, close o he IC erminals, in order o compensae line influences. See also Chaper 6.2.1 2, 4, 6 n.c. no conneced Leave open or connec o GND 3 EN Enable (inegraed pull-down resisor) Enable he IC wih high level inpu signal; Disable he IC wih low level inpu signal; 5 GND Ground 7 WI Wachdog Inpu (inegraed pull-down resisor) Serve Wachdog wih rigger inpu signal (usable for microconroller monioring) 8 RADJ Rese Threshold Adjusmen Connec o GND o use sandard value; Connec an exernal volage divider o adjus rese hreshold 9 DT1 Delay Timing 1 (inegraed pull-down resisor) Connec o GND or Q o selec Rese iming acc. o Table 7 Connec o GND or Q o selec Wachdog iming acc. o Table 10 10 DT2 Delay Timing 2 (inegraed pull-down resisor) Connec o GND or Q o selec Wachdog iming acc. o Table 10 11 RO Rese Oupu (inegraed pull-up resisor o Q) Open collecor oupu; Leave open if he rese funcion is no needed 12 WO Wachdog Oupu (inegraed pull-up resisor o Q) Open collecor oupu; Leave open if he wachdog funcion is no needed Daa Shee 6 Rev. 1.0, 2016-04-28
Pin Configuraion Pin Symbol Funcion 13 n.c. no conneced Leave open or connec o GND 14 Q Oupu Volage Connec oupu capacior C Q o GND close o he IC s erminals, respecing he values specified for is capaciance and ESR in Funcional Range on Page 9 Pad Exposed Pad Connec o heasink area; Connec o GND Daa Shee 7 Rev. 1.0, 2016-04-28
General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Table 1 Absolue Maximum Raings 1) = -40 C o +150 C; all volages wih respec o ground (unless oherwise specified) -0.3 7 V P_4.1.3-0.3 7 V P_4.1.5 Parameer Symbol Values Uni Noe / Number Min. Typ. Max. Tes Condiion Inpu I, Enable EN Volage V I, V EN -0.3 45 V P_4.1.1 Oupu Q, Rese Oupu RO, Wachdog Oupu WO Volage V Q, V RO, V WO Wachdog Inpu WI, Delay Timing DT1 and DT2, Rese Threshold Adjusmen RADJ Volage V WI,V DT1, V DT2, V RADJ Temperaures Juncion Temperaure -40 150 C P_4.1.7 Sorage Temperaure T sg -55 150 C P_4.1.8 ESD Absorpion ESD Suscepibiliy o GND V ESD -2 2 kv 2) HBM P_4.1.9 ESD Suscepibiliy o GND V ESD -500 500 V 3) CDM P_4.1.10 ESD Suscepibiliy Pin 1, 7, 8, 14 (corner V ESD1,7,8,14-750 750 V 3) CDM P_4.1.11 pins) o GND 1) No subjec o producion es, specified by design. 2) ESD suscepibiliy, HBM according o ANSI/ESDA/JEDEC JS001 (1.5 kω, 100 pf) 3) ESD suscepibiliy, Charged Device Model CDM according JEDEC JESD22-C101 Noe: 1. Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. 2. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daa Shee 8 Rev. 1.0, 2016-04-28
General Produc Characerisics 4.2 Funcional Range Table 2 Funcional Range = -40 C o +150 C; all volages wih respec o ground (unless oherwise specified) Parameer Symbol Values Uni Noe / Number Min. Typ. Max. Tes Condiion Inpu Volage Range V I V Q,nom + V dr 40 V 1) P_4.2.1 Exended Inpu Volage Range V I,ex 3.0 40 V 2) P_4.2.3 Enable Volage Range V EN 0 40 V P_4.2.5 Oupu Capacior s Requiremens for Sabiliy C Q 1 µf 3)4) P_4.2.6 ESR ESR(C Q ) 100 Ω 3) P_4.2.7 Juncion Temperaure -40 150 C P_4.2.9 1) Oupu curren is limied inernaly and depends on he inpu volage, see Elecrical Characerisics for more deails. 2) When V I is beween V I,ex,min and V Q,nom + V dr, V Q = V I - V dr. When V I is below V I,ex,min, V Q can drop down o 0 V. 3) No subjec o producion es, specified by design. 4) The minimum oupu capaciance requiremen is applicable for a wors case capaciance olerance of 30% Noe: Wihin he funcional or operaing range, he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he Elecrical Characerisics able. Daa Shee 9 Rev. 1.0, 2016-04-28
General Produc Characerisics 4.3 Thermal Resisance Noe: This hermal daa was generaed in accordance wih JEDEC JESD51 sandards. For more informaion, go o www.jedec.org. Table 3 Thermal Resisance Parameer Symbol Values Uni Noe / Number Min. Typ. Max. Tes Condiion Package Version PG-SSOP-14 Juncion o Case R hjc 9 K/W 1) P_4.3.1 Juncion o Ambien R hja 43 K/W 1)2) 2s2p board P_4.3.2 Juncion o Ambien R hja 128 K/W 1)3) 1s0p board, P_4.3.3 fooprin only Juncion o Ambien R hja 58 K/W 1)3) 1s0p board, P_4.3.4 300 mm 2 heasink area on PCB Juncion o Ambien R hja 50 K/W 1)3) 1s0p board, 600 mm 2 heasink area on PCB P_4.3.5 1) No subjec o producion es, specified by design 2) Specified R hja value is according o Jedec JESD51-2,-5,-7 a naural convecion on FR4 2s2p board; The Produc (Chip+Package) was simulaed on a 76.2 x 114.3 x 1.5 mm³ board wih 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a hermal via array under he exposed pad conaced he firs inner copper layer. 3) Specified R hja value is according o JEDEC JESD 51-3 a naural convecion on FR4 1s0p board; The Produc (Chip+Package) was simulaed on a 76.2 114.3 1.5 mm 3 board wih 1 copper layer (1 x 70µm Cu). Daa Shee 10 Rev. 1.0, 2016-04-28
5 5.1 Volage Regulaion The oupu volage V Q is divided by a resisor nework. This fracional volage is compared o an inernal volage reference and he pass ransisor is driven accordingly. The conrol loop sabiliy depends on he oupu capacior C Q, he load curren, he chip emperaure and he inernal circui design. To ensure sable operaion, he oupu capacior s capaciance and is equivalen series resisor (ESR) requiremens given in Funcional Range on Page 9 have o be mainained. For deails, also see he ypical performance graph Oupu Capacior Series Resisor ESR(CQ) versus Oupu Curren IQ on Page 14. As he oupu capacior also has o buffer load seps, i should be sized according o he applicaion s needs. An inpu capacior C I is recommended o compensae line influences. In order o block influences like pulses and HF disorion a inpu side, an addiional reverse polariy proecion diode and a combinaion of several capaciors for filering should be used. Connec he capaciors close o he componen s erminals. In order o preven overshoos during sar-up, a smooh ramp up funcion is implemened. This ensures almos no oupu volage overshoos during sar-up, mosly independen from load and oupu capaciance. Whenever he load curren exceeds he specified limi, e.g. in case of a shor circui, he oupu curren is limied and he oupu volage decreases. The overemperaure shudown circui prevens he IC from immediae desrucion under faul condiions (e.g. oupu coninuously shor-circui) by swiching off he power sage. Afer he chip has cooled down, he regulaor resars. This leads o an oscillaory behavior of he oupu volage unil he faul is removed. However, juncion emperaures above 150 C are ouside he maximum raings and herefore significanly reduce he IC s lifeime. Supply I I I Q I Q Regulaed Oupu Volage EN Curren Limiaion Rese RO C I V I WI Enable Temperaure Shudown Bandgap Reference RADJ DT1 DT2 C ESR C Q V Q LOAD Wachdog WO GND Figure 4 Volage Regulaion V V I V dr V Q,nom VI,ex,min V Q Figure 5 Oupu Volage vs. Inpu Volage Daa Shee 11 Rev. 1.0, 2016-04-28
Table 4 Elecrical Characerisics Volage Regulaor 5 V version = -40 C o +150 C, V I = 13.5 V, all volages wih respec o ground (unless oherwise specified) Typical values are given a = 25 C Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. Oupu Volage Precision V Q 4.9 5.0 5.1 V 0.05 ma < I Q <200mA P_5.1.1 5.44 V < V I < 28V Oupu Volage Precision V Q 4.9 5.0 5.1 V 0.05 ma < I Q <100mA 5.27 V < V I <40V P_5.1.2 Oupu Volage Sar-up slew rae dv Q /d 3.0 7.5 18 V/ms V I >18V/ms C Q =1µF 0.5 V < V Q <4.5V P_5.1.7 Oupu Curren Limiaion I Q,max 201 350 550 ma 0 V < V Q <4.8V P_5.1.8 Load Regulaion seady-sae Line Regulaion seady-sae V Q,load -15-1.5 5 mv I Q = 0.05 ma o 200 ma V I = 6 V V Q,line -20 0 20 mv V I = 8 V o 32 V I Q =1mA Dropou Volage V dr = V I - V Q V dr 140 340 mv Dropou Volage V dr 70 170 mv V dr = V I - V Q Power Supply Ripple Rejecion PSRR 59 db 1) I Q = 200 ma P_5.1.10 P_5.1.12 P_5.1.14 1) I Q = 100 ma P_5.1.15 2) f ripple = 100 Hz V ripple = 0.5 Vpp P_5.1.18 Overemperaure Shudown,sd 151 200 C 2) increasing P_5.1.19 Threshold Overemperaure Shudown,sdh 15 K 2) decreasing P_5.1.20 Threshold Hyseresis 1) Measured when he oupu volage V Q has dropped 100 mv from he nominal value obained a V I = 13.5V 2) No subjec o producion es, specified by design Daa Shee 12 Rev. 1.0, 2016-04-28
5.2 Typical Performance Characerisics Volage Regulaor Typical Performance Characerisics Oupu Volage V Q versus Juncion Temperaure Dropou Volage V dr versus Juncion Temperaure 5.15 I Q = 100mA 300 250 I Q = 100 ma I Q = 200 ma V Q = 5 V 5.1 5.05 200 V Q [V] 5 V dr [mv] 150 4.95 100 4.9 4.85 50 4.8 0 50 100 150 [ C] 0 0 50 100 150 [ C] Load Regulaion V Q,load versus Oupu Curren Change I Q Line Regulaion V Q,line versus Inpu Volage V I 0 8 0.5 1 1.5 6 4 ΔV Q,load [mv] 2 2.5 3 ΔV Q,line [mv] 2 0 2 3.5 4 V I = 6 V = 40 C 4.5 = 25 C = 150 C 5 0 50 100 150 200 I Q [ma] 4 6 8 I Q = 1 ma = 40 C = 25 C = 150 C 10 15 20 25 30 V I [V] Daa Shee 13 Rev. 1.0, 2016-04-28
Oupu Volage V Q versus Inpu Volage V I Power Supply Ripple Rejecion PSRR versus ripple frequency f 6 = 40 C 80 = 25 o C 5 = 25 C = 150 C 70 I Q = 100 ma 60 4 50 V Q [V] 3 PSRR [db] 40 2 30 20 1 0 0 1 2 3 4 5 6 V I [V] Oupu Capacior Series Resisor ESR(C Q ) versus Oupu Curren I Q 10 I Q = 10 ma C Q = 1 μf V ripple = 0.5 V pp 0 10 2 10 1 10 0 10 1 10 2 10 3 f [khz] Maximum Oupu Curren I Q versus Inpu Volage V I 10 3 800 = 40 C 10 2 Unsable Region 700 600 = 25 C = 150 C V Q = 0 V ESR(C Q ) [Ω] 10 1 10 0 Sable Region I Q,max [ma] 500 400 300 10 1 C Q = 1 μf 200 100 = 25 o C 10 2 0.05 1 10 100 500 I Q [ma] 0 0 10 20 30 40 V I [V] Daa Shee 14 Rev. 1.0, 2016-04-28
Dropou Volage V dr versus Oupu Curren I Q 300 = 25 o C 250 200 V dr [mv] 150 100 50 0 0 50 100 150 200 I Q [ma] Daa Shee 15 Rev. 1.0, 2016-04-28
5.3 Curren Consumpion Table 5 Elecrical Characerisics Curren Consumpion = -40 C o +150 C, V I = 13.5 V (unless oherwise specified) Typical values are given a = 25 C Condiions of oher pins: DT1 = DT2 = WI = GND Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. Curren Consumpion I q,off 1.3 5 µa V EN =0V; <105 C P_5.3.1 I q = I I Curren Consumpion I q,off 8 µa V EN =0.4V; < 125 C P_5.3.3 I q = I I Curren Consumpion I q = I I - I Q I q 40 52 µa I Q =0.05mA =25 C Wachdog enabled P_5.3.4 Curren Consumpion I q 62 77 µa I Q =0.05mA I q = I I - I Q <125 C Wachdog enabled Curren Consumpion I q = I I - I Q I q 62 80 µa 1) I Q =200mA <125 C Wachdog enabled 1) No subjec o producion es, specified by design P_5.3.7 P_5.3.9 Daa Shee 16 Rev. 1.0, 2016-04-28
5.4 Typical Performance Characerisics Curren Consumpion Typical Performance Characerisics Curren Consumpion I q versus Oupu Curren I Q Curren Consumpion I q versus Inpu Volage V I 100 90 = 25 C 200 180 = 40 C = 25 C 80 70 160 140 = 150 C V EN = 5 V I Q = 50 ua 60 120 I q [ua] 50 I q [ua] 100 40 80 30 60 20 40 10 20 0 0 50 100 150 200 I Q [ma] 0 5 10 15 20 25 30 35 40 V I [V] Daa Shee 17 Rev. 1.0, 2016-04-28
5.5 Enable The TLS820F1ELV50 can be swiched on and off by he Enable feaure: Connec a HIGH level as specified below (e.g. he baery volage) o pin EN o enable he device; connec a LOW level as specified below (e.g. GND) o shu i down. The enable has a buil in hyseresis o avoid oggling beween ON/OFF sae, if signals wih slow slopes are applied o he EN inpu. Table 6 Elecrical Characerisics Enable = -40 C o +150 C, V I = 13.5 V, all volages wih respec o ground (unless oherwise specified) Typical values are given a = 25 C Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. High Level Inpu Volage V EN,H 2 V V Q seled P_5.5.1 Low Level Inpu Volage V EN,L 0.8 V V Q 0.1 V P_5.5.2 Enable Threshold Hyseresis V EN,Hy 100 mv P_5.5.3 High Level Inpu Curren I EN,H 3.5 µa V EN =3.3V P_5.5.4 High Level Inpu Curren I EN,H 22 µa V EN 18 V P_5.5.6 Enable inernal pull-down resisor R EN 0.95 1.5 2.6 MΩ P_5.5.7 Daa Shee 18 Rev. 1.0, 2016-04-28
5.6 Typical Performance Characerisics Enable Typical Performance Characerisics Inpu Curren I IN versus Inpu Volage V IN (condiion: V EN = 0 V) Enabled Inpu Curren I EN versus Enabled Inpu Volage V EN 30 50 25 = 40 C = 25 C = 150 C 45 40 = 40 C = 25 C = 150 C 20 V EN = 0V 35 30 I IN [ua] 15 I EN [ua] 25 20 10 15 5 10 5 0 0 10 20 30 40 V IN [V] 0 0 10 20 30 40 V EN [V] Oupu Volage V Q versus ime (EN swiched ON) 6 5 4 V Q, V EN [V] 3 2 1 I Q = 100 ma = 40 C = 25 C = 150 C V EN 0 0 500 1000 1500 2000 [us] Daa Shee 19 Rev. 1.0, 2016-04-28
5.7 Rese The TLS820F1ELV50 s oupu volage is supervised by he Rese feaure, including Undervolage Rese, delayed Rese a Power-On and an adjusable Rese Threshold. The Undervolage Rese funcion ses he pin RO o LOW, in case V Q is falling for any reason below he Rese Threshold V RT,low. When he regulaor is powered on, he pin RO is held a LOW for he duraion of he Power-On Rese Delay Time rd. Supply I Q VDD Conrol S R RO,in RO C Q opional Rese I RO Reference OR OR R Q R ADJ,1 Micro- Conroller Timer RADJ I RADJ opional GND DT1 R ADJ,2 GND Figure 6 Block Diagram Rese Circui Rese Delay Time The pin DT1 is used o se he desired Rese Delay Time rd. Connec his pin eiher o GND or Q o selec he iming according o Table 7. Table 7 Rese DelayTime Selecion DT1 conneced o GND Q rd 16.5 ms 8.5 ms Power-On Rese Delay Time The power-on rese delay ime is defined by he parameer rd and allows a microconroller and oscillaor o sar up. This delay ime is he ime period from exceeding he upper rese swiching hreshold V RT,high unil he rese is released by swiching he rese oupu RO from LOW o HIGH. Undervolage Rese Delay Time Unlike he power-on rese delay ime, he undervolage rese delay ime is defined by he parameer rd and considers an oupu undervolage even where he oupu volage V Q rigger he V RT,low hreshold. Rese Blanking Time The rese blanking ime rr,blank avoids ha shor undervolage spikes rigger an unwaned rese low signal. Daa Shee 20 Rev. 1.0, 2016-04-28
Rese Reacion Time In case he oupu volage of he regulaor drops below he oupu undervolage lower rese hreshold V RT,low, he rese oupu RO is se o low, afer he delay of he inernal rese reacion ime rr,in. The rese blanking ime rr,blank is par of he rese reacion ime rr,in. Rese Oupu RO The rese oupu RO is an open collecor oupu wih an inegraed pull-up resisor. In case a lower-ohmic RO signal is desired, an exernal pull-up resisor can be conneced o he oupu Q. Since he maximum RO sink curren is limied, he minimum value of he opional exernal resisor R RO,ex is given in Table Rese Oupu RO on Page 23. Rese Oupu RO Low for VQ 1V In case of an undervolage rese condiion rese oupu RO is held low for V Q 1 V, even if he inpu I is no supplied and he volage V I drops below 1 V. This is achieved by supplying he rese circui from he oupu capacior. Rese Adjus Funcion The undervolage rese swiching hreshold can be adjused according o he applicaion s needs by connecing an exernal volage divider (R ADJ1, R ADJ2 ) a pin RADJ. For selecing he defaul hreshold connec pin RADJ o GND. The rese adjusmen range for he TLS820F1ELV50 is given in Rese Threshold Adjusmen Range. When dimensioning he volage divider, ake ino consideraion ha here will be an addiional curren consanly flowing hrough he resisors. Wih a volage divider conneced, he rese swiching hreshold V RT,new is calculaed as follows (neglecing he Rese Adjus Pin Curren I RADJ ): V RT,lo,new = V RADJ,h (R ADJ,1 + R ADJ,2 )/R ADJ,2 (1) wih V RT,lo,new : Desired undervolage rese swiching hreshold. R ADJ,1, R ADJ,2 : Resisors of he exernal volage divider, see Figure 6. V RADJ,h : Rese adjus swiching hreshold given in Rese Adjusmen Swiching Threshold. Daa Shee 21 Rev. 1.0, 2016-04-28
V I V Q V RT,hi gh V RT,low V RH < rr,blank 1 V rd rr,in rd rr,in rd rr,in V RO rd V RO,low 1V Thermal Shudown Inpu Volage Dip Spike a oupu Undervolage Overload Figure 7 Typical Timing Diagram Rese Daa Shee 22 Rev. 1.0, 2016-04-28
Table 8 Elecrical Characerisics Rese = -40 C o +150 C, V I = 13.5 V, all volages wih respec o ground (unless oherwise specified) Typical values are given a = 25 C Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. Oupu Undervolage Rese 5V Version only Oupu Undervolage Rese Upper Swiching Threshold V RT,high 4.6 4.7 4.8 V V Q increasing P_5.7.1 Oupu Undervolage Rese Lower Swiching Threshold - Defaul Oupu Undervolage Rese Swiching Hyseresis V RT,low 4.5 4.6 4.7 V V Q decreasing RADJ = GND P_5.7.2 V RT,hy 60 100 mv RADJ conneced o GND P_5.7.3 Oupu Undervolage Rese V RH 200 400 mv RADJ = GND P_5.7.4 Headroom V Q - V RT Rese Threshold Adjusmen Rese Adjusmen Swiching Threshold V RADJ,h 1.15 1.20 1.25 V P_5.7.9 Rese Threshold Adjusmen Range V RT,range 2.5 4.4 V for V Q,nom =5V P_5.7.10 Rese Oupu RO Rese Oupu Low Volage V RO,low 0.2 0.4 V 1 V V Q V RT ; R RO 5.1 kω P_5.7.12 Rese Oupu R RO,in 13 20 36 kω inernally conneced o Q P_5.7.13 Inernal Pull-Up Resisor Rese Oupu Exernal R RO,ex 5.1 kω 1V V Q V RT ; P_5.7.14 Pull-up Resisor o V Q V RO 0.4 V Rese Delay Timing Rese Delay Time rd,slow 13.2 16.5 19.8 ms DT1 conneced o GND P_5.7.20 Rese Delay Time rd,fas 6.8 8.5 10.2 ms DT1 conneced o Q P_5.7.21 Rese blanking ime rr,blank 7 µs 1) for V Q,nom =5V P_5.7.46 Inernal Rese Reacion Time rr,in 10 33 µs for V Q,nom =5V P_5.7.36 Rese Delay Inpu DT1 Delay Inpu DT1 V DT1,H 2.0 V P_5.7.24 High Signal Valid Delay Inpu DT1 V DT1,L 0.80 V P_5.7.25 Low Signal Valid Delay Inpu DT1 dv DT1 /d 1 V/µs V DT1,L <V DT1 < V DT1,H P_5.7.34 Signal Slew Rae High Level Inpu Curren I DT1,H 3.5 µa V DT1 =3.3V P_5.7.27 Delay Inpu DT1 inernal pull-down resisor R DT1 0.9 1.5 2.6 MΩ P_5.7.28 1) No subjec o producion es, specified by design. Daa Shee 23 Rev. 1.0, 2016-04-28
5.8 Typical Performance Characerisics Rese Typical Performance Characerisics Undervolage Rese Threshold V RT versus Juncion Temperaure Power On Rese Delay Time rd versus Juncion Temperaure 5 4.9 4.8 4.7 25 20 fas slow I Q = 1 ma 4.6 V RT [V] 4.5 rd [ms] 15 4.4 4.3 4.2 I Q = 1 ma V Q = 5 V RADJ se o GND 10 4.1 V RT, high 4 V RT, low 0 50 100 150 [ C] 5 0 50 100 150 [ C] Inernal Rese Reacion Time rr,in versus Juncion Temperaure 20 18 16 14 12 rr,in [μs] 10 8 6 4 2 0 40 0 50 100 150 [ C] Daa Shee 24 Rev. 1.0, 2016-04-28
5.9 Sandard Wachdog The TLS820F1ELV50 feaures a load dependen wachdog funcion wih a prgrammable wachdog iming. The wachdog funcion moniors a microconroller, including ime base failures. In case of a missing falling edge wihin a cerain pulse repeiion ime, he wachdog oupu WO is se o low. The wachdog uses an inernal oscillaor as imebase. The effecive rigger window is derived from he wachdog imebase and can be adjused by using he pins DT1 and DT2. The wachdog oupu WO is separaed from he rese oupu RO. Hence, he wachdog oupu migh be used as an inerrup signal for he microconroller independen from he rese signal. I is possible o inerconnec pin WO and pin RO in order o esablish a wire-or funcion wih a dominan low signal. Supply I Q VDD R WO,in WO C Q opional Rese Conrol Reference I WO WD core Micro- Conroller WI Conrol I WI GND DT1 DT2 GND Figure 8 Block Diagram Wachdog Circui Wachdog Timing By changing he condiion on he DT pins, he new iming is valid from he beginning of nex period. From his ime on, he frequency of he WI signal mus be adaped (see also Typical Wachdog Timing Diagram, Wachdog and Rese Modes on Page 26). Figure 9 shows he sae diagram of he wachdog (WD) and he mode selecion. Afer power-on, he rese oupu signal a he RO pin (microconroller rese) is kep LOW for he rese delay ime rd. Wih he LOW o HIGH ransiion of he signal a WO he device sars he wachdog ignore ime WI.i. Nex, he WD sars he wachdog rigger ime (ime frame wihin a rigger a WI mus occur). From now on, he iming of he signal on WI from he microconroller mus fi o he WD-rigger ime WI,r, based on he seing of he DT pins. A Re-Trigger of he WD-rigger ime is done wih a HIGH-o-LOW ransien a he WIpin wihin he acive WI,r. Wachdog Oupu WO The wachdog oupu WO is an open collecor oupu wih an inegraed pull-up resisor. In case a lower-ohmic WO signal is desired, an exernal pull-up resisor can be conneced o he oupu Q. Since he maximum WO sink curren is limied, he minimum value of he opional exernal resisor R WO,ex is given in Table Wachdog Oupu WO on Page 28. A HIGH o LOW ransiion of he wachdog rigger signal on pin WI is aken as a rigger. A wachdog signal is generaed ( WO goes LOW), if here is no rigger pulse during he Wachdog rigger ime. Daa Shee 25 Rev. 1.0, 2016-04-28
VI VQ VRT,high VRT,low DT1 Capure DT1 Capure DT1 Capure DT1 Capure DT1 Capure DT1 Capure DT1 Capure DT1 Capure DT1 DT2 Seup rd (slow) Capure DT2 Capure DT2 Capure DT2 Capure DT2 Capure DT2 Capure DT2 Capure DT2 Trigger rd 16.5ms yp. Ignore Time WI,i 48ms *) WD Trigger (WD-rigger ime WI,r) 32ms NO WD Trigger 96ms *) WD Trigger 32ms *) WD Trigger 48ms *) 16ms *) 96ms *) WD Trigger WD Trigger V WI Don care WI during rd and ignore ime Don care WI during WO,low and ignore ime V WO rd Normal operaion WO,low Normal operaion VRO rd rr,in Power Fail *) wachdog rigger ime inerruped by correc WI signal serving he wachdog Figure 9 Typical Wachdog Timing Diagram, Wachdog and Rese Modes Wachdog Inpu WI The wachdog is riggered by a falling edge a he wachdog inpu pin WI. The ampliude and slope of his signal has o comply wih he specificaion (Table Wachdog Inpu WI on Page 27). For deails regarding es pulses, see Figure 10 Tes Pulses Wachdog Inpu WI on Page 26. V WI WI,ph V WI,high WI,pl V WI,low dv WI / d Figure 10 Tes Pulses Wachdog Inpu WI Daa Shee 26 Rev. 1.0, 2016-04-28
Table 9 Elecrical Characerisics Wachdog = -40 C o +150 C, V I = 13.5 V, all volages wih respec o ground (unless oherwise specified) Typical values are given a = 25 C Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. Wachdog Timing Wachdog Ignore Time WI,i 12.8 16 19.2 ms P_5.9.1 Wachdog Trigger Time WI,r,1 76.8 96 115.2 ms DT1 conneced o GND; DT2 conneced o GND P_5.9.2 Wachdog Trigger Time WI,r,2 38.4 48 57.6 ms DT1 conneced o Q; P_5.9.3 DT2 conneced o GND Wachdog Trigger Time WI,r,3 25.6 32 38.4 ms DT1 conneced o GND; P_5.9.4 DT2 conneced o Q Wachdog Trigger Time WI,r,4 12.8 16 19.2 ms DT1 conneced o Q; P_5.9.5 DT2 conneced o Q Wachdog Oupu Low Time WO,low 6.4 8 9.6 ms P_5.9.6 Wachdog Inpu WI Wachdog Inpu V WI,low 0.8 V 1) P_5.9.16 Low Signal Valid Wachdog Inpu V WI,high 2.0 V 1) P_5.9.17 High Signal Valid Wachdog Inpu WI,ph 1 µs 1) V WI V WI,high P_5.9.19 High Signal Pulse Lengh Wachdog Inpu WI,pl 1 µs 1) V WI V WI,low P_5.9.20 Low Signal Pulse Lengh Wachdog Inpu dv WI /d 1 V/µs 1) V WI,low <V WI < V WI,high P_5.9.21 Signal Slew Rae High Level Inpu Curren I WI,H 3.5 µa V WI =3.3V P_5.9.22 Wachdog Inpu inernal pull-down resisor R WI 0.9 1.5 2.6 MΩ P_5.9.23 Wachdog Disable Threshold WI Signal Value Wachdog Minimum Filer Time sae ransiion by WI Wachdog Maximum Filer Time sae ransiion by WI V WI,dis 1.15 1.40 V for V Q,nom =5V: V I > 5.44 V; signal mus be applied for > W,filer,max o deacivae and acivae he wachdog P_5.9.31 WI,filer,min 100 µs 2) see Page 28 P_5.9.25 WI,filer,max 500 µs 2) see Page 28 P_5.9.26 Wachdog Delay Inpu DT2 (DT1 is defined in chaper Rese Delay Inpu DT1) Delay Inpu DT2 V DT2,L 0.8 V P_5.9.27 Low Signal Valid Delay Inpu DT2 High Signal Valid V DT2,H 2.0 V P_5.9.28 Daa Shee 27 Rev. 1.0, 2016-04-28
Table 9 Wachdog seup and hold ime (DT1, DT2) seup,hold, DT 150 µs 2) Wihin he seup and hold ime phase, a DTx ransiion will no be recognized P_5.9.33 Wachdog Oupu WO Wachdog Oupu Low Volage V WO,low 0.2 0.4 V R WO >5.1kΩ P_5.9.34 Wachdog Oupu Inernal Pull-Up Resisor Elecrical Characerisics Wachdog (con d) = -40 C o +150 C, V I = 13.5 V, all volages wih respec o ground (unless oherwise specified) Typical values are given a = 25 C Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Typ. Max. Delay Inpu DT2 dv DT2 /d 1 V/µs V DTx,L <V DTx < V DTx,H P_5.9.38 Signal Slew Rae High Level Inpu Curren DT2 I DT2,H 3.5 µa V DTx =3.3V P_5.9.30 Delay Inpu DT2 inernal pull-down resisor R DT2 0.9 1.5 2.6 MΩ P_5.9.32 R WO,in 13 20 36 kω inernally conneced o pin Q P_5.9.35 Wachdog Oupu Exernal R WO,ex 5.1 kω V WO 0.4 V; P_5.9.36 Pull-up Resisor o V Q 1) For deails on applied es pulse, see Figure 10 2) No subjec o producion es, specified by design. Wachdog Trigger Time Two pins, DT1 and DT2, are used o se he desired Wachdog Trigger Time WI,r. Connec hese pins eiher o GND or o high level (e.g. Q) o selec he iming according o Table 10. Table 10 Wachdog Trigger Time Selecion DT1 conneced o DT2 conneced o WI,r,yp GND GND 96 ms Q GND 48 ms GND Q 32 ms Q Q 16 ms Wachdog deacivaion by exernal signal (pin WI ) Noe: Disabling he wachdog should only considered when he applicaion is no running in he normal operaing condiions as he safe operaion is no ensured any more. Example would be he flashing process of he microconroller. The Wachdog can be disabled by connecing a volage level beween he range of 1.15 V o 1.40 V o WI. By enering he Wachdog deacivaion, he WO signal behaves like i is described in. The ransiion from acive o an inacive sae will be performed afer a dead ime of WI,filer,max, when correc level o WI pin is applied. This proecs agains he uninended enering of wachdog deacivaion sae. Afer leaving he deacivaion volage range 1.15 V o 1.40 V, he Wachdog is again acive and sars wih an ignore window. This scenario is also valid for he ransiion from deacivaion o acivaion sae. Daa Shee 28 Rev. 1.0, 2016-04-28
V WI >WO,low V WI Scenario D <WO,low VWI,dis.high VWI,dis.high VWI,dis,low VWI,dis,low V WO Scenario A V WO WD disabled WD-rigger ime WI,r *) WD disabled ignore ime WI,i WD-rigger ime WI,r WD-rigger ime WI,r WO,low ignore ime WI,i WD-rigger ime WI,r V WO Scenario B WD disabled *) inerruped by enering in Wachdog deacivaion by WI pin Wachdog filer ime W,IQ,filer WD-rigger ime WI,r WO,low ignore ime WI,i WD-rigger ime WI,r V WO Scenario C WD-rigger ime WI,r WO,low *) WD disabled ignore ime WI,i WD-rigger ime WI,r Figure 11 Wachdog Oupu behavior for Wachdog deacivaion by WI pin Scenario A In scenario A he wachdog logic expecs a nex rigger a WI pin wihin he WD-rigger ime WI,r. This sae is inerruped by seing V WI o he disable condiion (V WI,dis,low V WI V WI,dis,high ). During his sae, he wachdog is disabled. The wachdog oupu signal WO will say high while he wachdog is disabled. Afer leaving he disable condiion (V WI V WI,dis,high or V WI V WI,dis,low ), an ignore window WI,i follows. Afer his, he wachdog rigger ime WI,r sars based on he seing of he DT pins. This behavior is defined for cases wih a low curren load ime greaer han WO,low. Scenario B In scenario B he wachdog is no served wihin WD-rigger ime WI,r wih an rigger even a WI pin. As a resul he WO is se o low. This sae is inerruped by seing V WI o he disable condiion (V WI,dis,low V WI V WI,dis,high ). During his sae, he wachdog is disabled. The wachdog oupu signal WO is kep in low sae for WO,low and hen he WO is se o high. Afer leaving he disable condiion (V WI V WI,dis,high or V WI V WI,dis,low ), an ignore window WI,i follows. Afer his, he wachdog rigger ime WI,r sars based on he seing of he DT pins. This behavior is defined for cases wih a low curren load ime greaer han WO,low. Scenario C In scenario C he wachdog is no served wihin WD-rigger ime WI,r wih an rigger even a WI pin. As a resul he WO is se o low. Afer his an ignore window follows. This sae is inerruped by seing V WI o he disable condiion (V WI,dis,low V WI V WI,dis,high ). During his sae, he wachdog is disabled. The wachdog oupu signal WO will say high while he wachdog is disabled. Afer leaving he disable condiion (V WI V WI,dis,high or V WI V WI,dis,low ), an ignore window WI,i follows. Afer his, he wachdog rigger ime WI,r sars based on he seing of he DT pins. This behavior is defined for cases wih a low curren load ime greaer han WO,low. Scenario D In scenario D he wachdog is no served wihin WD-rigger ime WI,r wih a rigger even a WI pin. As a resul he WO is se o low. This sae is inerruped by seing V WI o he disable condiion (V WI,dis,low V WI V WI,dis,high ). During his sae, he wachdog is disabled. The wachdog oupu signal WO is kep in low sae for he ime of low curren load sae. Afer leaving he disable condiion (V WI V WI,dis,high or V WI V WI,dis,low ), an ignore window WI,i follows. Afer his, he wachdog rigger ime WI,r sars based on he seing of he DT pins. This behavior is defined for cases wih a low curren load ime less han WO,low. Daa Shee 29 Rev. 1.0, 2016-04-28
5.10 Typical Performance Characerisics Sandard Wachdog Typical Performance Characerisics Wachdog Trigger Time WI,r versus Juncion Temperaure Wachdog Oupu Low Time WO,low versus Juncion Temperaure 120 100 x = 1 x = 2 x = 3 x = 4 I Q = 10 ma 15 I Q = 10 ma 80 10 WI,r,x [ms] 60 WO,low [ms] 40 5 20 0 0 50 100 150 [ C] 0 0 50 100 150 [ C] Wachdog Disable V WI,dis Threshold versus Juncion Temperaure 3 2.5 2 V WI,dis low/high [V] 1.5 1 0.5 0 I Q = 10 ma low high 0 50 100 150 [ C] Daa Shee 30 Rev. 1.0, 2016-04-28
Applicaion Informaion 6 Applicaion Informaion 6.1 Applicaion Diagram Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. Supply DI1 DI2 CI2 CI1 I EN Curren Limiaion Rese Q RO Regulaed Oupu Volage CQ Load e. g. Micro Conroller XC22xx <45V 47µF 100nF Enable RADJ R1 1µF WI Temperaure Shudown Bandgap Reference DT1 DT2 R2 Wachdog WO GND GND e.g. Igniion Figure 12 Applicaion Diagram Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion. 6.2 Selecion of Exernal Componens 6.2.1 Inpu Pin The ypical inpu circuiry for a linear volage regulaor is shown in he applicaion diagram above. A ceramic capacior a he inpu, in he range of 100 nf o 470 nf, is recommended o filer ou he high frequency disurbances imposed by he line e.g. ISO pulses 3a/b. This capacior mus be placed very close o he inpu pin of he linear volage regulaor on he PCB. An aluminum elecrolyic capacior in he range of 10 µf o 470 µf is recommended as an inpu buffer o smooh ou high energy pulses, such as ISO pulse 2a. This capacior should be placed close o he inpu pin of he linear volage regulaor on he PCB. An overvolage suppressor diode can be used o furher suppress any high volage beyond he maximum raing of he linear volage regulaor and proec he device agains any damage due o over-volage. The exernal componens a he inpu are no mandaory for he operaion of he volage regulaor, bu hey are recommended in case of possible exernal disurbances. 6.2.2 Oupu Pin An oupu capacior is mandaory for he sabiliy of linear volage regulaors. The requiremen o he oupu capacior is given in Funcional Range on Page 9. The graph Oupu Capacior Series Resisor ESR(CQ) versus Oupu Curren IQ on Page 14 shows he sable operaion range of he device. Daa Shee 31 Rev. 1.0, 2016-04-28
Applicaion Informaion TLS820F1ELV50 is designed o be also sable wih low ESR capaciors. According o he auomoive requiremens, ceramic capaciors wih X5R or X7R dielecrics are recommended. The oupu capacior should be placed as close as possible o he regulaor s oupu and GND pins and on he same side of he PCB as he regulaor iself. In case of rapid ransiens of inpu volage or load curren, he capaciance should be dimensioned in accordance and verified in he real applicaion ha he oupu sabiliy requiremens are fulfilled. 6.3 Thermal Consideraions Knowing he inpu volage, he oupu volage and he load profile of he applicaion, he oal power dissipaion can be calculaed: P D = (V I - V Q ) I Q + V I I q (2) wih P D : coninuous power dissipaion V I : inpu volage V Q : oupu volage I Q : oupu curren I q : quiescen curren The maximum accepable hermal resisance R hja can hen be calculaed: R hja,max = (,max - T a )/P D (3) wih,max : maximum allowed juncion emperaure T a : ambien emperaure Based on he above calculaion he proper PCB ype and he necessary hea sink area can be deermined wih reference o he specificaion in Thermal Resisance on Page 10. Example Applicaion condiions: V I = 13.5 V V Q = 5 V I Q = 150 ma T a = 85 C Calculaion of R hja,max : P D =(V I V Q ) I Q + V I I q (V I I q can be negleced because of very low I q ) =(13.5V 5V) 150mA =1.275W R hja,max =(,max T a )/P D = (150 C 85 C) / 1.275 W = 50.98 K/W Daa Shee 32 Rev. 1.0, 2016-04-28
Applicaion Informaion As a resul, he PCB design mus ensure a hermal resisance R hja lower han 50.98 K/W. According o Thermal Resisance on Page 10, a leas 600 mm 2 heasink area is needed on he FR4 1s0p PCB, or he FR4 2s2p board can be used o ensure a proper cooling for he TLS820F1ELV50 in PG-SSOP-14 package. 6.4 Reverse Polariy Proecion TLS820F1ELV50 is no self proeced agains reverse polariy fauls and mus be proeced by exernal componens agains negaive supply volage. An exernal reverse polariy diode is needed. The absolue maximum raings of he device as specified in Absolue Maximum Raings on Page 8 mus be kep. 6.5 Furher Applicaion Informaion For furher informaion you may conac hp://www.infineon.com/ Daa Shee 33 Rev. 1.0, 2016-04-28
Package Oulines 7 Package Oulines 2) 0.25 ±0.05 Index Marking 0.65 14 1 7 8 0.05 ±0.05 STAND OFF (1.45) 1.7 MAX. C 6 x 0.65 = 3.9 A 0.15 M C A-B D B 0.1 H A-B 2x 4.9 ±0.1 1) 0.08 C SEATING PLANE 14x Exposed Diepad 3.9 ±0.1 1) 0.35 x 45 Boom View 3 ±0.2 1 7 14 8 1) Does no include plasic or meal prorusion of 0.15 max. per side 2) Lead widh can be 0.61 max. in dambar area D H 0.19 +0.06 0.64 ±0.25 6 ±0.2 0.2 C 14x 2.65 ±0.2 0.1 H D 2x PG-SSOP-14 8 MAX. Figure 13 PG-SSOP-14 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp://www.infineon.com/packages. Dimensions in mm Daa Shee 34 Rev. 1.0, 2016-04-28
Revision Hisory 8 Revision Hisory Revision Dae Changes 1.0 2016-04-28 Daa Shee - Iniial version Daa Shee 35 Rev. 1.0, 2016-04-28
Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, DI-POL, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EconoPACK, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, LITIX, MIPAQ, ModSTACK, my-d, NovalihIC, OpiMOS, ORIGA, POWERCODE, PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SaRIC, SIEGET, SINDRION, SIPMOS, SmarLEWIS, SPOC, SOLID FLASH, TEMPFET, hinq!, TRENCHSTOP, TriCore. Oher Trademarks Advance Design Sysem (ADS) of Agilen Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limied, UK. AUTOSAR is licensed by AUTOSAR developmen parnership. Blueooh of Blueooh SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirsGPS of Trimble Navigaion Ld. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsof Corporaion. FlexRay is licensed by FlexRay Consorium. HYPERTERMINAL of Hilgraeve Incorporaed. IEC of Commission Elecroechnique Inernaionale. IrDA of Infrared Daa Associaion Corporaion. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MahWorks, Inc. MAXIM of Maxim Inegraed Producs, Inc. MICROTEC, NUCLEUS of Menor Graphics Corporaion. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muraa of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Sysems Inc. RED HAT Red Ha, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Saellie Radio Inc. SOLARIS of Sun Microsysems, Inc. SPANSION of Spansion LLC Ld. Symbian of Symbian Sofware Limied. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tekronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limied. VERILOG, PALLADIUM of Cadence Design Sysems, Inc. VLYNQ of Texas Insrumens Incorporaed. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zeex Limied. Las Trademarks Updae 2011-11-11 www.infineon.com Ediion 2016-04-28 Published by Infineon Technologies AG 81726 Munich, Germany 2016 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? Email: erraum@infineon.com Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of noninfringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.