Dual SPDT CMOS nalog Switch HI-5051/883 This CMOS analog switch offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 70m. ON resistance is low and stays reasonably constant over the full range of operating signal voltage and current. R ON remains exceptionally constant for input voltages between +5V and -5V and currents up to 50m. Switch impedance also changes very little over temperature, particularly between 0 C and +75 C. R ON is nominally 25Ω. The HI-5051/883 provides break-before-make switching and is TTL and CMOS compatible for maximum application versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input and output leakage currents (0.8n at +25 C). The HI-5051/883 switch also features very low power operation (1.5mW at +25 C). The HI-5051/883 is available in a 20 Ld CLCC package and operates over the -55 C to +125 C temperature range. Features This Circuit is Processed in ccordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Wide nalog Signal Range........................ ±15V Low ON Resistance............... 25Ω (Typ), 50Ω (Max) High Current Capability..................... 70m (Max) Break-Before-Make Switching - Turn-On Time.................370ns (Typ), 800ns (Max) - Turn-Off Time............... 280ns (Typ), 400ns (Max) No Latch-Up Input MOS Gates are Protected from Electrostatic Discharge DTL, TTL, CMOS, PMOS Compatible pplications High Frequency Switching Sample and Hold Digital Filters Operational mplifier Gain Switching Pin Configuration D 3 S3 NC S 4 D 4 4 5 6 7 8 HI-5051/883 20 LD CLCC TOP VIEW LOGIC 0 PUT NC D 1 NC S 1 1 3 2 1 20 19 18 17 16 15 14 V R NC V L V+ Functional Diagram S 1 S 3 1 2 S 2 S 4 16 4 15 10 LOGIC 1 PUT 9 5 V L V R 12 V+ 11 13 14 1 3 8 6 D 1 D 3 D 2 D 4 NOTE: 9 10 11 12 13 NC D 2 NC S 2 2 Unused pins may be internally connected. Ground all unused pins. TYPICL SWITCH S Ordering Information N P PRT NUMBER PRT MRKG TEMP. RNGE ( C) PCKGE PKG. DWG. # HI4-5051/883 HI4-5051 883-55 to +125 20 Ld CLCC J20. NOTE: Source and Drain are arbitrarily depicted as nalog Input and Output, respectively. They may be interchanged without affecting performance. D FN8289.0 1 CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-TERSIL or 1-888-468-3774 Copyright Intersil mericas Inc. 1989, 2012. ll Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. ll other trademarks mentioned are the property of their respective owners.
bsolute Maximum Ratings Voltage Between V+ and Terminals........................... 36V ±V SUPPLY to Ground (V+, ).................................. ±18V V R to Ground............................................ -V SUPPLY V L to Ground........................................... +V SUPPLY Digital and nalog Input Voltage (V, V S, V D )............ +V SUPPLY +4V -V SUPPLY -4V Peak Current (Source to Drain) (Pulse at 1ms, 10% Duty Cycle Max)........................ 70m Continuous Current (ny Pin)................................ 20m ESD Rating..............................................<2000V Thermal Information Thermal Resistance θ J ( C/W) θ JC ( C/W) CLCC Package........................ 8O 20 Package Power Dissipation at +75 C CLCC Package............................................ 1.0W Package Power Dissipation Derating Factor above +75 C CLCC Package......................................12.5mW/ C Junction Temperature.....................................+175 C Storage Temperature Range........................-65 C to +150 C Lead Temperature (Soldering 10s)...........................+300 C Recommended Operating Conditions Operating Temperature Range......................-55 C to +125 C Operating Supply Voltage....................................±15V Logic Supply Voltage (V L ).................................... +5.0V Logic Reference Voltage (V R )..................................0.0V nalog Input Voltage (V S )................................ ±V SUPPLY ddress Low Level (V L ).................................0V to 0.8V ddress High Level (V H ).............................. 2.4V to +5.0V CUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. TBLE 1. D.C. ELECTRICL PERFORMNCE SPECIFICTIONS Device Tested at: Supply Voltage = ±15V, V L = +5.0V, V R = 0.0V, V H = 2.4V, V L = +0.8V, unused pins are grounded, unless otherwise specified. D.C. PRMETERS SYMBOL CONDITIONS Switch ON Resistance R DS2 V D = -10V, I S = 10m Source OFF Leakage Current Drain OFF Leakage Current Channel ON Leakage Current I S(OFF) I D(OFF) I D(ON) V D = 10V, I S = -10m V S = -10V, V D = 10V V S = 10V, V D = -10V V D = -10V, V S = 10V V D = 10V, V S = -10V V D = V S = 10V V D = V S = -10V GROUP SUBGROUPS TEMPERTURE ( C) M MX UNITS 1 +25-45 Ω 2, 3-55 to +125-50 Ω 1 +25-45 Ω 2, 3-55 to +125-50 Ω 1 +25-1 1 n 2, 3-55 to +125-100 100 n 1 +25-1 1 n 2, 3-55 to +125-100 100 n 1 +25-1 1 n 2, 3-55 to +125-100 100 n 1 +25-1 1 n 2, 3-55 to +125-100 100 n 1 +25-2 2 n 2, 3-55 to +125-200 200 n 1 +25-2 2 n 2, 3-55 to +125-200 200 n Low Level ddress Current I L V = 0V 1 +25-1 1 µ 1, 2 2, 3-55 to +125-10 1 µ High Level ddress Current I H V = 2.4V, 5V 1 +25-1 1 µ 1, 2 2, 3-55 to +125-1 10 µ Positive Supply Current +I CC V = 0V, 5V 1 +25-200 µ 1, 2 2, 3-55 to +125-300 µ Negative Supply Current -I CC V = 0V, 5V 1 +25-200 - µ 1, 2 2, 3-55 to +125-300 - µ 2 FN8289.0
TBLE 1. D.C. ELECTRICL PERFORMNCE SPECIFICTIONS (Continued) Device Tested at: Supply Voltage = ±15V, V L = +5.0V, V R = 0.0V, V H = 2.4V, V L = +0.8V, unused pins are grounded, unless otherwise specified. D.C. PRMETERS SYMBOL CONDITIONS GROUP SUBGROUPS TEMPERTURE ( C) M MX UNITS Logic Supply Current +I L V = 0V, 5V 1 +25-200 µ 2, 3-55 to +125-300 µ Reference Supply Current +I R V = 0V, 5V 1 +25-200 - µ 2, 3-55 to +125-300 - µ TBLE 2..C. ELECTRICL PERFORMNCE SPECIFICTIONS Device Tested at: Supply Voltage = ±15V, V L = +5.0V, V R = 0.0V, V H = +5.0V, V L = +0.0V, unused pins are grounded, unless otherwise specified. PRMETERS SYMBOL CONDITIONS Turn ON Time t ON V S = 10V, -10V C L = 10pF R L = 1kΩ Turn OFF Time t OFF V S = 10V, -10V C L = 10pF R L = 1kΩ GROUP SUBGROUPS TEMPERTURE ( C) M MX UNITS 11-55 - 450 ns 9 +25-500 ns 10 +125-800 ns 11-55 - 350 ns 9 +25-450 ns 10 +125-600 ns TBLE 3. ELECTRICL PERFORMNCE SPECIFICTIONS (NOTE 1) Device Characterized at: Supply Voltage = ±15V, V L = +5.0V, V R = 0.0V, V H = 4.0V, V L = 0.8V, unused pins are grounded, unless otherwise specified. PRMETERS SYMBOL CONDITIONS NOTE ON Resistance Match (Channel to Channel) R ON2 Match V D = ±10V I D = 10m TEMPERTURE ( C) M MX UNITS 1 +25-10 Ω ddress Capacitance C V = 0V, 5V 1 +25-45 pf Switch Input Capacitance C S(OFF) Switch Off: V = 0V 1 +25-60 pf Switch Output Capacitance C D(OFF) Switch Off: V = 0V 1 +25-60 pf C D(ON) Switch On: V = 5V 1 +25-60 pf Drain to Source Capacitance C DS(OFF) Switch Off: V = 0V 1 +25-10 pf Off Isolation V ISO V S = 2V P-P @ f = 100kHz, R L =100Ω 1 +25-60 db Crosstalk V CT V S = 2V P-P @ f = 100kHz, R L =100Ω Charge Transfer Error V CTE V S = GND, C L = 0.01µF V = 0V to 4V @ f = 200kHz 1 +25-60 db 1 +25-30 mv NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TBLE 4. ELECTRICL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (See Tables 1 and 2) Interim Electrical Parameters (Pre Burn-in) 1 Final Electrical Test Parameters 1 (Note 2), 2, 3, 9, 10, 11 Group Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 2. PD applies to Subgroup 1 only. 3 FN8289.0
Test Circuits 10m V 2 R ON = 10m V 2 I S(OFF) I D(OFF) ±10V ±10V ±10V FIGURE 1. R DS FIGURE 2. I S(OFF) I S(OFF) I D(OFF) I D(ON) ±10V ±10V ±10V FIGURE 3. I D(OFF) FIGURE 4. I D(ON) +V CC +I CC +V CC V GND -I CC V I -V CC GND -V CC FIGURE 5. DDRESS CURRENT FIGURE 6. SUPPLY CURRENTS 4 FN8289.0
Test Circuits (Continued) V 2V P-P 50Ω R L V V 2V P-P SWITCHED CHNNEL 50Ω V R L OFF ISOLTION 20 Log V = --------------- V FIGURE 7. OFF ISOLTION R L CROSSTLK 20 Log V = --------------- V NOTE: pplies only to dual or double throw switches. FIGURE 8. CROSSTLK S D 0.01MF TO MESUREMENT CIRCUITRY WITH PUT RESISTNCE OF 1MΩ OR GRETER DRIVER f = 200kHz SQURE WVE t R 20ns IF PULSE TEST IS USED: t R, t F 20ns V (DRIVER) V CTE NOTE: V CTE may be a positive or negative value. SWITCHG TRNSIENT DROOP CUSED BY DEVICE LEKGE ND MESUREMENT CIRCUITRY FIGURE 9. CHRGE TRNSFER Test Characteristics V H V L V 90% 90% +10V 1 2 t ON t OFF 90% 90% 1 2 1k 1k V t OFF t ON FIGURE 10. ON/OFF SWITCH TIME (t ON, t OFF ) 5 FN8289.0
Test Characteristics (Continued) 720 660 600 540 480 420 t 360 ON 300 t OFF 240 180 120 60 2.4 3.0 3.6 4.2 4.8 DIGITL HIGH (V H ) FIGURE 11. SWITCHG TIMES FOR DIGITL TRNSITION 720 660 600 540 480 420 360 t ON 300 240 t OFF 180 120 60 0 0.5 1.0 1.5 DIGITL LOW (V L ) FIGURE 12. SWITCHG TIMES FOR NEGTIVE DIGITL TRNSITION Test Waveforms 5V 5V PUT PUT PUT PUT 5V 100ns 5V 100ns Vertical Scale: Input = 5V/Div, (TTL; V H = 5V, V L = 0V) Output = 5V/Div Horizontal Scale: 100ns/Div FIGURE 13. Vertical Scale: Input = 5V/Div, (CMOS; V H = 10V, V L = 0V) Output = 5V/Div Horizontal Scale: 100ns/Div FIGURE 14. 6 FN8289.0
Burn-In Circuit HI-5051/883 CERMIC LCC NOTES: R 1 thru R 4 = 10kΩ, ±5%, 1/4W (Min) C 1, C 2, C 3 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min) D 1, D 2, D 3 = 1N4002 or Equivalent/Board V L = 5.5V ±0.5V 2 = 2 = 5.5V ±0.5V (V+) - () = 30V 7 FN8289.0
Schematic Diagrams V+ V+ R3 VR 1 ( 2 ) TO (V R ) V+ N1 P2 N3 N2 P1 NOTE: Connect V+ to V L for minimizing power consumption when driving from CMOS circuits. FIGURE 15. TTL/CMOS REFERENCE CIRCUIT 1 ( 2 ) FIGURE 16. SWITCH CELL P3 V+ R4 200Ω V+ D1 D2 P1 N1 V R ' V L ' P4 P5 P6 P7 P8 P9 P10 P11 P12 1 1 2 2 P2 N2 N4 N5 N6 N7 N8 N9 N10 N11 N12 N3 NOTE: ll N-Channel bodies to, all P-Channel bodies to V+ except as shown. DIGITL PUT BUFFER ND LEVEL SHIFTER 8 FN8289.0
Die Characteristics DIE DIMENSIONS: 96mils x 81mils x 20mils (2430µm x 2050µm x 508µm) METLLIZTION: Type: luminum Thickness: 16kÅ ±2kÅ GLSSIVTION: Type: Nitride over Silox Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1kÅ SUBSTRTE POTENTIL (Powered-up): DEVICE COUNT: 82 WORST CSE CURRENT DENSITY: 1.0 x 10 5 /cm 2 at 20m Metallization Mask Layout HI-5051/883 D 1 S 1 1 D 3 S 3 V R V L S 4 D 4 V+ 10 D 2 S 2 2 9 FN8289.0
Design Information The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves T = +25 C, V SUPPLY = ±15V 80 ON RESISTNCE (Ω) 60 40 20 V+ = +10V = -10V V+ = +12V = -12V V+ = +15V = -15V NORMLIZED ON RESISTNCE (REFERRED TO +25 C) 1.2 1.1 1.0 0.9 0.8 0.7 V = 0V 0-15 -10-5 0 5 10 15 NLOG SIGNL LEVEL (V) FIGURE 17. ON RESISTNCE vs NLOG SIGNL LEVEL ND POWER SUPPLY VOLTGE 0.6-50 -25 0 25 50 75 100 125 TEMPERTURE ( C) FIGURE 18. NORMLIZED ON RESISTNCE vs TEMPERTURE 1.4 100n NORMLIZED ON RESISTNCE (REFERRED TO 1m) 1.3 1.2 1.1 1.0 LEKGE CURRENT 10n 1n 100p I S(OFF) = I D(OFF) I D(ON) 0 20 40 60 80 NLOG CURRENT (m) FIGURE 19. NORMLIZED ON RESISTNCE vs NLOG CURRENT 10p 25 50 75 100 125 TEMPERTURE ( C) FIGURE 20. ON/OFF LEKGE CURRENTS vs TEMPERTURE -200 200 OFF ISOLTION (db) -160-120 -80-40 R L = 100Ω R L = 10kΩ CROSSTLK (db) 160 120 80 40 R L = 10kΩ R L = 1kΩ R L = 100Ω 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 21. OFF ISOLTION vs FREQUENCY 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 22. CROSSTLK vs FREQUENCY 10 FN8289.0
Design Information The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves T = +25 C, V SUPPLY = ±15V (Continued) 200 POWER CONSUMPTION (mw) 160 120 80 40 0 1k 10k 100k 1M TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 23. POWER CONSUMPTION vs FREQUENCY For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN8289.0
Ceramic Leadless Chip Carrier Packages (CLCC) HI-5051/883 j x 45 o 0.010 S E H S D D3 J20. MIL-STD-1835 CQCC1-N20 (C-2) 20 PD CERMIC LEDLESS CHIP CRRIER PCKGE CHES MILLIMETERS SYMBOL M MX M MX NOTES 0.060 0.100 1.52 2.54 6, 7 1 0.050 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 B E3 E B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC - D2 0.100 BSC 2.54 BSC - h x 45 o D3-0.358-9.09 2 0.010 S E F S E 0.342 0.358 8.69 9.09-1 PLNE 2 E1 0.200 BSC 5.08 BSC - E2 0.100 BSC 2.54 BSC - E3-0.358-9.09 2 -E- PLNE 1 e 0.050 BSC 1.27 BSC - e1 0.015-0.38-2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 0.007 M E F S HS L 0.045 0.055 1.14 1.40 - L B1 -H- e L3 L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 3 NE 5 5 3 N 20 20 3 E1 -F- E2 e1 L2 D1 B2 D2 B3 L1 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol N is the maximum number of terminals. Symbols ND and NE are the number of terminals along the sides of length D and E, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension controls the overall package thickness. The maximum dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per NSI Y14.5M-1982. 9. Controlling dimension: CH. 12 FN8289.0