DATASHEET EL57, EL57 55MHz Differential Twisted-Pair Drivers The EL57 and EL57 are single and triple high bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs can be in either single-ended or differential form but the outputs are always in differential form. On the EL57 and EL57, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see the EL57, EL57 data sheet (FN7). The output common mode level for each channel is set by the associated REF pin, which has a -db bandwidth of over MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL57 is available in a 8 Ld SOIC package and the EL57 is available in a 8 Ld QSOP package. All are specified for operation over the full - C to +85 C temperature range. Features Fully differential inputs, outputs, and feedback Differential input range ±.V 55MHz db bandwidth V/µs slew rate Low distortion at 5MHz Single 5V or dual ±5V supplies 6mA maximum output current Low power -.5mA per channel Pb-free (RoHS compliant) Applications FN7 Rev 9. Twisted-pair driver Differential line driver VGA over twisted-pair ADSL/HDSL driver Single-ended to differential amplification Transmission of analog signals in a noisy environment Pinouts EL57 (8 LD SOIC) TOP VIEW EL57 (8 LD QSOP) TOP VIEW FBP 8 OUT+ NC 8 OUT IN+ REF + - 7 6 VS- VS+ INP INN + - 7 FBP 6 FBN FBN 5 OUT- REF 5 OUTB NC 5 VSP INP 6 VSN INN 7 OUT REF NC 8 + FBP 9 - FBN INP INN REF NC + - 9 OUTB 8 OUT 7 FBP 6 FBN EN 5 OUTB FN7 Rev 9. Page of 5
Pin Descriptions EL57 EL57 PIN NAME PIN FUNCTION FBP Feedback from non-inverting output IN+ Non-inverting input REF Inverting inputs, note that on EL57, this pin is also the REF pin FBN Feedback from inverting output 5 OUT- Inverting output 6 VS+ Positive supply 7 VS- Negative supply 8 OUT+ Non-inverting output 7,, 7 FBP, FBP, FBP Feedback from non-inverting outputs, 6, INP, INP, INP Non-inverting inputs, 7, INN, INN, INN Inverting inputs, note that on EL57, this pin is also the REF pin 6,, 6 FBN, FBN, FBN Feedback from inverting outputs 5, 9, 5 OUTB, OUTB, OUTB Inverting outputs VSP Positive supply VSN Negative supply 8,, 8 OUT, OUT, OUT Non-inverting outputs, 5, 9, NC No connect; grounded for best crosstalk performance, 8, REF, REF, REF Reference inputs, sets common-mode output voltage EN ENABLE Ordering Information PART NUMBER (Notes,, ) PART MARKING TEMP. RANGE ( C) PACKAGE (RoHS Compliant) PKG. DWG. # EL57ISZ 57ISZ - to +85 8 Ld SOIC M8.5E EL57IUZ (No longer available, recommended replacement: EL57IUZ) EL57IUZ - to +85 8 Ld QSOP M8.5 NOTE:. Add -T* suffix for tape and reel. Please refer to TB7 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see device information page for EL57, EL57. For more information on MSL please see tech brief TB6. FN7 Rev 9. Page of 5
Absolute Maximum Ratings (T A = +5 C) Supply Voltage (V S + to V S -).................................... V Supply Voltage Rate-of-rise (dv/dt)........................... V/µs Input Voltage (IN+, IN- to V S +, V S -)............. V S - -.V to V S + +.V Differential Input Voltage (IN+ to IN-).......................... ±.8V Maximum Output Current.................................. ±6mA Thermal Information Thermal Resistance (Typical, Note ) JA ( C/W) 8 Ld SOIC Package............................... 8 Ld QSOP Package............................ 77.6 Operating Junction Temperature............................+5 C Ambient Operating Temperature.....................- C to +85 C Storage Temperature Range........................-65 C to +5 C Power Dissipation...................................... See Curves Pb-Free Reflow Profile............................... see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE:. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB79 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, V IN = V, R LD = k, =, = OPEN, C LD =.7pF, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS AC PERFORMANCE MIN (Note 5) TYP MAX (Note 5) BW -db Bandwidth A V =, C LD =.7pF 55 MHz A V =, = 5, C LD =.7pF MHz A V =, = 5, C LD =.7pF MHz BW ±.db Bandwidth A V =, C LD =.7pF MHz SR Slew Rate (EL57) V OUT = V P-P, % to 8% 8 V/µs Slew Rate (EL57) V OUT = V P-P, % to 8% 6 85 V/µs t STL Settling Time to.% V OUT = V P-P ns t OVR Output Overdrive Recovery Time ns GBWP Gain Bandwidth Product MHz V REF BW (-db) V REF -db Bandwidth A V =, C LD =.7pF MHz V REF SR+ V REF Slew Rate - Rise V OUT = V P-P, % to 8% V/µs V REF SR- V REF Slew Rate - Fall V OUT = V P-P, % to 8% 7 V/µs V N Input Voltage Noise at khz nv/ Hz I N Input Current Noise at khz.7 pa/ Hz HD Second Harmonic Distortion V OUT = V P-P, 5MHz -95 dbc V OUT = V P-P, MHz -9 dbc HD Third Harmonic Distortion V OUT = V P-P, 5MHz -88 dbc V OUT = V P-P, MHz -87 dbc dg Differential Gain at.58mhz R LD =, A V =.6 % d Differential Phase at.58mhz R LD =, A V =. e S Channel Separation - for EL57 only at f = MHz 9 db INPUT CHARACTERISTICS V OS Input Referred Offset Voltage (EL57) ±. ±5 mv (EL57) ±. ±5 mv I IN Input Bias Current (V IN +, V IN -) - - -7 µa I REF Input Bias Current (V REF ).5. µa R IN Differential Input Resistance 5 k UNIT FN7 Rev 9. Page of 5
Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, V IN = V, R LD = k, =, = OPEN, C LD =.7pF, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS C IN Differential Input Capacitance pf DMIR Differential Mode Input Range ±. ±. ±.5 V CMIR+ Common Mode Positive Input Range at V IN +, V IN -. V CMIR- Common Mode Negative Input Range at V IN +, V IN - -. V V REFIN + Positive Reference Input Voltage Range (EL57) V IN + = V IN - = V..7 V V REFIN - Negative Reference Input Voltage Range (EL57) V IN + = V IN - = V -. - V V REFOS Output Offset Relative to V REF (EL57) ±5 ± mv CMRR Input Common Mode Rejection Ratio (EL57) V IN = ±.5V 65 78 db Gain Gain Accuracy V IN = V (EL57).98.995. V V IN = V (EL57).978.99.8 V OUTPUT CHARACTERISTICS V OUT Output Voltage Swing R L = 5 to GND (EL57) ±. V R L = 5 to GND (EL57) ±.6 ±.8 V I OUT (Max) Maximum Output Current R L =, V IN + = ±.V ±5 ±6 ± ma R OUT Output Impedance m SUPPLY MIN (Note 5) V SUPPLY Supply Operating Range V S + to V S -.75 V I S(ON) Power Supply Current - Per Channel.5 ma I S(OFF) + Positive Power Supply Current - Disabled (EL57) EN pin tied to.8v.7 µa I S(OFF) - Negative Power Supply Current - Disabled (EL57) - - µa PSRR Power Supply Rejection Ratio V S from ±.5V to ±5.5V 6 75 db ENABLE (EL57 ONLY) t EN Enable Time ns t DS Disable Time. µs V IH EN Pin Voltage for Power-Up V S + -.5 V V IL EN Pin Voltage for Shut-Down V S + -.5 V I IH-EN EN Pin Input Current High At V EN = 5V 5 µa I IL-EN EN Pin Input Current Low At V EN = V - -8 µa NOTE: 5. Parameters with MIN and/or MAX limits are % tested at +5 C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TYP MAX (Note 5) UNIT FN7 Rev 9. Page of 5
FN7 Rev 9. Page 5 of 5 Connection Diagrams INP INN REF INP INN REF INP INN REF R SP 5 R SN 5 R SR 5 R SP 5 R SN 5 R SR 5 IN+ REF R SP 5 R S 5 R SN 5 R S 5 R SR 5 FBP OUT 8 INP VSN 7 REF VSP 6 FBN OUTB 5 FIGURE. EL57 NC INP INN REF 5 NC 6 INP 7 INN 8 REF 9 NC INP INN REF NC OUT 8 FBP 7 FBN 6 OUTB 5 VSP VSN OUT FBP FBN OUTB 9 OUT 8 FBP 7 FBN 6 EN OUTB 5 ENABLE FIGURE. EL57-5V +5V +5V -5V C L C L R LD k C L OUT OUTB C LB C L C LB R LD k R LD k C L R LD k C LB EL57, EL57
Typical Performance Curves A V =, R LD = k, C LD =.7pF R LD = k, C LD =.7pF MAGNITUDE (db) - - - - -5 V OP-P = mv V OP-P = V NORMALIZED MAGNITUDE (db) - - - - -5 A V = A V = 5 A V = A V = -6 M M M G -6 M M M G FIGURE. FREQUENCY RESPONSE FIGURE. FREQUENCY RESPONSE FOR VARIOUS GAIN A V =, R LD = k A V =, C LD =.7pF MAGNITUDE (db) 8 6 - - -6 C LD = C LD = pf C LD = 9pF C LD =.7pF C LD = pf MAGNITUDE (db) - - - - R LD = 5 R LD = R LD = k -8-5 - M M M G -6 M M G FIGURE 5. FREQUENCY RESPONSE vs C LD FIGURE 6. FREQUENCY RESPONSE vs R LD MAGNITUDE (db) A V =, R LD = k, C LD =.7pF 9 8 = k 7 6 5 = 5 = M M M M FIGURE 7. FREQUENCY RESPONSE MAGNITUDE (db) A V =, C LD =.7pF, = 75 9 8 7 R LD = k 6 5 R LD = 5 R LD = M M M M FIGURE 8. FREQUENCY RESPONSE vs R LD FN7 Rev 9. Page 6 of 5
Typical Performance Curves (Continued) MAGNITUDE (db) 5 - - - - PSRR (db) - - - - -5-6 -7-8 PSRR- PSRR+ -5 k M M M -9 k k M M M FIGURE 9. FREQUENCY RESPONSE - V REF FIGURE. PSRR vs FREQUENCY k CMRR (db) 8 6 VOLTAGE NOISE (nv/ Hz), CURRENT NOISE (pa/ Hz) E N I N - k k k M M M G FIGURE. CMRR vs FREQUENCY k k k M M FIGURE. VOLTAGE AND CURRENT NOISE vs FREQUENCY GAIN (db) - - - - -5 CH <=> CH, CH <=> CH -6-7 -8 CH <=> CH -9 - k M M M G IMPEDANCE ( ).. k k M M M FIGURE. CHANNEL ISOLATION (EL57 ONLY) FIGURE. OUTPUT IMPEDANCE vs FREQUENCY FN7 Rev 9. Page 7 of 5
Typical Performance Curves (Continued) - V S = ±5V, A V =, R LD = k - V S = ±5V, A V =, R LD = k -5 HD (f = 5MHz) -5 DISTORTION (db) -6-7 -8 HD (f = MHz) DISTORTION (db) -6-7 -8 HD (f = MHz) HD (f = 5MHz) -9 HD (f = MHz) HD (f = 5MHz) -..5..5..5..5 5. V OP-P, DM (V) FIGURE 5. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -9 HD (f = MHz) HD (f = 5MHz) - 5 6 7 8 9 V OP-P, DM (V) FIGURE 6. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE DISTORTION (db) -5-55 -6-65 -7-75 -8-85 -9-95 V S = ±5V, A V =, V OP-P, DM = V HD (f = MHz) HD (f = 5MHz) HD (f = 5MHz) HD (f = MHz) - 5 6 7 8 9 R LD ( ) FIGURE 7. HARMONIC DISTORTION vs R LD DISTORTION (db) V S = ±5V, A V =, V OP-P, DM = V -5-55 HD (f = MHz) -6-65 -7-75 -8-85 -9-95 HD (f = 5MHz) HD (f = MHz) HD (f = 5MHz) - 5 6 7 8 9 R LD ( ) FIGURE 8. HARMONIC DISTORTION vs R LD V S = ±5V, R LD = k, V OP-P, DM = V for A V =, V OP-P, DM = V for A V = - -5 HD (A V = ) DISTORTION (db) -6-7 -8-9 HD (A V = ) HD (A V = ) HD (A V = ) 5mV/DIV - 5 6 FREQUENCY (MHz) FIGURE 9. HARMONIC DISTORTION vs FREQUENCY ns/div FIGURE. SMALL SIGNAL TRANSIENT RESPONSE FN7 Rev 9. Page 8 of 5
Typical Performance Curves (Continued) M = ns, CH = 5mV/DIV, CH = 5V/DIV.5V/DIV CH CH ns/div FIGURE. LARGE SIGNAL TRANSIENT RESPONSE ns/div FIGURE. ENABLED RESPONSE CH CH JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD M = ns, CH = mv/div, CH = 5V/DIV. POWER DISSIPATION (W)..8.6...W 65mW SO8 JA = +6 C/W QSOP8 JA = +99 C/W 5 5 75 85 5 5 ns/div FIGURE. DISABLED RESPONSE AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W)...8.6...66W 99mW SO8 JA = + C/W QSOP8 JA = +79 C/W 5 5 75 85 5 5 AMBIENT TEMPERATURE ( C) FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7 Rev 9. Page 9 of 5
Simplified Schematic V S + R R R R R 7 R 8 IN+ IN- FBP FBN V B OUT+ R CD R CD REF C C V B OUT- R 9 R C C Description of Operation and Application Information Product Description The EL57 and EL57 are wide bandwidth, low power and single/differential ended to differential output amplifiers. The EL57 is a single channel differential amplifier. Since the I N - pin and REF pin are tied together internally, the EL57 can be used as a single-ended to differential converter. The EL57 is a triple channel differential amplifier. The EL57 has a separate I N - pin and REF pin for each channel. It can be used as single/differential ended to differential converter. The EL57 and EL57 are internally compensated for closed loop gain of + of greater. Connected in a gain of and driving a k differential load, the EL57 and EL57 have a -db bandwidth of 55MHz. Driving a differential load at gain of, the bandwidth is about MHz. The EL57 is available with a power-down feature to reduce the power while the amplifier is disabled. Input, Output and Supply Voltage Range The EL57 and EL57 have been designed to operate with a single supply voltage of 5V to V or split supplies with its total voltage from 5V to V. The amplifiers have an input common mode voltage range from -.V to.v for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -.V to +.V. The input voltage range at the REF pin is from -.V to.7v. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL57 and EL57 can swing from -.8V to +.8V at k differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings For EL57, since the I N - pin and REF pin are bound together as the REF pin in an 8 Ld package, the signal at the REF pin is part of the common mode signal and also part of the R 5 V S - R 6 differential mode signal. For the true balance differential outputs, the REF pin must be tied to the same bias level as the I N + pin. For a ±5V supply, just tie the REF pin to GND if the I N + pin is biased at V with a 5 or 75 termination resistor. For a single supply application, if the I N + is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL57 is expressed in Equation : V ODM V IN + + = + --------------------------- V ODM V IN + = = + ---------- V OCM = V REF = V Where: V REF = V = = The EL57 has a separate I N - pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one. The gain setting for EL57 is expressed in Equation : V ODM V IN + V IN - + = + --------------------------- V ODM V IN + V IN - = + ---------- V OCM = V REF Where: = = (EQ. ) (EQ. ) FN7 Rev 9. Page of 5
V IN + V IN - V REF FBP I N + I N - REF FBN FIGURE 6. V O + Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, has some maximum value that should not be exceeded for optimum performance. If a large value of must be used, a small capacitor in the few Pico farad range in parallel with can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL57 and EL57 depends on the load and the feedback network. and appear in parallel with the load for gains other than +. As this combination gets smaller, the bandwidth falls off. Consequently, also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +, = is optimum. For the gains other than +, optimum response is obtained with between 5 to k. The EL57 and EL57 have a gain bandwidth product of MHz for R LD = k. For gains 5, its bandwidth can be predicted by Equation : Gain BW = MHz (EQ. ) Driving Capacitive Loads and Cables The EL57 and EL57 can drive a pf differential capacitor in parallel with k differential load with less than 5dB of peaking at gain of +. If less peaking is desired in applications, a small series resistor (usually between 5 to 5 ) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than, the gain resistor can then be chosen to make up for any gain loss, which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination V O - resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down (for EL57 only) The EL57 can be disabled and its outputs placed in a high impedance state. The turn-off time is about.µs and the turn-on time is about ns. When disabled, the amplifier's supply current is reduced to.7µa for I S + and µa for I S - typically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the EN pin. The applied logic signal is relative to the V S + pin. Letting the EN pin float or applying a signal that is less than.5v below V S + will enable the amplifier. The amplifier will be disabled when the signal at the EN pin is above V S + -.5V. Output Drive Capability The EL57 and EL57 have internal short circuit protection. Its typical short circuit current is ±6mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±6mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL57 and EL57, it is possible to exceed the +5 C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation : T JMAX T AMAX PD MAX = -------------------------------------------- (EQ. ) Where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or as expressed in Equation 5: Where: JA PD i V STOT I SMAX VSTOT V O V O = + ----------- R LD V STOT = Total supply voltage = V S + - V S - I SMAX = Maximum quiescent supply current per channel V O = Maximum differential output voltage of the application R LD = Differential load resistance (EQ. 5) FN7 Rev 9. Page of 5
I LOAD = Load current i = Number of channels By setting the two PD MAX equations equal to each other, we can solve the output current and R LD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S - pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Typical Applications As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. R T EL57/ EL57 5 5 TWISTED PAIR Z O = IN+ FBP IN+ IN- REF FBN IN- REF EL575/ EL575 V O R R FIGURE 7. TWISTED PAIR CABLE RECEIVER GAIN (db) FBP R T 75 C I N + I N - V O + C L REF FBN V O - f L f H FREQUENCY DC Gain = + ---------- HF Gain = + -------------------------- C f L ------------------------ C C f H ---------------------------- C C C FIGURE 8. TRANSMIT EQUALIZER FN7 Rev 9. Page of 5
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN7.9 Updated Ordering Information table on page. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7 Rev 9. Page of 5
Package Outline Drawing M8.5E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9.9 ±. A DETAIL "A". ±. B 6. ±..9 ±. PIN NO. ID MARK 5.7. ±.76 (.5) x 5 ± TOP VIEW.5 MCAB SIDE VIEW B.75 MAX.5 ±..75 ±.75 SIDE VIEW A.5 GAUGE PLANE C SEATING PLANE. C.6 ±. (.7) (.6) DETAIL "A" (.5) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (5.)... 5. 6. Dimensioning and tolerancing conform to AMSE Y.5m-99. Unless otherwise specified, tolerance : Decimal ±.5 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.5mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS-. TYPICAL RECOMMENDED LAND PATTERN FN7 Rev 9. Page of 5
Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA e D B.7(.7) M C A M E -B- -A- -C- SEATING PLANE A B S H.5(.) M B A NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be.mm (. inch) total in excess of B dimension at maximum material condition.. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. GAUGE PLANE.(.).5. A M h x 5 L C M8.5 8 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (.5 WIDE BODY) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.5.69.5.75 - A....5 - A -.6 -.5 - B.8... 9 C.7..8.5 - D.86.9 9.8. E.5.57.8.98 e.5 BSC.65 BSC - H.8. 5.8 6.9 - h.99.96.6.9 5 L.6.5..7 6 N 8 8 7 8 8 - Rev. 6/ Copyright Intersil Americas LLC -5. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7 Rev 9. Page 5 of 5