& Digging Deeper Devices, Fabrication & Reliability For More Info:.com or email Dellin@ieee.org SAMPLE SLIDES & COURSE OUTLINE In : 2. A Easy, Effective, of How Devices Are.. Recommended for everyone who works with, or depends on, Technologies Integrated With Our Digging Deeper courses in Fabrication if you need more detail. Integrated With Other Courses: 1. Devices & 3. Reliability. 7 Hour Course Available Learning Formats: Live, Webinar, Narrated elearning, Course Notes & PowerPoint Slides. Dr. Theodore (Ted) Dellin Chief Scientist of the Center (retired), Sandia National Labs Reliability Lead (retired), Intl. Roadmap for s Quick Start Micro Training LLC, dellin@ieee.org,.com 2016, Dellin, All Rights Reserved. 1INTRODUCTION 1.1Overview of Dellin 1.2Overview of Fabrication Course 2MICRO TECHNIQUES 2.1 Photolithography 2.2 Subwavelength Photolithography 2.3Wafers, Defects, Planarization & Implant 2.4Thin Films and Etching 3HOW DEVICES ARE MADE 3.1Overview 3.2 CMOS IC 3.3Design, Layout & Test 3.4CMOS IC Process Flow 3.5 Microelectronics Industry 4PACKAGING 4.1 Package Types 4.2Package Performance 5MICRO ELECTRICAL MECHANICAL SYSTEMS 5.1 MEMS 5.2: Hybrid & Monolithic 5.3Applying a Voltage to a pn Junction 5.4Other types of Junctions
& Digging Deeper Devices, Fabrication & Reliability For More Info:.com or email Dellin@ieee.org CORE COMPETENCY CERTIFICATION IN SEMICONDUCTOR TECHNOLOGIES DEVICE TUTORIALS s Junctions MOS Transistor IC & Scaling Photodiode & Solar Cell LED and Laser DEVICE s Junctions Transistor Optoelectronics TUTORIALS Microfabrication Making Devices Packaging Micromachining & RELIABILITY TUTORIALS Integrated Circuit and Component Reliability CMOS IC Failure Mechanisms INTEGRATED DIGGING DEEPER COURSES Unit Processes CMOS IC Materials RELIABILITY Failure Mechanisms Rel Engineering Prob. & Statistics FORMATS Narrated elearning Webinars PowerPoint Slides In Person UNIQUE FEATURES Focused on real world needs of tech people Easy to understand. Picture how things work instead of focusing on equations Seamless integration of all tutorials 35 years experience in semiconductor technologies, reliability and training including: Chief Scientist of Research, & Components Center, Sandia National Lab Reliability Lead International Roadmap for s Reliability Technical Advisory Board, Sematech External Review Panel, NASA NEPP Tech. & Genl. Chair, IEEE Nonvolatile Memory Symposium FLC Award for Transfer 6 at IEEE Reliability Physics Symp. Unique training courses for industry & gov t.
CF1. Introduction Dellin CF1: Introduction 1.1 Overview of Dellin & 1.2 Overview of Fabrication Core Competency Intuitive - - - - IMPACT Evolutionary & Revolutionary Changes Analyze & Solve Problems Flexibility in job assignments : Intuitive & Knowledge 1 S +V GS D 2 W ( Vg Vth ) I ds, sat eff Cox L 2m IMPACT Derivation & Modeling Prediction & Optimization 2 Dellin Fills The Critical Need for Intuitive Knowledge Dellin Strategy For IMPACTFUL WORKING KNOWLEDGE Intuitive Knowledge Dellin Knowledge University Courses BASIC CORE COMPETENCY Devices-Fab-Reliability ALL Technical Folks Intuitive Knowledge Intuitive Knowledge Intuitive Knowledge TECH WORK FORCE IN-DEPTH EXPERTISE Selected Folks in Selected Areas Area 1 & Intuitive Area 2 & Intuitive 3 4 Overview of the Hierarchy In Making Devices Unit Modules Technologies Processes Wells Integrated Cleaning Circuits Isolation -CMOS Deposition Gate Stack -Bipolar -BiCMOS Lithography Source/Drain Discrete Contact Planarization Devices Metalization MEMS Etching Passivation -Bulk Doping Mechanical -Surface Layers Opto- Wafer Machining Electronics Assembly and Packaging Single Chip Packages MCMs System in A Package (SIP) Dellin : Integrated Curriculum Cover All Semi CORE COMPETENCY CERTIFICATION TUTORIALS Microfabrication How Devices Are Packaging Micromachining & IN-DEPTH TUTORIALS Unit Processes IC Manufacturing 5 BONUS TUTORIALS Materials Background 6.com
Dellin CF2: Microfabrication 2.1 Photolithography 2.2 Subwavelength Photolithography 2.3 Starting Wafers, Managing Defects, Planarization and Ion Implantation 2.4 Thin Films and Etching Spin on PR Bake Layer to be Patterned Wafer Pattern Definition Using Positive Photoresist (PR) Light Source Mask Developer Solution Expose Develop 7 Strip PR Etch 8 Mask Optical Proximity Correction Is a Key Enabler of Subwavelength Litho Light Intensity in PR Traditional Mask Feature on mask looks like desired feature However, does not accurately reproduce the feature on Silicon 2 Main Applications of CMP: Reduce Topography & Damascene Inlay Reduce Topography Damascene Inlay (Courtesy, Madge, LSI Logic) Optical Proximity Correction Distorts features and adds new subwavelength structures More accurate reproduction of desired feature on the wafer CMP Images courtesy of D. Hetherington, Sandia Natl. Lab. CMP 10 Many Choices for Depositing Films Each with Advantages & Disadvantages Method Type Consume Si? with Si Wafer Physical Vapor Deposition (PVD) Chemical Vapor Deposition Electroplating Spin on Films Chemical Physical Chemical Chemical Physical Conformal Coating? Temperature Examples Yes Yes High Oxide; Silicide No No Low Aluminum Titanium No Yes Low To High Oxide Polysilicon NItride No Yes Low Copper No No Low Photo Resist Isotropic Etch Etch proceeds in all directions Etch undercuts mask Can limit minimum feature size Typical of wet chemical etches Isotropic Vs. Anisotropic Etching Anisotropic Etch Etch proceeds only in vertical direction Can form deep contact holes and trenches with rectangular sidewalls Requires a direction dry etch (sputtering) Etch Mask (Photoresist) Lower level (not to be etched) 11 12.com
Dellin CF3: How Devices Are 3.1. Making a Device Overview 3.2. CMOS IC Manufacturing 3.3. Design Layout and Test 3.4. CMOS IC Process Flow 3.5. Microelectronics Industry 1. Develop a Silicon IC Manufacturing Making an IC Overview 3. Process the Silicon Wafers Using the Mask Set 2. Design the IC And Produce The Mask Set IC Requirements 13 4. Test the ICs On the Wafer 5. Cut Out the ICs, Package the ICS And Re-Test Deliver IC 14 Making an IC A More Detailed Look Next, The Physical Layout of the Circuit On an IC Must Be Developed Qualify New Develop New New Materials, Processes & Equipment Previous Process Recipes & Controls Design Rules Transistor Models Manufacture IC (Processing) Mask Set Layout IC & Check Rules Design & Verify IC Customer s Requirements For an IC Wafer Level Test How to Test Package Design Package & Final Test Qualify IC Deliver IC To Customer IN VDD S G p-ch D OUT D n-ch G S VSS n-active p-active POLY CONTACT METAL V SS (0V) (Externally Supplied Ground) n Channel Transistor Source Drain Input Signal Output Signal p Channel Transistor Source Drain V DD (Externally Supplied Voltage) After Rich Flores, Sandia 15 16 Expose Photoresist Through Mask 1 Expose photoresist using Mask 1 Where light hits the photoresist it undergoes a chemical change Integrated Device Manufacturer (IDM) vs. Foundry/Fabless OEM: Original Equipment Manufacturer Integrated Device Manuf. (IDM) Processing Design Packaging Foundry (Processing) Fabless Design Co. R&D Consortia Equipment & Supplies 17 18.com
Dellin CF4: Packaging Major Steps In Conventional Wire Bond, Plastic Packaging MODULES SECTIONS Wafers After 1 st Electrical Test Back Grinding (optional) Singulate (Dicing) Good Attach To Leadframe 4.1. Package Types 4.2. Package Performance Final Electrical Test Lead Forming 19 Plastic Encapsulation Wire Bonding Plastic Packaged Etched Away to Show Inside Analytical Solutions, Inc 20 Flip Chip (Level 1 Packaging) Has Advantages Over Wire Bonding Advanced Packaging: Stacked For Density & Speed Improvements Solder Balls With Underfill Circuit Board WITHIN Package Upside Down IC With Solder Balls on Bond Pads Shorter, more uniform electrical interconnect Lower parasitic inductance Highest frequency Smaller package area (when used with BGA) Higher pin counts Can use area array for IC bond pads In volume, potential for lower costs Potential for higher reliability Photo Courtesy of Samsung Now developing through Silicon via (TSV) technologies to run die to die interconnections through the wafers, not around the outside 21 22 The Package Temperature Rises Until Energy In = Energy Out What Makes MEMS/ Assembly and Packaging Different? 2. Which Generates Thermal Energy in The Package Causing the Package Temperature to Rise 1. Supply Electrical Energy to the Package 3. Which Causes Thermal Energy to Flow Out of The Package to the Lower Temperature Ambient As The Package Temperature Rises More Heat Flows Out. The Steady State Temperature Occurs When Heat Loss = Heat Gain Basically, want everything that IC packaging wants Plus, one or more of these features Let light in and out Let fluids and/or gasses in and out Allow for mechanical motion of parts inside package Plus, one or more of these complications during assembly Need to release surface micromachined parts Stiction from liquids or contact Temperature requirements Susceptibility to particles Non-IC materials 23 24.com
Dellin CF5: MEMS & IC Manufacturing Capabilities Enable Surface and Bulk Micromachining MODULES SECTIONS 5.1. Micro Electrical Mechanical Systems (MEMS) 5.2. Bulk MEMS 5.3. Surface MEMS 5.4. : Hybrid & Monolithic Integration 25 Features Built Above the Wafer Surface Features Built Into the Wafer Surface SURFACE Micro Machining BULK Micro Machining 26 Features Can Be Formed By Etching The Backside of the Wafer Trench Groove Membrane Nozzle Via Desirable Characteristics for Mechanical and Sacrificial Layer Mechanical layer Good mechanical properties Good electrical properties Good optical properties Controllable stress Features Using Backside Etching (Requires a two-sided aligner to do optical alignment of features on both sides of the wafer) Starting Si Wafer Sacrificial Layer Stable during processing Highly selective etch to remove sacrificial layer without attacking mechanical layer 27 28 Fabricating a Gear and Flanged Hub Two Approaches to : Hybrid and Monolithic Integration -Deposit conformal poly 2 layer (hub) HYBRID Integration (PC Board, MCM, System-in-a-Package) MEMS Or Pkg Opto Or Pkg MONOLITHIC Integration (System-on-a-Chip) Microelectronics MEMS Opto - Pattern Poly 2 (Hub) Different Technologies Individually Fabricated And Then Assembled Together Different Technologies Built On a Single 29 30.com