Disconinued Produc This device is no longer in producion. The device should no be purchased for new design applicaions. Samples are no longer available. Dae of saus change: Sepember 1, 2016 Recommended Subsiuions: no direc replacemen For exising cusomer ransiion, and for new cusomers or new applicaions, conac Allegro Sales. NOTE: For deailed informaion on purchasing opions, conac your local Allegro field applicaions engineer or sales represenaive. reserves he righ o make, from ime o ime, revisions o he anicipaed produc life cycle plan for a produc o accommodae changes in producion capabiliies, alernaive produc availabiliies, or marke demand. The informaion included herein is believed o be accurae and reliable. However, assumes no responsibiliy for is use; nor for any infringemens of paens or oher righs of hird paries which may resul from is use.
Feaures and Benefis AEC-Q100 Qualified Wide inpu volage range of 5 o 40 V for sar/sop, cold crank and load dump requiremens Fully inegraed LED curren sinks and boos converer wih 60 V DMOS Sync funcion o synchronize boos converer swiching frequency up o 2.3 MHz, allowing operaion above he AM band Excellen inpu volage ransien response Single resisor primary OVP minimizes V OUT leakage Inernal secondary OVP for redundan proecion LED curren of 80 ma per channel Drives up o 12 series LEDs in 4 parallel srings 0.7% o 0.8% LED o LED maching accuracy PWM and analog dimming inpus 5000:1 PWM dimming a 200 Hz Provides driver for exernal PMOS inpu disconnec swich Exensive proecion agains: Shored boos swich or inducor Shored FSET or ISET resisor Shored oupu Open or shored LED pin Open boos Schoky Overemperaure (OTP) Package: 20-pin TSSOP wih exposed hermal pad (suffix LP) No o scale Descripion The A8521 is a muli-oupu whie LED driver for small-size LCD backlighing. I inegraes a curren-mode boos converer wih inernal power swich and four curren sinks. The boos converer can drive up o 48 LEDs, 12 LEDs per sring, a 80 ma. The LED sinks can be paralleled ogeher o achieve even higher LED currens, up o 320 ma. The A8521 can operae wih a single power supply, from 5 o 40 V, which allows he par o wihsand load dump condiions encounered in auomoive sysems. The A8521 can drive an exernal P-FET o disconnec he inpu supply from he sysem in he even of a faul. The A8521 provides proecion agains oupu shor and overvolage, open or shored diode, open or shored LED pin, shored boos swich or inducor, shored FSET or ISET resisor, and IC overemperaure. A dual level cycle-by-cycle curren limi funcion provides sof sar and proecs he inernal curren swich agains high curren overloads. The A8521 has a synchronizaion pin ha allows PWM swiching frequencies o be synchronized in he range of 580 khz o 2.3 MHz. The high swiching frequency allows he A8521 o operae above he AM radio band. Coninued on he nex page Applicaions: LCD backlighing or LED lighing for: Auomoive infoainmen Auomoive cluser Auomoive cener sack Typical Applicaion Circui V IN 8 o 16 V R SC 0.033 Ω Q1 L1 D1 10 μh 2 A / 60 V V OUT C IN 4.7 μf 50 V 100 kω V C R ADJ 249 Ω R ISET 8.25 kω R C 20 Ω C C 22 nf C VDD 0.1 μf R FSET 10 kω GATE VSENSE VIN VDD FAULT APWM ISET FSET/SYNC AGND SW A8521 PAD PGND OVP LED1 LED2 LED3 LED4 COMP R OVP 137 kω C P 120 pf COUT 4.7 μf 50 V R Z 150 Ω C Z 0.47 μf Figure 1. Applicaion wih VIN o ground shor proecion, using P-MOSFET sensing A8521-DS
Descripion (coninued) The A8521 is provided in a 20-pin TSSOP package (suffix LP) wih an exposed pad for enhanced hermal dissipaion. I is lead (Pb) free, wih 100% mae in lead frame plaing. Selecion Guide Par Number Packing* A8521KLPTR-T 4000 pieces per 13-in. reel *Conac Allegro for addiional packing opions Absolue Maximum Raings* Characerisic Symbol Noes Raing Uni LEDx Pins 0.3 o 55 V OVP Pin 0.3 o 60 V VIN, VSENSE, GATE Pins VSENSE and GATE pins should no exceed V IN by more han 0.4 V 0.3 o 40 V SW Pin Coninuous 0.6 o 62 V < 50 ns 1.0 V F ĀŪ L T Pin -0.3 o 40 V ISET, FSET, APWM, COMP Pins 0.3 o 5.5 V All Oher Pins 0.3 o 7 V Operaing Ambien Temperaure T A Range K 40 o 125 ºC Maximum Juncion Temperaure T J (max) 150 ºC Sorage Temperaure T sg 55 o 150 ºC *Sresses beyond hose lised in his able may cause permanen damage o he device. The Absolue Maximum raings are sress raings only, and funcional operaion of he device a hese or any oher condiions beyond hose indicaed in he Elecrical Characerisics able is no implied. Exposure o Absolue Maximum-raed condiions for exended periods may affec device reliabiliy. Specificaions 2 Pin-ou Diagram and Terminal Lis 3 Characerisic Performance 8 Funcional Descripion 11 Enabling he IC 11 Powering up: LED pin shor-o-ground check 11 Sof sar funcion 13 Frequency selecion 13 Sync 14 LED curren seing and LED dimming 15 PWM dimming 15 APWM pin 16 Analog dimming 18 Table of Conens Overvolage proecion 19 Boos swich overcurren proecion 21 Inpu overcurren proecion and disconnec swich 22 Seing he curren sense resisor 23 Inpu UVLO 23 VDD 23 Shudown 23 Faul proecion during operaion 24 Applicaion Informaion 26 Design Example for Boos Configuraion 26 Design Example for SEPIC Configuraion 30 Package Ouline Drawing 34 2
Thermal Characerisics may require deraing a maximum condiions, see applicaion informaion Characerisic Symbol Tes Condiions* Value Uni Package Thermal Resisance R θja On 4-layer PCB based on JEDEC sandard (esimaed) 29.0 ºC/W On 2-layer PCB, 3 in. 2 40.0 ºC/W *Addiional hermal informaion available on he Allegro websie Pin-ou Diagram GATE 1 VSENSE 2 VIN 3 FAULT 4 COMP 5 APWM 6 7 FSET/SYNC 8 ISET 9 AGND 10 20 SW 19 OVP 18 PGND 17 PGND 16 PGND 15 VDD 14 LED1 13 LED2 12 LED3 11 LED4 Terminal Lis Table Number Name Funcion 1 GATE Oupu gae driver pin for exernal P-channel FET conrol. 2 VSENSE Connec his pin o he negaive sense side of he curren sense resisor R SC. The hreshold volage is measured as V IN V SENSE. There is also a fixed curren sink o allow for rip hreshold adjusmen. 3 VIN Inpu power o he A8521 as well as he posiive inpu used for curren sense resisor. 4 F ĀŪ L T 5 COMP 6 APWM 7 Indicaes a faul condiion. Connec a 100 kω resisor beween his pin and he required logic level volage. The pin is an open drain ype configuraion ha will be pulled low when a faul occurs. Oupu of he error amplifier and compensaion node. Connec a series R Z -C Z nework from his pin o ground for conrol loop compensaion. Analog rimming opion for dimming. Applying a digial PWM signal o his pin adjuss he inernal I SET curren. PWM dimming pin, used o conrol he LED inensiy by using pulse widh modulaion. Also used o enable he A8521. 8 FSET/SYNC Frequency/synchronizaion pin. A resisor R FSET from his pin o ground ses he swiching frequency. This pin can also be used o synchronize wo or more A8521s in he sysem. The maximum synchronizaion frequency is 2.3 MHz. 9 ISET Connec he R ISET resisor beween his pin and ground o se he 100% LED curren. 10 AGND LED signal ground. 11,12,13,14 LEDx Connec he cahodes of he LED srings o hese pins. 15 VDD Oupu of inernal LDO; connec a 0.1 μf decoupling capacior beween his pin and ground. 16,17.18 PGND Power ground for inernal DMOS device. 19 OVP Overvolage Condiion (OVP) sense; connec he R OVP resisor from V OUT o his pin o adjus he overvolage proecion. 20 SW The drain of he inernal DMOS swich of he boos converer. PAD Exposed pad of he package providing enhanced hermal dissipaion. This pad mus be conneced o he ground plane(s) of he PCB wih a leas 8 vias, direcly in he pad. 3
Funcional Block Diagram VDD SW Inernal V CC VIN Regulaor UVLO 1.235 V Ref V REF FSET/SYNC COMP Inernal V CC Oscillaor AGND + Driver Circui Faul Diode Open + Sense Inernal Sof Sar I SS Curren Sense + + PGND VSENSE Inpu Curren Sense Amplifier Thermal Shudown I ADJ GATE APWM PMOS Driver 100 kω Inernal V CC Enable PWM GOFF V REF ISET I SS LED Driver Faul OVP Sense V REF Open/Shor LED Deec OVP LED1 LED2 LED3 LED4 ISET Faul + AGND Faul FAULT PAD PGND AGND 4
ELECTRICAL CHARACTERISTICS 1,2 Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over he full operaing emperaure range wih T A = T J = 40 C o 125 C; unless oherwise noed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni Inpu Volage Specificaions Operaing Inpu Volage Range 3 V IN 5 40 V UVLO Sar Threshold V UVLOrise V IN rising 4.35 V UVLO Sop Threshold V UVLOfall V IN falling 3.90 V UVLO Hyseresis 2 V UVLOHYS 300 450 600 mv Inpu Currens Inpu Quiescen Curren I Q = V IH ; SW = 2 MHz, no load 5.5 10 ma Inpu Sleep Supply Curren I QSLEEP V IN = 16 V, V PWMEN = V FSETSYNC = 0 V 2 10.0 μa Inpu Logic Levels ( and APWM) Inpu Logic Level-Low V IL V IN hroughou operaing inpu volage range 400 mv Inpu Logic Level-High V IH V IN hroughou operaing inpu volage range 1.5 V Pin Open Drain Pull-down Resisor R PWMEN = 5 V 60 100 140 kω APWM Pull-down Resisor R APWM = V IH 60 100 140 kω APWM APWM Frequency 2 f APWM V IH = 2 V, V IL = 0 V 20 1000 khz Error Amplifier Open Loop Volage Gain A VOL 44 48 52 db Transconducance g m ΔI COMP = ±10 μa 750 990 1220 μa/v Source Curren I EA(SRC) V COMP = 1.5 V 350 μa Sink Curren I EA(SINK) V COMP = 1.5 V 350 μa COMP Pin Pull-down Resisance R COMP F ĀŪ L T = 0 2000 Ω Overvolage Proecion Overvolage Threshold V OVP(h) OVP conneced o V OUT 7.7 8.1 8.5 V OVP Sense Curren I OVPH 188 199 210 μa OVP Leakage Curren I OVPLKG R OVP = 40.2 kω, V IN = 16 V, = V IL 0.1 1 μa Secondary Overvolage Proecion V OVP(sec) 53 55 58 V Boos Swich Swich On-Resisance R SW I SW = 0.750 A, V IN = 16 V 75 300 600 mω Swich Leakage Curren I SWLKG V SW = 16 V, = V IL 0.1 1 μa Swich Curren Limi I SW(LIM) 3.0 3.5 4.2 A Secondary Swich Curren Limi 2 Higher han I I SW(LIM) (max) for all condiions, SW(LIM2) device laches when deeced 7.00 A Sof Sar Boos Curren Limi I SWSS(LIM) Iniial sof sar curren for boos swich 700 ma Minimum Swich On-Time SWONTIME 60 85 111 ns Minimum Swich Off-Time SWOFFTIME 30 47 68 ns Coninued on he nex page 5
ELECTRICAL CHARACTERISTICS 1,2 (coninued) Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over he full operaing emperaure range wih T A = T J = 40 C o 125 C; unless oherwise noed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni Oscillaor Frequency Oscillaor Frequency f SW R FSET = 20 kω 0.9 1 1.1 MHz R FSET = 10 kω 1.8 2 2.2 MHz R FSET = 35.6 kω 520 580 640 khz FSET/SYNC Pin Volage V FSET R FSET = 10 kω 1.00 V FSET Frequency Range f FSET 580 2500 khz Synchronizaion Synchronized PWM Frequency f SWSYNC 580 2300 khz Synchronizaion Inpu Minimum Off-Time PWSYNCOFF 150 ns Synchronizaion Inpu Minimum On-Time PWSYNCON 150 ns SYNC Inpu Logic Volage V SYNC(H) FSET/SYNC pin, high level 2.0 V V SYNC(L) FSET/SYNC pin, low level 0.4 V LED Curren Sinks LEDx Accuracy Err LED I SET = 120 μa 3 % LEDx Maching ΔLEDx I SET = 120 μa 3 % LEDx Regulaion Volage V LED V LED1 =V LED2 =V LED3 =V LED4, I SET = 120 μa 600 700 800 mv I SET o I LEDx Curren Gain A ISET I SET = 120 μa 633 653 672 A/A ISET Pin Volage V ISET 0.988 1.003 1.018 V Allowable ISET Curren I SET 20 120 μa Curren hrough each enabled LEDx pin Sof Sar LEDx Curren I LEDSS during sof sar 2.0 ma Maximum PWM Dimming Unil Off-Time 2 PWML Measured while = low, during dimming conrol and inernal references are powered-on (exceeding PWML resuls in shudown) 32,750 Minimum PWM On-Time PWMH Firs cycle when powering-up device 0.75 2 μs Time beween PWM enable and LED curren PWM High o LED-On Delay dpwm(on) reaching 90% of maximum Time beween PWM enable going low and PWM Low o LED-Off Delay dpwm(off) LED curren reaching 10% of maximum f SW cycles 0.5 1 μs 360 500 ns Coninued on he nex page 6
ELECTRICAL CHARACTERISTICS 1,2 (coninued) Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over he full operaing emperaure range wih T A = T J = 40 C o 125 C; unless oherwise noed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni GATE Pin GATE Pin Sink Curren I GSINK V GS = V IN 104 μa Gae Faul Shudown Greaer han 2X Curren 2 GFAULT2 3 μs Gae Faul Shudown Greaer han 1 2X Curren GFAULT1 10,000 Gae o source volage measured when gae Gae Volage V GS is on 6.7 V VSENSE Pin VSENSE Pin Sink Curren I ADJ 18.8 20.3 21.8 μa Measured beween VIN and VSENSE, VSENSE Trip Poin V SENSErip1 R ADJ = 0 Ω 94 104 114 mv VSENSE 2X Trip 2 V SENSErip2 2X V SENSErip, insananeous shudown, R ADJ = 0 Ω 180 mv F Ā Ū L T Pin F ĀŪ L T Pull-Down Volage V FAULT I FAULT = 1 ma 0.5 V F ĀŪ L T Pin Leakage Curren I FAULTLKG V FAULT = 5 V 1 μa Thermal Proecion (TSD) Thermal Shudown Threshold 2 T SD Temperaure rising 165 ºC Thermal Shudown Hyseresis 2 T SDHYS 20 ºC 1 For inpu and oupu curren specificaions, negaive curren is defined as coming ou of he node or pin (sourcing); posiive curren is defined as going ino he node or pin (sinking). 2 Ensured by design and characerizaion, no producion esed. 3 Minimum V IN = 5 V is only required a sarup. Afer sarup is compleed, he IC is able o funcion down o V IN = 4 V. f SW cycles 7
Characerisic Performance T A = T J I QSLEEP (μa) 10 9 8 7 6 5 4 3 2 1 0 VIN Inpu Sleep Mode Curren versus Ambien Temperaure 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 0-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130-50 -40-30 -20-10 10 20 30 40 50 60 70 80 90 100 110 120 130 VUVLOrise (V) VIN UVLO Sar Threshold Volage versus Ambien Temperaure Temperaure ( C) Temperaure ( C) fsw (MHz) 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 Swiching Frequency versus Ambien Temperaure 3.70 3.69 3.68 3.67 3.66 3.65 3.64 3.63 3.62 3.61 3.60 0-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130-50 -40-30 -20-10 10 20 30 40 50 60 70 80 90 100 110 120 130 VUVLOfall (V) VIN UVLO Sop Threshold Volage versus Ambien Temperaure Temperaure ( C) Temperaure ( C) I OVPH (μa) OVP Pin Sense Curren versus Ambien Temperaure 210 8.4 208 8.3 206 204 8.2 202 8.1 200 8.0 198 7.9 196 194 7.8 192 190-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 7.7 7.6-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 V OVP(h) (V) OVP Pin Overvolage Threshold versus Ambien Temperaure Temperaure ( C) Temperaure ( C) 8
V GS (V) -6.3-6.4-6.5-6.6-6.7-6.8 Inpu Disconnec Swich Gae o Source Volage versus Ambien Temperaure IADJ (μa) 20.8 20.7 20.6 20.5 20.4 20.3 20.2 20.1 VSENSE Pin Sink Curren versus Ambien Temperaure -6.9-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 20.0-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperaure ( C) Temperaure ( C) ILED (ma) LED Curren versus Ambien Temperaure 83 82 81 80 79 78 77 76 75-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperaure ( C) AISET (A/A) 670 I SET o LED Curren Gain versus Ambien Temperaure I SET = 120 μa 665 660 655 650 645 640-50 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperaure ( C) 3 LED o LED Maching Accuracy versus Ambien Temperaure 2 ΔLEDx (%) 1 0-1 -2-3 -50-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperaure ( C) 9
Efficiency (%) 96 94 92 90 88 86 84 82 80 78 Efficiency for Various LED Configura ons I LED = 70 ma, LED V f 3.2 V 5 7 9 11 13 15 17 Inpu Volage, V IN (V) 4 srings, 6 series LEDs each 4 srings, 7 series LEDs each 4 srings, 8 series LEDs each 100 Efficiency for Various LED Configura ons I LED = 80 ma, LED V f 3.2 V Efficiency (%) 95 90 85 80 75 5 7 9 11 13 15 17 Inpu Volage, V IN (V) 4 srings, 6 series LEDs each 4 srings, 7 series LEDs each 4 srings, 8 series LEDs each 10
The A8521 incorporaes a curren-mode boos conroller wih inernal DMOS swich, and four LED curren sinks. I can be used o drive four LED srings of up o 12 whie LEDs in series, wih curren up o 80 ma per sring. For opimal efficiency, he oupu of he boos sage is adapively adjused o he minimum volage required o power all of he LED srings. This is expressed by he following equaion: V OUT = max ( V LED1,..., V LED4 ) + V REG (1) where V LEDx is he volage drop across LED srings 1 hrough 4, and V REG is he regulaion volage of he LED curren sinks (ypically 0.7 V a he maximum LED curren). Funcional Descripion Powering up: LED pin shor-o-ground check The VIN pin has a UVLO funcion ha prevens he A8521 from powering-up unil he UVLO hreshold is reached. Afer he VIN pin goes above UVLO, and a high signal is presen on he pin, he IC proceeds o power-up. As shown in figure 3, a his poin he A8521 enables he disconnec swich and checks if any LEDx pins are shored o ground and/or are no used. The LED deec phase sars when he GATE volage of he disconnec swich is equal o V IN 4.5 V. Afer he volage hreshold on he LEDx pins exceeds 120 mv, a delay of beween 3000 and 4000 clock cycles is used o deermine he saus of he pins. Thus, he LED deecion duraion varies wih he swiching frequency, as shown in he following able: Enabling he IC The IC urns on when a logic high signal is applied on he pin wih a minimum duraion of PWMH for he firs clock cycle, and he inpu volage presen on he VIN pin is greaer han he 4.35 V necessary o clear he UVLO (V UVLOrise ) hreshold. The power-up sequence is shown in figure 2. Before he LEDs are enabled, he A8521 driver goes hrough a sysem check o deermine if here are any possible faul condiions ha migh preven he sysem from funcioning correcly. Also, if he FSET/SYNC pin is pulled low, he IC will no power-up. More informaion on he FSET/SYNC pin can be found in he Sync secion of his daashee. Swiching Frequency (MHz) Deecion Time (ms) 2 1.5 o 2 1 3 o 4 0.800 3.75 o 5 0.600 5 o 6.7 The LED pin deecion volage hresholds are as follows: LED Pin Volage LED Pin Saus Acion <70 mv Shor-o-ground Power-up is haled 150 mv No used LED removed from operaion 325 mv LED pin in use None VDD GATE = V IN 4.5 V FSET/SYNC ISET GATE LEDx LED deecion period ISET Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2, 1 V/div.), ISET (ch3, 1 V/div.), and (ch4, 2 V/div.) pins, ime = 200 μs/div. Figure 3. Power-up diagram; shows he relaionship of an LEDx pin wih respec o he gae volage of he disconnec swich (if used) during he LED deec phase, as well as he duraion of he LED deec phase for a swiching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 μs/div. 11
LED1 LED deecion period LED1 LED deecion period LED2 LED2 ISET ISET 4A. An LED deec occurring when boh LED pins are seleced o be used; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 μs/div. 4B. Example wih LED2 pin no being used; he deec volage is abou 150 mv; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 μs/div. Shor removed Pin shored LED1 LED2 ISET 4C. Example wih one LED shored o ground. The IC will no proceed wih power-up unil he shored LED pin is released, a which poin he LED is checked o see if i is being used; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 1 ms/div. 12
All unused pins should be conneced wih a 2.37 kω resisor o ground, as shown in figure 5. The unused pin, wih he pull-down resisor, will be aken ou of regulaion a his poin and will no conribue o he boos regulaion loop. If a LEDx pin is shored o ground he A8521 will no proceed wih sof sar unil he shor is removed from he LEDx pin. This prevens he A8521 from powering-up and puing an unconrolled amoun of curren hrough he LEDs. Inrush curren caused by enabling he disconnec swich (when used) I OUT Operaion during I SWSS(lim) Sof sar funcion During sof sar he LEDx pins are se o sink (I LEDSS ) and he boos swich curren is reduced o he I SWSS(LIM) level o limi he inrush curren generaed by charging he oupu capaciors. When he converer senses ha here is enough volage on he LEDx pins he converer proceeds o increase he LED curren o he prese regulaion curren and he boos swich curren limi is swiched o he I SW(LIM) level o allow he A8521 o deliver he necessary oupu power o he LEDs. This is shown in figure 6. I IN V OUT Normal operaion I SW(lim) Frequency selecion The swiching frequency on he boos regulaor is se by he resisor conneced o he FSET/SYNC pin. The swiching frequency can be can be anywhere from 580 khz o 2.3 MHz. Figure 7 shows he ypical swiching frequencies, in MHz, for given resisor values, in kω. In case during operaion a faul occurs ha will increase he swiching frequency, he FSET/SYNC pin is clamped o a maximum swiching frequency of no more han 3.5 MHz. If he FSET/SYNC pin is shored o GND he par will shu down. For more deails see he Faul Mode able laer in his daashee. A8521 A8521 Figure 6. Sarup diagram showing he inpu curren, oupu volage, and oupu curren; shows I OUT (ch1, 200 ma/div.), I IN (ch2, 1 A/div.), V OUT (ch3, 20 V/div.), and (ch4, 5 V/div.), ime = 1 ms/div. f SW (MHz) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 30.0 32.5 35.0 GND LED1 LED2 LED3 LED4 GND LED1 LED2 LED3 LED4 Resisance for R SET (kω) Figure 7. Typical Swiching Frequency versus value of R FSET resisor. 2.37 kω Figure 5. Channel selec seup: (lef) using only LED1, LED2, and LED3, and (righ) using all four channels. 13
Sync The A8521 can also be synchronized using an exernal clock on he FSET/SYNC pin. Figure 8 shows he correspondence of a sync signal and he FSET/SYNC pin, and figure 9 shows he resul when a sync signal is deeced: he LED curren does no show any variaion while he frequency changeover occurs. A power-up if he FSET/SYNC pin is held low, he IC will no power-up. Only when he FSET/SYNC pin is ri-saed o allow he pin o rise, o abou 1 V, or when a synchronizaion clock is deeced, will he A8521 ry o power-up. The basic requiremen of he sync signal is 150 ns minimum onime and 150 ns minimum off ime, as indicaed by he specificaions for PWSYNCON and PWSYNCOFF. Figure 10 shows he iming for a synchronizaion clock ino he A8521 a 2.2 MHz. Thus any pulse wih a duy cycle of 33% o 66% a 2.2 MHz can be used o synchronize he IC. The SYNC pulse duy cycle ranges for seleced swiching frequencies are: SYNC Pulse Frequency (MHz) Duy Cycle Range (%) 2.2 33 o 66 2 30 o 70 1 15 o 85 0.800 12 o 88 0.600 9 o 91 If during operaion a sync clock is los, he IC will rever o he prese swiching frequency ha is se by he resisor R FSET. During his period he IC will sop swiching for a maximum period of abou 7 μs o allow he sync deecion circuiry o swich over o he exernally prese swiching frequency. If he clock is held low for more han 7 μs, he A8521 will shu down. In his shudown mode he IC will sop swiching, he inpu disconnec swich is open, and he LEDs will sop sinking curren. To shudown he IC ino low power mode, he user mus disable he IC using he PWM pin, by keeping he pin low for a period of 32,750 clock cycles. If he FSET/SYNC pin is released a any ime afer 7 μs, he A8521 will proceed o sof sar. Figure 8. Diagram showing a synchronized FSET/SYNC pin and swich node; shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 ma/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), ime = 2 μs/div. 2 MHz operaion FSET/SYNC 1 MHz operaion SW node V OUT I OUT Figure 9. Transiion of he SW waveform when he SYNC pulse is deeced. The A8521 swiching a 2 MHz, applied SYNC pulse a 1 MHz; shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 ma/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), ime = 5 μs/div. PWSYNCON 150 ns 154 ns V OUT I OUT FSET/SYNC SW node 150 ns PWSYNCOFF T = 454 ns Figure 10. SYNC pulse on and off ime requiremens. 14
V OUT LED curren seing and LED dimming The maximum LED curren can be up o 80 ma per channel, and is se hrough he ISET pin. To se he I LED curren, connec a resisor, R ISET, beween his pin and ground, according o he following formula: R ISET = (1.003 653) / I LED (2) where I LED is in A and R ISET is in Ω. This ses he maximum curren hrough he LEDs, referred o as he 100% curren. Sandard R ISET values, a gain equals 653, are as follows: COMP PWM I LED Sandard Closes R ISET Resisor Value (kω) LED curren per LED, I LED (ma) 8.25 80 10.2 65 16.5 40 22.1 30 Figure 11B. Typical PWM diagram showing V OUT, I LED, and COMP pin as well as he PWM signal. PWM dimming frequency is 500 Hz a 1% duy cycle ; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 50 ma/div.), ime = 500 μs/div. PWM PWM dimming The LED curren can be reduced from he 100% curren level by PWM dimming using he pin. When he pin is pulled high, he A8521 urns on and all enabled LEDs sink 100% curren. When is pulled low, he boos converer and LED sinks are urned off. The compensaion (COMP) pin is floaed, and criical inernal circuis are kep acive. The ypical PWM dimming frequencies fall beween 200 Hz and 1 khz. Figures 11A o 11D provide examples of PWM swiching behavior. I LED Figure 11C. Delay from rising edge of PWM signal o LED curren; shows PWM (ch1, 2 V/div.), and I LED (ch2, 50 ma/div.), ime = 200 ns/div. V OUT PWM COMP PWM I LED I LED Figure 11A. Typical PWM diagram showing V OUT, I LED, and COMP pin as well as he PWM signal. PWM dimming frequency is 500 Hz a 50% duy cycle; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 50 ma/div.), ime = 500 μs/div. Figure 11D. Delay from falling edge of PWM signal o LED curren urn off; shows PWM (ch1, 2 V/div.), and I LED (ch2, 50 ma/div.), ime = 200 ns/div. 15
Anoher imporan feaure of he A8521 is he PWM signal o LED curren delay. This delay is ypically less han 500 ns, which allows greaer accuracy a low PWM dimming duy cycles, as shown in figure 12. APWM pin The APWM pin is used in conjuncion wih he ISET pin (see figure 13). This is a digial signal pin ha inernally adjuss he ISET curren. When his pin is no used i should be ied o ground. The ypical inpu signal frequency is beween 20 khz and 1 MHz. The duy cycle of his signal is inversely proporional o he percenage of curren ha is delivered o he LEDs (figure 14). To use his pin for a rim funcion, he user should se he maximum oupu curren o a value higher han he required curren by a leas 5%. The LED I SET curren is hen rimmed down o he appropriae value. Anoher consideraion ha also is imporan is he limiaion of he user APWM signal duy cycle. In some cases i migh be preferable o se he maximum I SET curren o be 25% o 50% higher, hus allowing he APWM signal o have duy cycles ha are beween 25% and 50%. 10 APWM A8521 Err LED (%) 8 6 4 2 Wors-case Typical 0 0.1 1 10 100 PWM Duy Cycle, D (%) R ISET ISET PWM ISET Curren Mirror Curren Adjus LED Driver Figure 12. Typical percenage error, due o PWM-o-LED delay, for he average LED curren versus PWM duy cycle (a 200 Hz PWM frequency). Figure 13. Simplified block diagram of he APWM and ISET circui. IOUT (ma) 80 70 60 50 40 30 20 10 0 I OUT = 80 ma I OUT = 65 ma 0 20 40 60 80 100 %Err LED 12 10 8 6 4 2 0 I OUT = 65 ma I OUT = 80 ma 0 20 40 60 80 100 APWM Duy Cycle (%) APWM Duy Cycle (%) Figure 14. Oupu curren versus duy cycle; 200 khz APWM signal. Figure 15. Percenage Error of he LED curren versus PWM duy cycle; 200 khz APWM signal. 16
As an example, a sysem ha delivers a full LED curren of 80 ma per LED would deliver 60 ma of curren per LED when an APWM signal is applied wih a duy cycle of 25% (figures 16 and 17). Alhough he order in which APWM and he PWM signal are enabled does no maer, when enabling he A8521 ino low curren oupu while PWM and APWM dimming, he APWM signal should be enable before or a he same ime as he PWM signal. This sequence will preven he ligh oupu inensiy from changing during power up of he IC. Figure 18 shows he sequencing of he APWM and PWM signal during power-up o preven inadveren ligh inensiy changes. The full inensiy ligh oupu wih no APWM or PWM dimming is 80 ma per channel. I LED I LED APWM APWM Figure 16. Diagram showing he ransiion of LED curren from 60 ma o 80 ma, when a 25% duy cycle signal is removed from he APWM pin. PWM = 1; shows I LED (ch1, 50 ma/div.), APWM (ch2, 10 V/div.), and (ch3, 5 V/div.), ime = 500 μs/div. Figure 17. Diagram showing he ransiion of LED curren from 80 ma o 60 ma, when a 25% duy cycle signal is applied o he APWM pin; PWM = 1; shows I LED (ch1, 50 ma/div.), APWM (ch2, 10 V/div.), and (ch3, 5 V/div.), ime = 500 μs/div. APWM I LED I OUT APWM V OUT Figure 18. Diagram showing power-up sequencing LED curren of 5 ma per channel wih a 10% duy cycle PWM signal and a 95% duy cycle APWM signal; shows APWM (ch1, 5 V/div.), I LED (ch2, 50 ma/div.), (ch3, 5 V/div.), and V OUT (ch4, 10 V/div.), ime = 500 μs/div. Figure 19. Transiion of oupu curren level when a 50% duy cycle signal is applied o he APWM pin, in conjuncion wih a 50% duy cycle PWM dimming being applied o he PWM pin; shows I OUT (ch1, 50 ma/div.), APWM (ch2, 10 V/div.), and (ch3, 5 V/div.), ime = 500 μs/div. 17
Alhough he APWM dimming funcion has a wide frequency range, if his funcion is used sricly as an analog dimming funcion i is recommended o use frequency ranges beween 50 and 500 khz for bes accuracy. The frequency range mus be considered only if he user is no using his funcion as a closed loop rim funcion. Anoher limiaion is ha he propagaion delay beween his APWM signal and I OUT akes several milliseconds o change he acual LED curren. This effec is shown in figures 16, 17, and 19. Analog dimming The A8521 can also be dimmed by using an exernal DAC or anoher volage source applied eiher direcly o he ground side of he R ISET resisor or hrough an exernal resisor o he ISET pin (see figure 19). The limi of his ype of dimming depends on he range of he ISET pin. In he case of he A8521 he limi is 20 o 125 μa. For a single resisor (panel A of figure 20), he ISET curren is conrolled by he following formula: I SET = V ISET V DAC R ISET (3) where V ISET is he ISET pin volage and V DAC is he DAC oupu volage. When he DAC volage is 0 V he LED curren will be a is maximum. To keep he inernal gain amplifier sable, he user should no decrease he curren hrough he R ISET resisor o less han 20 μa For a dual-resisor configuraion (panel B of figure 20), he I SET curren is conrolled by he following formula: V ISET I SET = R ISET V DAC V ISET R 1 (4) The advanage of his circui is ha he DAC volage can be higher or lower, hus adjusing he LED curren o a higher or lower value of he prese LED curren se by he R ISET resisor: V DAC = 1.003 V; he oupu is sricly conrolled by R ISET V DAC > 1.003 V; he LED curren is reduced V DAC < 1.003 V; he LED curren is increased DAC VDAC GND R ISET A8521 ISET GND (A) DAC VDAC GND R1 R ISET A8521 ISET GND (B) Figure 20. Simplified diagrams of volage conrol of I LED : ypical applicaions using a DAC o conrol I LED using a single resisor (upper), and dual resisors (lower). 18
Overvolage proecion The A8521 has overvolage proecion (OVP) and open Schoky diode (D1 in figure 1) proecion. The OVP proecion has a defaul level of 8.1 V and can be increased up o 53 V by connecing resisor R OVP beween he OVP pin and V OUT. When he curren ino he OVP pin exceeds 199 μa (ypical), he OVP comparaor goes low and he boos sops swiching. The following equaion can be used o deermine he resisance for seing he OVP level: where: R OVP = ( V OUTovp V OVP(h) ) / I OVPH (5) V OUTovp is he arge overvolage level, R OVP is he value of he exernal resisor, in Ω, V OVP(h) is he pin OVP rip poin found in he Elecrical Characerisics able, and I OVPH is he curren ino he OVP pin. There are several possibiliies for why an OVP condiion would be encounered during operaion, he wo mos common being: a disconneced oupu, and an open LED sring. Examples of hese are provided in figures 21 and 22. Figure 21 illusraes when he oupu of he A8521 is disconneced from load during normal operaion. The oupu volage insanly increases up o OVP volage level and hen he boos sops swiching o preven damage o he IC. If he oupu is drained off, evenually he boos migh sar swiching for a shor duraion unil he OVP hreshold is hi again. Figure 22 displays a ypical OVP even caused by an open LED sring. Afer he OVP condiion is deeced, he boos sops swiching, and he open LED sring is removed from operaion. Aferwards V OUT is allowed o fall, and evenually he boos will resume swiching and he A8521 will resume normal operaion. Oupu disconnec even deeced V OUT V OUT LED sring open condiion deeced SW node SW node PWM PWM I OUT I OUT Figure 21. OVP proecion in an oupu disconnec even; shows V OUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and I OUT (ch4, 200 ma/div.), ime = 1 ms/div. Figure 22. OVP proecion in an open LED sring even; shows V OUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and I OUT (ch4, 200 ma/div.), ime = 500 μs/div. 19
A8521 also has buil-in secondary overvolage proecion o proec he inernal swich in he even of an open diode condiion. Open Schoky diode deecion is implemened by deecing overvolage on he SW pin of he device. If volage on he SW pin exceeds he device safe operaing volage raing, he A8521 disables and remains lached. To clear his faul, he IC mus be shu down eiher by using he signal or by going below he UVLO hreshold on he VIN pin. Figure 23 illusraes his. As soon as he swich node volage (SW) exceeds 60 V, he IC shus down. Due o small delays in he deecion circui, as well as here being no load presen, he swich node volage will rise above he rip poin volage. Figure 24 illusraes when he A8521 is being enabled during an open diode condiion. The IC goes hrough all of is iniial LED deecion and hen ries o enable he boos, a which poin he open diode is deeced. Open diode condiion deeced PWM SW node V OUT I OUT Figure 23. OVP proecion in an open Schoky diode even, while he IC is in normal operaion; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), V OUT (ch3, 20 V/div.), and I OUT (ch4, 200 ma/div.), ime = 1 μs/div. PWM Open diode condiion deeced SW node V OUT I OUT Figure 24. OVP proecion when he IC is enabled during an open diode condiion; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), V OUT (ch3, 10 V/div.), and I OUT (ch4, 200 ma/div.), ime = 500 μs/div. 20
Boos swich overcurren proecion The boos swich is proeced wih cycle-by-cycle curren limiing se a a minimum of 3.0 A. There is also a secondary curren limi ha is sensed on he boos swich. When deeced his curren limi immediaely shus down he A8521. The level of his curren limi is se above he cycle-by-cycle curren limi o proec he swich from desrucive currens when he boos inducor is shored. Various boos swich overcurren condiions are shown in figures 25 hrough 27. SW node SW node I L I L V OUT V OUT Figure 25. Normal operaion of he swich node (SW); inducor curren (I L ) and oupu volage (V OUT ) for 9 series LEDs in each of four srings configuraion; shows SW node (ch1, 20 V/div.), inducor curren I L (ch2, 1 A/div.), V OUT (ch3, 10 V/div.), and (ch4, 5 V/div.), ime = 2 μs/div. Figure 26. Cycle-by-cycle curren limiing; inducor curren (yellow race, I L ), noe reducion in oupu volage as compared o normal operaion wih he same configuraion (figure 26); shows SW node (ch1, 20 V/div.), inducor curren I L (ch2, 1 A/div.), V OUT (ch3, 10 V/div.), and (ch4, 5 V/div.), ime = 2 μs/div. FAULT SW node I L Figure 27. Secondary boos swich curren limi; when his limi is hi, he A8521 immediaely shus down; shows PWM (ch1, 5 V/div.), V OUT (ch2, 5 V/div.), SW node (ch3, 50 V/div.), and inducor curren I L (ch4, 2 A/div.), ime = 100 ns/div. 21
Inpu overcurren proecion and disconnec swich The primary funcion of he inpu disconnec swich is o proec he sysem and he device from caasrophic inpu currens during a faul condiion. The exernal circui implemening he disconnec is shown in figure 28. If he inpu disconnec swich is no used, he VSENSE pin mus be ied o VIN and he GATE pin mus be lef open. When selecing he exernal PMOS, check for he following parameers: Drain-source breakdown volage V (BR)DSS > 40 V Gae hreshold volage (make sure i is fully conducing a V GS = 4 V, and cu-off a 1 V) R DS(on) : Make sure he on-resisance is raed a V GS = 4.5 V or similar, no a 10 V; derae i for higher emperaure The inpu disconnec swich has wo modes of operaion: 1X mode When he inpu curren is beween one and wo imes he prese curren limi value, he disconnec swich eners a consan-curren mode for a maximum duraion of 10,000 cycles or 5 ms a 2 MHz. During his ime, he Faul flag is se immediaely and he disconnec swich goes ino a linear mode of operaion, in which he inpu curren will be limied o a value approximae o he 1X curren rip poin level (figure 29). If he faul correcs iself before he expiraion of he imer, he Faul flag will be removed and normal operaion will resume. The user can also during his ime decide wheher o shu down he A8521. To immediaely shu down he device, pull he FSET/ SYNC pin low for more han 7 μs. Afer he FSET/SYNC pin has been low for a period longer han 7 μs, he IC will sop swiching, he inpu disconnec swich will open, and he LEDx pins will sop sinking curren. The A8521 can be powered-down ino low power mode. To do so, disable he IC by keeping he pin low for a period of 32,750 clock cycles. To keep he disconnec swich sable while he disconnec swich is in 1X mode, use a 22 nf capacior for C C and a 20 Ω resisor for R C. Figure 29. Showing ypical wave forms for a 3-A, 1X curren limi under a faul condiion; shows f SW = 800 khz, F ĀŪ L T (ch1, 5 V/div.), I IN (ch2, 2 A/ div.), GATE (ch3, 5 V/div.), and (ch4, 5 V/div.), ime = 5 ms/div. FAULT I IN GATE (1) Iniial faul deeced (2) Disconnec swich goes ino a linear mode FAULT GATE I IN Faul flag se a 1X rip poin (3) I IN limied o 3 A (4) Afer 12.5 ms, disconnec swich shus down A8521 shus down a 2X rip poin V IN R SC Q1 To L1 R ADJ R C C C VSENSE VIN GATE A8521 Figure 30. 2X mode, secondary overcurren faul condiion. I IN is he inpu curren hrough he swich. The Faul flag is se a he 1X curren limi, and when he 2X curren limi is reached he A8521 disables he gae of he disconnec swich (GATE); shows F ĀŪ L T (ch1, 5 V/div.), GATE (ch2, 10 V/div.), I IN (ch3, 2 A/div.), and (ch4, 5 V/div.), ime = 5 μs/div. Figure 28. Typical circui showing he implemenaion of he inpu disconnec feaure. 22
2X curren limi If he inpu curren level goes above 2X of he prese curren limi hreshold, he A8521 will shu down in less han 3 μs regardless of user inpu (figure 30). This is a lached condiion. The Faul flag is also se o indicae a faul. This feaure is mean o preven caasrophic failure in he sysem due o inducor shor o ground, swich pin shor o ground, or oupu shor o ground. Seing he curren sense resisor The ypical hreshold for he curren sense circui is 104 mv, when R ADJ is 0 Ω. This volage can be rimmed by he R ADJ resisor. The ypical 1X rip poin should be se a abou 3 A, which coincides wih he cycle-by-cycle curren limi minimum hreshold. For example, given 3 A of inpu curren, and he calculaed maximum value of he sense resisor, R SC = 0.033 Ω. The R SC chosen is 0.03 Ω, a sandard. Also: R ADJ = (V SENSETRIP V ADJ ) / I ADJ (6) The rip poin volage is calculaed as: V ADJ = 3.0 A 0.03 Ω = 0.090 V R ADJ = (0.104 0.09 V) / (20.3 μa) = 731 Ω Inpu UVLO When V IN and V SENSE rise above he V UVLOrise hreshold, he A8521 is enabled. A8521 is disabled when V IN falls below he V UVLOfall hreshold for more han 50 μs. This small delay is used o avoid shuing down because of momenary gliches in he inpu power supply. When V IN falls below 4.35 V, he IC will shu down (see figure 31). VDD The VDD pin provides regulaed bias supply for inernal circuis. Connec he capacior C VDD wih a value of 0.1 μf or greaer o his pin. The inernal LDO can deliver no more han 2 ma of curren wih a ypical V DD of abou 3.5 V, enabling his pin o serve as he pull-up volage for he F Ā Ū L T pin. Shudown If he pin is pulled low for more han PWML (32,750 clock cycles), he device eners shudown mode and clears all I OUT Figure 31. Shudown showing a falling inpu volage (V IN ); shows V IN (ch1, 2 V/div.), I OUT (ch2, 200 ma/div.), V DD (ch3, 5 V/div.), and (ch4, 2 V/div.), ime = 5 ms/div. Figure 32. Shudown using he enable funcion, showing he 16 ms delay beween he signal and when he VDD and GATE of he disconnec swich urns off; shows GATE (ch1, 10 V/div.), I OUT (ch2, 200 ma/div.), V DD (ch3, 5 V/div.), and (ch4, 2 V/div.), ime = 5 ms/div. V IN V DD GATE I OUT V DD 23
inernal faul regisers. As an example, a a 2 MHz clock frequency, i will ake approximaely 16.3 ms o shu down he IC ino he low power mode (figure 32). When he A8521 is shu down, he IC will disable all curren sources and wai unil he signal goes high o re-enable he IC. If faser shu down is required, he FSET/SYNC pin can be used. Faul proecion during operaion The A8521 consanly moniors he sae of he sysem o deermine if any faul condiions occur during normal operaion. The response o a riggered faul condiion is summarized in he Faul Mode able. The possible faul condiions ha he device can deec are: Open LED pin, LED pin shored o ground, shored inducor, V OUT shor o ground, SW pin shored o ground, ISET pin shored o ground, and inpu disconnec swich source shored o ground. Noe he following: Some of he proecion feaures migh no be acive during sarup, o preven false riggering of faul condiions. Some of hese fauls will no be proeced if he inpu disconnec swich is no being used. An example of his is V OUT shor o ground. Faul Mode Table Faul Name Type Acive Primary swich overcurren proecion (cycle-by-cycle curren limi) Secondary swich curren limi Inpu disconnec curren limi Faul Flag Se Auo-resar Always No Lached Always Yes Lached Always Yes Secondary OVP Lached Always Yes Descripion This faul condiion is riggered by he cycle-bycycle curren limi, I SW(LIM). When he curren hrough he boos swich exceeds secondary curren SW limi (I SW(LIM2) ) he device immediaely shus down he disconnec swich, LED drivers, and boos. The Faul flag is se. To reenable he device, he pin mus be pulled low for 32,750 clock cycles. The device is immediaely shu off if he volage across he inpu sense resisor is 2X he prese curren value. The Faul flag is se. If he inpu curren limi is beween 1X and 2X, he Faul flag is se bu he IC will coninue o operae normally for GFAULT1 or unil i is shu down. To re-enable he device he pin mus be pulled low for 32,750 clock cycles. Secondary overvolage proecion is used for open diode deecion. When diode D1 opens, he SW pin volage will increase unil V OVP(SEC) is reached. This faul laches he IC. The inpu disconnec swich is disabled as well as he LED drivers, and he Faul flag is se. To re-enable he par he PWM pin mus be pulled low for 32,750 clock cycles. Boos Off for a single cycle Disconnec swich On Sink driver On Off Off Off Off Off Off Off Off Off Coninued on he nex page 24
Faul Mode Table (coninued) Faul Name Type Acive LED Pin Shor Proecion LED Pin open Faul Flag Se Auo-resar Sarup No Auo-resar Normal Operaion No ISET Shor Proecion Auo-resar Always No FSET/SYNC Shor Proecion Overvolage Proecion Overemperaure Proecion Auo-resar Always Yes Auo-resar Always No Auo-resar Always No VIN UVLO Auo-resar Always No Descripion This faul prevens he device from saring-up if eiher of he LEDx pins are shored. The device sops sof-sar from saring while eiher of he LEDx pins are deermined o be shored. Afer he shor is removed, sof-sar is allowed o sar. When an LEDx pin is open he device will deermine which LED pin is open by increasing he oupu volage unil OVP is reached. Any LED sring no in regulaion will be urned off. The device will hen go back o normal operaion by reducing he oupu volage o he appropriae volage level. This faul occurs when he ISET curren goes above 150% of he maximum curren. The boos will sop swiching, he disconnec swich will urn off, and he IC will disable he LED sinks unil he faul is removed. When he faul is removed he IC will ry o o regulae o he prese LED curren. Faul occurs when he FSET/SYNC curren goes above 150% of maximum curren, abou 180 μa. The boos will sop swiching, he disconnec swich will urn off, and he IC will disable he LED sinks unil he faul is removed. When he faul is removed he IC will ry o resar wih sof-sar. Faul occurs when OVP pin exceeds V OVP(h) hreshold. The A8521 will immediaely sop swiching o ry o reduce he oupu volage. If he oupu volage decreases hen he A8521 will resar swiching o regulae he oupu volage. Faul occurs when he die emperaure exceeds he overemperaure hreshold, 165 C. Faul occurs when V IN drops below V UVLO, 3.90 V maximum. This faul reses all lached fauls. Boos Disconnec Swich Sink driver Off On Off On On Off for open pins. On for all ohers. Off On Off Off Off Off Sop during OVP even. On On Off Off Off Off Off Off 25
Applicaion Informaion Design Example for Boos Configuraion This secion provides a mehod for selecing componen values when designing an applicaion using he A8521. The resuling design is diagrammed in figure 33. Assumpions: For he purposes of his example, he following are given as he applicaion requiremens: V BAT : 10 o 14 V Quaniy of LED channels, # CHANNELS : 4 Quaniy of series LEDs per channel, # SERIESLEDS : 10 LED curren per channel, I LED : 60 ma V f a 60 ma: 3.2 V f SW : 2 MHz T A (max): 65 C PWM dimming frequency: 200 Hz, 1% duy cycle Procedure: The procedure consiss of selecing he appropriae configuraion and hen he individual componen values, in an ordered sequence. Sep 1 Connec LEDs o pins LED1 and LED2. Sep 2 Deermining he LED curren seing resisor R ISET : R ISET = (V ISET A ISET ) / I LED (7) = (1.003 (V) 653) / 60 ma = 10.92 kω Choose a 11.00 kω resisor. Sep 3 Deermining he OVP resisor. The OVP resisor is conneced beween he OVP pin and he oupu volage of he converer. Sep 3a The firs sep is deermining he maximum volage based on he LED requiremens. The regulaion volage, V LED, of he A8521 is 700 mv. A consan erm, 2 V, is added o give margin o he design due o noise and oupu volage ripple. V OUT(OVP) = # SERIESLEDS V f + V LED + 2 (V) (8) = 10 3.2 V+ 0.7 V + 2 V = 34.7 V Then he OVP resisor is: R OVP = (V OUT(OVP) V OVP(h) ) / I OVPH (9) = (34.7 (V) 8.1 (V)) / 199 (μa) = 133.67 kω where boh I OVPH and V OVP(h) are aken from he Elecrical Characerisics able. Chose a value of resisor ha is higher value han he calculaed R OVP. In his case a value of 137 kω was seleced. Below is he acual value of he minimum OVP rip level wih he seleced resisor: V OUT(OVP) = 137 (kω) 199 (μa) + 8.1 (V) = 35.36 V Sep 3b A his poin a quick check mus be done o see if he conversion raio is accepable for he seleced frequency. D maxofboos = 1 SWOFFTIME f SW (10) = 1 68 (ns) 2.0 (MHz) = 86.4% where he minimum off-ime ( SWOFFTIME ) is found in he Elecrical Characerisics able. The Theoreical Maximum V OUT is hen calculaed as: V OUT (max) V IN (min) = 1 D maxofboos V d 10 (V) = 0.4 (V) = 73.13 V 1 0.864 where V d is he diode forward volage. The Theoreical Maximum V OUT value mus be greaer han he value V OUT(OVP). If his is no he case, he swiching frequency of he boos converer mus be reduced o mee he maximum duy cycle requiremens. (11) Sep 4 Selecing he inducor. The inducor mus be chosen such ha i can handle he necessary inpu curren. In mos applicaions, due o sringen EMI requiremens, he sysem mus operae in coninuous conducion mode hroughou he whole inpu volage range. 26
Sep 4a Deermining he duy cycle, calculaed as follows: D(max) = 1 V IN (min) V OUT(OVP) + V d 10 (V) = 1 =72.04% 35.36 (V) + 0.4 (V) (12) Sep 4b Deermining he maximum and minimum inpu curren o he sysem. The minimum inpu curren will dicae he inducor value. The maximum curren raing will dicae he curren raing of he inducor. Firs, he maximum inpu curren, given: I OUT = # CHANNELS I LED (13) = 4 0.060 (A) = 0.240 A hen: I IN (max) = V OUT(OVP) VIN (min) I OUT 35.36 (V) 240 (ma) = = 0.94 A 10 (V) 0.90 where η is efficiency. Nex, calculae minimum inpu curren, as follows: I IN (min) = V OUT(OVP) V IN (max) I OUT 35.36 (V) 240 (ma) = = 14 (V) 0.90 0.67 A A good approximaion of efficiency, η, can be aken from he efficiency curves locaed in he daashee. A value of 90% is a good saring approximaion. (14) (15) Sep 4c Deermining he inducor value. To ensure ha he inducor operaes in coninuous conducion mode, he value of he inducor mus be se such ha he ½ inducor ripple curren is no greaer han he average minimum inpu curren. A firs pas assumes I ripple o be 40% of he maximum inducor curren: hen: ΔI L = I IN (max) I ripple (16) = 0.94 0.40 = 0.376 A L = V IN(min) ΔI L f SW D(max) 10 (V) = 0.72 = 9.57 μh 0.376 (A) 2 (MHz) (17) Sep 4d Double-check o make sure he ½ curren ripple is less han I IN (min): I IN (min) > 1 / 2 ΔI L (18) 0.67 A > 0.19 A A good inducor value o use would be 10 μh. Sep 4e This sep is used o verify ha here is sufficien slope compensaion for he inducor chosen. The slope compensaion value is deermined by he following formula: 3.6 f Slope Compensaion = SW 2 10 6 = 3.6 A /μs (19) Nex inser he inducor value used in he design: ΔI Lused = V IN (min) D(max) L used f SW 10 (V) 0.72 = = 10 (μh) 2.0 (MHz) Calculae he minimum required slope: Required Slope (min) = ΔI Lused 1 f SW 1 10 6 (1 D(max)) 0.36 A 0.36 (A) 1 10 = 6 = 2.57 A/μs 1 (1 0.72) 2.0 (MHz) (20) (21) If he minimum required slope is greaer han he calculaed slope compensaion, he inducor value mus be increased. Noe: The slope compensaion value is in A/μs, and 1 10 6 is a consan muliplier. Sep 4f Deermining he inducor curren raing. The inducor curren raing mus be greaer han he I IN (max) value plus he ripple curren ΔI L, calculaed as follows: L(min) = I IN (max) + 1 / 2 ΔI Lused (22) = 0.94 (A) + 0.36 (A) / 2 = 1.12 A Sep 5 Deermining he resisor value for a paricular swiching frequency. Use he R FSET values shown in figure 7. For example, a 10 kω resisor will resul in a 2 MHz swiching frequency. Sep 6 Choosing he proper swiching diode. The swiching diode mus be chosen for hree characerisics when i is used in LED lighing circuiry. The mos obvious wo are: curren raing of he diode and reverse volage raing. 27
The reverse volage raing should be such ha during operaion condiion, he volage raing of he device is larger han he maximum oupu volage. In his case i is V OUT(OVP). The peak curren hrough he diode is calculaed as: I dp = I IN (max) + 1 / 2 ΔI Lused (23) = 0.94 (A) + 0.36 (A) / 2 = 1.12 A The hird major componen in deciding he swiching diode is he reverse curren, I R, characerisic of he diode. This characerisic is especially imporan when PWM dimming is implemened. During PWM off-ime he boos converer is no swiching. This resuls in a slow bleeding off of he oupu volage, due o leakage currens. I R can be a large conribuor, especially a high emperaures. On he diode ha was seleced in his design, he curren varies beween 1 and 100 μa. Sep 7 Choosing he oupu capaciors. The oupu capaciors mus be chosen such ha hey can provide filering for boh he boos converer and for he PWM dimming funcion. The bigges facors ha conribue o he size of he oupu capacior are: PWM dimming frequency and PWM duy cycle. Anoher major conribuor is leakage curren, I LK. This curren is he combinaion of he OVP leakage curren as well as he reverse curren of he swiching diode. In his design he PWM dimming frequency is 200 Hz and he minimum duy cycle is 1%. Typically, he volage variaion on he oupu, V COUT, during PWM dimming mus be less han 250 mv, so ha no audible hum can be heard. The capaciance can be calculaed as follows: C OUT = I LK 1 D(min) f PWM(dimming) V COUT (24) 1 0.01 = 200 μa = 3.96 μf 200 Hz 0.250 V A capacior larger han 3.96 μf should be seleced due o degradaion of capaciance a high volages on he capacior. A ceramic 4.7 μf 50 V capacior is a good choice o fulfill his requiremen. Corresponding capaciors include: Vendor Value Par number Muraa 4.7 μf 50 V GRM32ER71H475KA88L Muraa 2.2 μf 50 V GRM31CR71H225KA88L The rms curren hrough he capacior is given by: I COUT rms = I OUT I Lused D(max) + I IN (max) 12 1 D(max) 0.36 (A) 0.72 + = 0.240 (A) 0.94 (A) 12 = 0.39 A 1 0.72 (25) The oupu capacior mus have a curren raing of a leas 390 ma. The capacior seleced in his design was a 4.7 μf 50 V capacior wih a 3 A curren raing. Sep 8 Selecing inpu capacior. The inpu capacior mus be seleced such ha i provides a good filering of he inpu volage waveform. A good rule of humb is o se he inpu volage ripple ΔV IN o be 1% of he minimum inpu volage. The minimum inpu capacior requiremens are as follows: I Lused C IN = 8 f SW V IN 0.36 (A) = = 0.23 μf 8 2 (MHz) 0.1 (V) The rms curren hrough he capacior is given by: C IN rms = I OUT I Lused I IN (max) (1 D) 12 0.36 (A) 0.240 (A) = 0.94 (A) 0.095 A (1 0.72) 12 = A good ceramic inpu capacior wih raings of 2.2 μf 50 V or 4.7 μf 50 V will suffice for his applicaion. Corresponding capaciors include: Vendor Value Par number Muraa 4.7 μf 50 V GRM32ER71H475KA88L Muraa 2.2 μf 50 V GRM31CR71H225KA88L (26) (27) 28