EL, EL, EL, EL, EL Data Sheet January 7, 8 FN7.8 MHz Slew Enhanced VFs The ELx and ELx families represent highspeed VFs based on a CF amplifier architecture. This gives the typical high slew rate benefits of a CF family along with the stability and ease of use associated with the VF type architecture. With slew rates of V/µs, this family of devices enables the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family will also be available in single, dual, and triple versions, with MHz, MHz, and 7MHz versions. These are all available in single, dual, and triple versions. Both families operate on single V or ±V supplies from minimum supply current. ELx also features an output enable function, which can be used to put the output in to a highimpedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. Typical applications for these families will include cable driving, filtering, /D and D/ buffering, multiplexing and summing within video, communications, and instrumentation designs. Features Operates off V, V, or ±V applications Powerdown to µ (ELx) db bandwidth = MHz ±.db bandwidth = MHz Low supply current = m Slew rate = V/µs Low offset voltage = mv max Output current = m VOL = Differential gain/phase =.%/. Pbfree available (RoHS compliant) pplications Video amplifiers PCMCI applications /D drivers Line drivers Portable computers High speed communications RGB applications Broadcast equipment ctive filtering CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or 8886877 Intersil (and design) is a registered trademark of Intersil mericas Inc. Copyright Intersil mericas Inc. 7, 8. ll Rights Reserved ll other trademarks mentioned are the property of their respective owners.
EL, EL, EL, EL, EL Ordering Information PRT NUMBER PRT MRKING PCKGE PKG. DWG. # ELIS IS 8 Ld SOIC ( mil) MDP7 ELIST7* IS 8 Ld SOIC ( mil) MDP7 ELIST* IS 8 Ld SOIC ( mil) MDP7 ELISZ (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELISZT7* (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELISZT* (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELIWT7* q 6 Ld SOT MDP8 ELIWT7* q 6 Ld SOT MDP8 ELIWZT7* (Note) BBS 6 Ld SOT (Pbfree) MDP8 ELIWZT7* (Note) BBS 6 Ld SOT (Pbfree) MDP8 ELIC B Ld SC7 P.9 ELICT7* B Ld SC7 P.9 ELICT7* B Ld SC7 P.9 ELIWT7* g Ld SOT MDP8 ELIWT7* g Ld SOT MDP8 ELIWZT7* BBT Ld SOT (Pbfree) MDP8 ELIWZT7* BBT Ld SOT (Pbfree) MDP8 ELIY BR Ld MSOP (.mm) MDP ELIYT7* BR Ld MSOP (.mm) MDP ELIYT* BR Ld MSOP (.mm) MDP ELIYZ (Note) BD Ld MSOP (.mm) (Pbfree) MDP ELIYZT7* (Note) BD Ld MSOP (.mm) (Pbfree) MDP ELIYZT* (Note) BD Ld MSOP (.mm) (Pbfree) MDP ELIS IS 8 Ld SOIC ( mil) MDP7 ELIST7* IS 8 Ld SOIC ( mil) MDP7 ELIST* IS 8 Ld SOIC ( mil) MDP7 ELISZ (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELISZT7* (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELISZT* (Note) ISZ 8 Ld SOIC ( mil) (Pbfree) MDP7 ELIY BS 8 Ld MSOP (.mm) MDP ELIYT7* BS 8 Ld MSOP (.mm) MDP ELIYT* BS 8 Ld MSOP (.mm) MDP ELIYZ (Note) BE 8 Ld MSOP (.mm) (Pbfree) MDP ELIYZT7* (Note) BE 8 Ld MSOP (.mm) (Pbfree) MDP ELIYZT* (Note) BE 8 Ld MSOP (.mm) (Pbfree) MDP ELIU IU 6 Ld QSOP ( mil) MDP ELIUT7* IU 6 Ld QSOP ( mil) MDP ELIUT* IU 6 Ld QSOP ( mil) MDP ELIUZ (Note) IUZ 6 Ld QSOP ( mil) (Pbfree) MDP ELIUZT7* (Note) IUZ 6 Ld QSOP ( mil) (Pbfree) MDP ELIUZT* (Note) IUZ 6 Ld QSOP ( mil) (Pbfree) MDP * Please refer to TB7 for details on reel specifications. NOTE: These Intersil Pbfree plastic packaged products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate PLUS NNEL e termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. FN7.8 January 7, 8
EL, EL, EL, EL, EL Pinouts EL (6 LD SOT) TOP VIEW EL ( LD SOT) TOP VIEW OUT 6 VS OUT VS IN CE IN VS IN VS IN EL (8 LD SOIC) TOP VIEW EL (8 LD SOIC, MSOP) TOP VIEW NC 8 CE OUT 8 VS IN 7 6 VS OUT NC 7 6 IN VS IN IN VS OUTB INB INB EL ( LD MSOP) TOP VIEW EL (6 LD QSOP) TOP VIEW OUT VS IN 6 IN 9 8 7 OUT IN IN IN VS IN CE VS CEB OUT VS OUTB CE 6 CE INB INB NC CEC INC 6 7 8 9 NC OUTC INC FN7.8 January 7, 8
EL, EL, EL, EL, EL bsolute Maximum Ratings (T = C) Supply Voltage between V S and GND...................V Maximum Supply Slewrate between V S and V S......... V/µs Input Voltage........................................±V S Differential Input Voltage...............................±V Maximum Continuous Output Current................... 8m Maximum Current into I N, I N, CE..................... ±m Thermal Information Power Dissipation............................. See Curves Storage Temperature Range..................6 C to C mbient Operating Temperature Range.......... C to 8 C Operating Junction Temperature...................... C Pbfree reflow profile..........................see link below http://www.intersil.com/pbfree/pbfreereflow.asp CUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTNT NOTE: ll parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T DC Electrical Specifications V S = V, V S = V, T = C, R L = Ω, V ENBLE = V, Unless Otherwise Specified. PRMETER DESCRIPTION CONDITIONS MIN TYP MX UNIT V OS Offset Voltage EL, EL, EL, EL mv EL 8 mv TCV OS Offset Voltage Temperature Coefficient Measured from T MIN to T MX µv/ C IB Input Bias Current V IN = V µ I OS Input Offset Current V IN = V 8 8 µ TCI OS Input Bias Current Temperature Coefficient Measured from T MIN to T MX n/ C PSRR Power Supply Rejection Ratio V S = ±.7V to ±.V 7 8 db CMRR Common Mode Rejection Ratio V CM = V to.v 6 8 db CMIR Common Mode Input Range Guaranteed by CMRR test ±. V R IN Input Resistance Common mode kω C IN Input Capacitance SO package pf I S,ON Supply Current Enabled Per mplifier.6..8 m I S,OFF Supply Current Shutdown Per mplifier V S 9 µ V S µ VOL Open Loop Gain V OUT = ±.V, R L = kω to GND 8 66 db V OUT = ±.V, R L = Ω to GND 6 db V OUT Output Voltage Swing R L = kω to GND ±. ±.9 V R L = Ω to GND ±. ±.7 V I OUT Output Current V =, R L = Ω to V ±8 ± m V CE ON CE Pin Voltage for Powerup (V S ) (V S ) V V CE OFF CE Pin Voltage for Shutdown (V S ) V S V I EN ON Pin Current Enabled CE = V µ I EN OFF Pin Current Disabled CE = V µ FN7.8 January 7, 8
EL, EL, EL, EL, EL Closed Loop C Electrical Specifications V S = V, V S = V, T = C, V ENBLE = V, V =, R F = Ω, R L = Ω to GND Pin, Unless Otherwise Specified. (Note ) PRMETER DESCRIPTION CONDITIONS MIN TYP MX UNIT BW db Bandwidth (V OUT = mv PP ) V =, R F = Ω MHz SR Slew Rate V =, R L = Ω, V OUT = V to V V/µs R L = Ω, V OUT = V to V V/µs t R,t F Rise Time, Fall Time ±.V step.8 ns OS Overshoot ±.V step % t S.% Settling Time, R L = Ω, V =, V OUT = ±V ns dg Differential Gain (Note ) V =, R F = kω. % dp Differential Phase (Note ) V =, R F = kω. e N Input Noise Voltage f = khz nv/ Hz i N Input Noise Current f = khz p/ Hz t DIS Disable Time (Note ) ns t EN Enable Time (Note ) ns NOTES:. ll C tests are performed on a warmed up part, except slew rate, which is pulse tested.. Standard NTSC signal = 86mV PP, f =.8MHz, as V IN is swept from.6v to.v.r L is DC coupled.. Disable/Enable time is defined as the time from when the logic signal is applied to the ENBLE pin to when the supply current has reached half its final value. FN7.8 January 7, 8
Typical Performance Curves EL, EL, EL, EL, EL V = R F = R L = Ω C L =.pf db BW @ 8MHz. M M M G PHSE ( ) 8 6 6 8 V = R F = R L = Ω C L =.pf. M M M G FIGURE. GIN vs FREQUENCY (db BNDWIDTH) FIGURE. PHSE vs FREQUENCY.. V =. R F =. R L = Ω C L =.pf.db BW @ MHz...... M M M FIGURE..dB BNDWIDTH GIN (db) 7 6 R L = Ω GIN = db or FREQUENCY =.6 MHz GIN BW PRODUCT =.6 x = 6MHz M M M FIGURE. GIN BNDWIDTH PRODUCT GINBNDWIDTH PRODUCT (MHz) R L = Ω........ 6. SUPPLY VOLTGES (±V) R L = Ω C L =.pf V = R F =.6k, R G = V = R F = R G = Ω V = R F =. M M M G FIGURE. GIN BNDWIDTH PRODUCT vs SUPPLY VOLTGES FIGURE 6. GIN vs FREQUENCY FOR VRIOUS V 6 FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) V = R F = R L = Ω C L =.pf V S = ±6 V S = ±V V S = ±V V S = ±.V. M M M G V S = ±V V = R F = C R L = Ω R L = kω L =.pf R L = Ω R L = 7Ω R L = Ω. M M M G FIGURE 7. GIN vs FREQUENCY FOR VRIOUS ±V S FIGURE 8. GIN vs FREQUENCY FOR VRIOUS R LOD ( V = ) V = R F = Ω C L =.9pF R L = Ω R L = 7Ω R L = Ω R L = Ω. M M M G FIGURE 9. GIN vs FREQUENCY FOR VRIOUS R LOD ( V = ) R L = kω V = R F = Ω C L =.9pF R L = Ω R L = 7Ω R L = Ω R L = Ω R L = kω. M M M FIGURE. GIN vs FREQUENCY FOR VRIOUS R LOD ( V = ) V = R F = R L = Ω C L = pf C L = 8.pF C L =.pf C L = pf C L = 7pF. M M M G V = R F = Ω R L = Ω C L = pf C L = 8pF C L = 8.pF C L = pf C L = 7pF. M M M G FIGURE. GIN vs FREQUENCY FOR VRIOUS C LOD ( V = ) FIGURE. GIN vs FREQUENCY FOR VRIOUS C LOD ( V = ) 7 FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) V = C L = pf C L = pf R F = Ω R C L = pf L = Ω C L = 6pF C L = pf. M M M V = R L = Ω C L = pf R F = Ω R F = Ω R F = Ω R F = Ω R F = Ω. M M M G FIGURE. GIN vs FREQUENCY FOR VRIOUS C LOD ( V = ) FIGURE. GIN vs FREQUENCY FOR VRIOUS R F ( V = ) R F =.kω V = R L = Ω R C L = 8pF F = 68Ω R F = Ω R F = 7Ω R F = Ω. M M M G FREQUENCY (MHz) V = R L = Ω C L = pf R F = Ω R F = kω R F = Ω R F = kω R F = kω. M M M FIGURE. GIN vs FREQUENCY FOR VRIOUS R F ( V = ) FIGURE 6. GIN vs FREQUENCY FOR VRIOUS R F ( V = ) V = R F = R G = Ω R L = Ω C L = 8pF C IN =.pf C IN =.pf C IN = pf C IN = pf C IN =.7pF. M M M G FIGURE 7. GIN vs FREQUENCY FOR VRIOUS C IN () ( V = ) V = R G = Ω R L = 6Ω C L = pf C IN = 8.pF C IN = 6.8pF C IN = pf C IN =.7pF C IN = pf. M M M FIGURE 8. GIN vs FREQUENCY FOR VRIOUS C IN () ( V = ) 8 FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) GIN (db) 8 7 6 GIN V CC = V V 6 EE = V k k k M M M G PHSE 9 8 7 PHSE ( ) OUTPUT IMPEDNCE (Ω).. V = k k M M M FIGURE 9. OPEN LOOP GIN ND PHSE vs FREQUENCY FIGURE. OUTPUT IMPEDNCE/PHSE vs FREQUENCY CMRR (db) 6 7 8 9 V = k k k M M M M PSRR (db) 6 7 V = PSRR 8 PSRR 9 k k k M M M M FIGURE. CMRR vs FREQUENCY FIGURE. PSRR vs FREQUENCY MX OUTPUT VOLTGE SWING (V PP ) 9 R LOD = kω 8 7 6 V = R F = R G = Ω R LOD = Ω C L = 8pF. M M M G GROUP DELY (ns) V = R F = R L = Ω. M M M G FIGURE. MX OUTPUT VOLTGE SWING vs FREQUENCY FIGURE. GROUP DELY vs FREQUENCY 9 FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) ISOLTION (db) 6 7 8 9 V = R F = CHIP DISBLED OUTPUT TO INPUT INPUT TO OUTPUT. M M M G GIN (db) 6 7 8 9 V = R F = R L = Ω NOTE: This was done on the EL (Dual Opmps) IN TO B OUT B IN TO OUT. M M M G FIGURE. INPUT ND OUTPUT ISOLTION FIGURE 6. CHNNELTOCHNNEL ISOLTION HRMONIC DISTORTION (dbc) 6 7 8 V = R F = R L = Ω C L =.pf V OUT = V PP nd HD T.H.D 9 rd HD. M M M FUNDMENTL THD (dbc) 6 7 8 9 V = R G = Ω R F = 6Ω R L = Ω C L = pf F IN = MHz F IN = MHz 6 7 8 OUTPUT VOLTGES (V PP ) FIGURE 7. HRMONIC DISTORTION vs FREQUENCY FIGURE 8. TOTL HRMONIC DISTORTION vs OUTPUT VOLTGES MPLITUDE (V) 6 ENBLE SIGNL OUTPUT SIGNL 6 6 8 6 TIME (ns) FIGURE 9. TURNON TIME V = R F = R L = Ω V OUT = V PP MPLITUDE (V) 6 V = R F = R L = Ω V OUT = V PP DISBLE SIGNL OUTPUT SIGNL 6 6 8 6 TIME (ns) FIGURE. TURNOFF TIME FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) NOISE VOLTGE (nv/ Hz) k k k FIGURE. EQUIVLENT NOISE VOLTGE vs FREQUENCY MPLITUDE (V)........ V = R F = R L = Ω C L =.pf V OUT = mv t RISE =.9ns t FLL =.9ns. 6 8 6 TIME (ns) FIGURE. SMLL SIGNL STEP RESPONSE RISE ND FLL TIME MPLITUDE (V) V = R G = Ω R L = Ω C L = pf V OUT =.V t RISE =.ns t FLL =.67ns 6 8 6 TIME (ns) FIGURE. LRGE SIGNL STEP RESPONSE RISE ND FLL TIME SUPPLY CURRENT (m) 6..8.6....8.6... V = R F = R L = Ω C L =.pf Please note that the curve showed positive Current. The negative current was almost the same........ 6. SUPPLY VOLTGE (V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTGE MPLITUDE (dbm) 6 7 8 9 V = R F = 6Ω R L = Ω C L = pf f = dbm @.9MHz ff = 76.8dBm @.8MHz ΔIM = () (77) = 78dB IP = (78/) = dbm f = dbm @.MHz ff = 77.dBm @.MHz.8M.9M.M.M.M IP (dbm) V = R F = 6Ω R L = Ω C L = pf M M M FIGURE. THIRD ORDER IMD INTERCEPT (IP) FIGURE 6. THIRD ORDER IMD INTERCEPT vs FREQUENCY FN7.8 January 7, 8
EL, EL, EL, EL, EL Typical Performance Curves (Continued) JEDEC JESD7 HIGH EFFECTIVE THERML CONDUCTIVITY TEST BORD. JEDEC JESD7 HIGH EFFECTIVE THERML CONDUCTIVITY TEST BORD. POWER DISSIPTION (W)..8.6...87W mw MSOP8/ θ J = C/W SOT/6 θ J = C/W POWER DISSIPTION (W)...8.6...6W.6W QSOP6 θ J = C/W SO8 θ J = C/W 7 8 MBIENT TEMPERTURE ( C) FIGURE 7. PCKGE POWER DISSIPTION vs MBIENT TEMPERTURE 7 8 MBIENT TEMPERTURE ( C) FIGURE 8. PCKGE POWER DISSIPTION vs MBIENT TEMPERTURE POWER DISSIPTION (W) JEDEC JESD LOW EFFECTIVE THERML CONDUCTIVITY TEST BORD.7 67mW.6. 88mW.... SOT/6 θ J = 6 C/W MSOP8/ θ J = 6 C/W POWER DISSIPTION (W) JEDEC JESD LOW EFFECTIVE THERML CONDUCTIVITY TEST BORD..8.6.. 79mW 78mW SO8 θ J = 6 C/W QSOP6 θ J = 8 C/W 7 8 7 8 MBIENT TEMPERTURE ( C) MBIENT TEMPERTURE ( C) FIGURE 9. PCKGE POWER DISSIPTION vs MBIENT TEMPERTURE FIGURE. PCKGE POWER DISSIPTION vs MBIENT TEMPERTURE FN7.8 January 7, 8
EL, EL, EL, EL, EL SOT Package Family. C D X C E SETING. C NX e N. C B X (L) 6 e B. M C B D b NX D H E D. C X MDP8 SOT PCKGE FMILY MILLIMETERS SYMBOL SOT SOT6 TOLERNCE.. MX.. ±... ±. b.. ±. c.. ±.6 D.9.9 Basic E.8.8 Basic E.6.6 Basic e.9.9 Basic e.9.9 Basic L.. ±. L.6.6 Reference N 6 Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. This dimension is measured at Datum Plane H.. Dimensioning and tolerancing per SME Y.M99.. Index area Pin # I.D. will be located within the indicated zone (SOT6 only). 6. SOT version has no center lead (shown as a dashed line). GUGE. c L FN7.8 January 7, 8
EL, EL, EL, EL, EL Quarter Size Outline Plastic Packages Family (QSOP) N D (N/) MDP QURTER SIZE OUTLINE PLSTIC PCKGES FMILY INCHES SYMBOL QSOP6 QSOP QSOP8 TOLERNCE NOTES E E PIN # I.D. MRK.68.68.68 Max..6.6.6 ±..6.6.6 ±. b... ±. B. C B (N/) c.8.8.8 ±. D.9..9 ±., E.6.6.6 ±.8 C SETING. C e.7 C B b H E... ±., e... Basic L... ±.9 L... Basic N 6 8 Reference c L SEE DETIL "X" Rev. F /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per SME Y.M99. GUGE. DETIL X L ± FN7.8 January 7, 8
Small Outline Package Family (SO) EL, EL, EL, EL, EL D h X N (N/) E E PIN # I.D. MRK c SEE DETIL X B. M C B (N/) L C e H SETING GUGE.. C. M C B b DETIL X L ± MDP7 SMLL OUTLINE PCKGE FMILY (SO) INCHES SO6 SO6 (. ) SO SO SO8 SYMBOL SO8 SO (. ) (SOL6) (SOL) (SOL) (SOL8) TOLERNCE NOTES.68.68.68.... MX.6.6.6.7.7.7.7 ±..7.7.7.9.9.9.9 ±. b.7.7.7.7.7.7.7 ±. c.9.9.9.... ±. D.9..9.6..66.7 ±., E.6.6.6.6.6.6.6 ±.8 E....9.9.9.9 ±., e....... Basic L....... ±.9 L....6.6.6.6 Basic h....... Reference N 8 6 6 8 Reference Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per SME Y.M99 FN7.8 January 7, 8
EL, EL, EL, EL, EL Small Outline Transistor Plastic Packages (SC7) E SETING e D e C L. (.8) M C C L WITH PLTING X θ X θ c C b VIEW C BSE METL C L C L. (.) C L L b b R α R VIEW C SETING C c GUGE L E C P.9 LED SMLL OUTLINE TRNSISTOR PLSTIC PCKGE INCHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES...8.......9.8. b.6... b.6... c..9.8. 6 c..9.8. 6 D.7.8.8. E.7.9.8. E.... e.6 Ref.6 Ref e. Ref. Ref L..8.6.6 L.7 Ref.. Ref. L.6 BSC. BSC α o 8 o o 8 o N R.. R.... Rev. 7/7 NOTES:. Dimensioning and tolerances per SME Y.M99.. Package conforms to EIJ SC7 and JEDEC MO.. Dimensions D and E are exclusive of mold flash, protrusions, or gate burrs.. Footlength L measured at reference to gauge plane.. N is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between.8mm and.mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only..mm.7mm.mm.6mm TYPICL RECOMMENDED LND PTTERN 6 FN7.8 January 7, 8
EL, EL, EL, EL, EL Mini SO Package Family (MSOP). M C B D (N/) N MDP MINI SO PCKGE FMILY MILLIMETERS SYMBOL MSOP8 MSOP TOLERNCE NOTES.. Max... ±. E E PIN # I.D..86.86 ±.9 b...7/.8 c.8.8 ±. B (N/) D.. ±., E.9.9 ±. E.. ±., C e H e.6. Basic L.. ±. SETING. C N LEDS c L b SEE DETIL "X".8 M C B L.9.9 Basic N 8 Reference Rev. D /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per SME Y.M99. GUGE. L DETIL X ± ll Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN7.8 January 7, 8