Lab Project EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 7 EE348L, Spring 2005
1 Lab Project 1.1 Introduction Based on your understanding of band pass filters and single transistor amplifiers in the previous labs, you will design, build, and test an amplifier with a band-pass filter front-end. The block diagram of the desired amplifier is shown in Figure 1-1. The band-pass filter is to be built using the second order Sallen-Key filter in Figure 2-12 in laboratory experiment 2. The output of the band-pass filter is ac-coupled to a cascade of three NMOS common-source amplifiers. The output of the final stage of the cascade of common-source amplifiers is ac-coupled to a load resistor, R L, whose value is 100 KΩ. Each common-source amplifier stage is to be built using the discrete NMOS transistor (2N7000) used in laboratory experiment 5 and should have a sourcedegeneration resistor for stable biasing considerations. 2 nd order Sallen-Key bandpass filter Cascade of three NMOS commonsource amplifiers v o (t) v in (t) + - R L Figure 1-1: Block diagram of amplifier to be designed. Supplies and Bias circuitry are not shown. 1.2 Background Band pass filter covered in laboratory experiment 2. Discrete MOSFET common-source amplifier covered in laboratory experiment 5. Two-stage MOSFET amplifier covered in laboratory experiment 6. 1.3 Specifications Laboratory component of project may be done in groups of two. Individual project reports are required. The project report should not be copied. Circuit schematics and measurements (tables and plots) can be the same for all members of a group. Second-order Sallen-Key band pass filter: Q = 2.5, f c = 5 KHz, gain = 1.5 Op-amp supply voltages: +15V, -15V. Cascade of three NMOS common-source amplifiers: Stage 1 gain of cascade of three-stage NMOS common-source amplifiers: at least 5 Stage 2 gain of cascade of three-stage NMOS common-source amplifiers: at least 4 B. Madhavan - 2 of 7- EE348L, Spring 2005
Stage 3 gain of cascade of three-stage NMOS common-source amplifiers: at least 2 Overall gain of cascade of three NMOS common-source amplifiers: at least 5 x 4 x 2 = 40 (32 db). Load resistance, R L :100 KΩ. NMOS amplifier supply voltage: 10V. V dd R D1 R D2 R D3 R b1 M 1 V D M 2 V D2 M 3 V D3 V G C c2 R b2 R SS1 R SS2 R SS3 Figure 1-2: Schematic of dc-coupled, cascade of 3-stage common-source NMOS transistor amplifier in Figure 1-1 for 100% of lab project grade. As show in Figure 1-2, it is desired to effect the cascade of three NMOS common-source amplifiers in Figure 1-1 as dc-coupled cascade, where the DC drain voltage of stage 1 sets the gate bias voltage of stage 2 and the DC drain voltage of stage 2 sets the gate bias voltage of stage 3. This has to be demonstrated for 100% of lab project grade. V dd R D R D2 R D3 R b1 M 1 V D R b3 M 2 R b4 M 3 V D3 V G1 C c2 V G2 V D2 Cc3 V G3 R b2 R SS R b4 R SS2 R b5 R SS3 Figure 1-3: Schematic of ac-coupled, cascade of 3-stage common-source NMOS transistor amplifier in Figure 1-1 for 70% of lab project grade. In the event of biasing difficulties, the common-source amplifier stages may be accoupled with inter-stage coupling capacitors C c2 and C c3 as shown in Figure 1-3, with a 30% penalty in your project grade. B. Madhavan Page 3 of 7 EE348L, Spring 2005
1.4 Bonus The project grade may be doubled if the overall gain of the cascade of three NMOS commonsource amplifiers is demonstrated to be 96 (39.65 db), such that 1. Stage 1 gain of cascade of three-stage NMOS common-source amplifiers: at least 8 2. Stage 2 gain of cascade of three-stage NMOS common-source amplifiers: at least 6 3. Stage 3 gain of cascade of three-stage NMOS common-source amplifiers: at least 2 4. Overall gain of cascade of three NMOS common-source amplifiers: at least 8 x 6 x 2 = 96 (39.65 db). The 30% penalty applies to the bonus for not having a dc-coupled NMOS amplifier cascade, as specified in the previous section. You are free to increase the supply voltage to 15V for the bonus part of the project. 1.5 Recommended Procedure 1. Follow an incremental design, build, and verification approach. Do not attempt to connect up the entire circuit and then start debugging it before verifying the correctness of each subblock of your design, namely the band-pass filter, each of the three NMOS common-source amplifiers and the cascaded three-stage NMOS common-source amplifier. 2. Perform the theoretical analysis of each circuit sub-block to guide its design and implementation before building it on the laboratory bench. This will be of tremendous assistance in quickly getting each circuit sub-block to work 3. Analyze and build the band pass filter first. Verify that it meets the desired specifications. 4. Analyze and build the first common-source amplifier stage. Tune the circuit as needed. Verify that its gain and dc-operating point meets your design criteria. 5. Analyze and build the cascade of stage 1 and stage 2 common-source amplifiers. Tune the circuit as needed. Verify that its gain and dc-operating point meets your design criteria. 6. Analyze and build the cascade all three stages of the cascade of common-source amplifiers. Connect the load resistor to the output of the cascade. Tune the circuit as needed. Verify that the gain and dc-operating point meets the project design criteria. 7. Hook up the circuit sub-blocks to satisfy the block diagram in Figure 1-1. Verify that its gain and dc-operating point meets the project design criteria. 1.6 Prelab (Required) Prepare design criteria for the second-order Sallen and Key band pass filter, each common-source amplifier stage, and the cascade of three common-source amplifiers, to meet the project specifications. Get it approved by your lab TA. 1.7 Measurements Since the signal source in the laboratory has a noise-free signal amplitude of 100mV, and the oscilloscope in the laboratory can only resolve only 50mV signals, you are limited to using signal amplitudes greater than 100mV. You are required to obtain the transient plots of each of the following at a frequency of 5 KHz and input signal amplitude of 100mV 1. band pass filter 2. Stage1 of cascade of common-source amplifiers B. Madhavan - 4 of 7- EE348L, Spring 2005
3. Cascade of stage 1 and stage 2 4. Cascade of stage 1, stage 2, and stage 3, with ac-coupled load-resistance of 100 KΩ. 5. Complete circuit of Figure 1-1. For the complete circuit of Figure 1-1, determine the overall gain of your circuit for input signal amplitudes of 100mV, 200mV, and 500mV at frequencies of 500 Hz, 1 KHz, 5KHz, 10 KHz and 50 KHz. Plot the simulated gain versus input signal amplitude for each of the three input signal frequencies. 1.8 Project Report 1. Follow the report format for the regular labs. 2. Your lab report should clearly show your reasoning for choosing the component values and dc-operating point of each of your circuits from the project specifications. This is a very important part of your project grade. 3. Tabulate the dc-operating point of each transistor your circuit. 4. Note down the node voltages of the final circuit with reference to the final circuit schematic in your report. 5. Your report should include all the required measurements. 1.9 Project Guidelines 1. The most common problem is that students show up unprepared for the lab. Make sure that you have thoroughly reviewed laboratory experiment 2 manual, laboratory experiment 5 manual, laboratory experiment 5 biasing supplement, and the laboratory experiment 6 manual. 2. Thoroughly check cables, breadboard, and components to verify that they are known good, and not open or short. 3. Verify that the resistor values are indeed the values that you think that they have. Common mistake is to pick up a 39 KΩ resistor when a 3.9 KΩ is desired. Part of the problem is that resistors may be in the wrong bins. 4. Verify that the transistors are connected correctly. In discrete devices, drain and source terminals are not interchangeable. 5. Verify that their instrumentation is working correctly -- check multi-meters, power supplies, press auto-set on oscilloscope etc. V GS + - + - V DS Figure 1-4: Schematic to determine V th, (µc ox W/L), and I DS for a desired gate overdrive voltage at a desired V DS of each NMOS transistor to be used in amplifier design B. Madhavan Page 5 of 7 EE348L, Spring 2005
6. NMOS transistors in the lab are likely to have large device-to-device V th variation. Use the following procedure in order to determine the V th, (µc ox W/L), and I DS for a desired gate overdrive voltage at a desired V DS of each NMOS transistor to be used in amplifier design: 7. Based on your understanding of the large-signal and smalls-signal analysis of the amplifier to be designed, determine the approximate dc drain-to-source voltage, V DS, of the NMOS transistor that is to be used in the amplifier. 8. Connect the discrete NMOS transistor to be used, as shown in Figure 1-4. Vary V GS from 0V in increments of 0.1V and note down the values of I DS. The value of V GS for which the current, I DS, increases above 0mA is rough approximation of the NMOS transistor s threshold voltage, V th. As in the procedure in laboratory experiment 5 question 1, use excel to plot I DS versus V GS, and determine V th, and (µc ox W/L) of the particular device under consideration, by approximating the plot of I DS versus V GS for data points corresponding to the device being in saturation (V GS > V th, V DS > V GS - V th ). Assume that the channel length modulation is negligible, i.e., λ=0 9. Based on your understanding of the laboratory experiment 5 biasing supplement, determine the NMOS transistor source voltage, V s, to get the desired gain. 10. Based on your understanding of the large-signal and smalls-signal analysis of the amplifier to be designed, determine the approximate gate-source overdrive voltage, V OV, of the NMOS transistor that is to be used in the amplifier. The choice of gate-overdrive voltage is that required to ensure that the gate-source voltage drop is above threshold under all conditions of input transient signal swing. Use the information of V th, and (µc ox W/L) obtained from your excel plot above to determine the drain-to-source current, I DS, corresponding to the desired V OV = V GS -V th. This will lead to the determination of the resistors R D and R SS, to be connected to the drain and source terminals respectively of the NMOS transistor in the common-source amplifier configuration with source degeneration resistor, as shown in Figure 1-5. V dd R D M 1 V D V G + V S - R SS Figure 1-5: Schematic to determine final, operating-point of NMOS transistor common-source amplifier. Biasing resistors are determined after the final value of V G is determined. 11. To determine the gate bias voltage of the common-source amplifier, connect the NMOS transistor in the common-source amplifier configuration as shown in Figure 1-5, with the source-degeneration resistor to ground and the drain load resistor to the supply voltage. Do not connect biasing resistors to the gate terminal. Connect a dc supply, V G, to the gate terminal. Set V G close to the expected value based on your design choice of V s and your calculation of V th. Connect a multi-meter to the source and drain terminals of the NMOS transistor so that you can determine V DS and I DS of the NMOS transistor in the commonsource amplifier configuration. Adjust V G to get the final, desired dc-operating point of V GS, V DS, and I DS. B. Madhavan - 6 of 7- EE348L, Spring 2005
12. The biasing network can be determined once the dc-operating point of the NMOS transistor in the amplifier has been determined. Calculate the values of the biasing network resistors, verify the component values of the selected resistors by using a multi-meter, and then connect the resistor biasing-network to the gate terminal. Disconnect the gate power supply. 13. As part of debugging/verification procedure, verify that the terminal voltages of the NMOS transistor are what they are expected to be. 14. Transient signal measurements should be performed only after the above has been done. 15. Dc-coupled cascade of common-source and source-amplifier requires that drain voltage of common-source amplifier biases source-amplifier. This is the important constraint that guides biasing of the cascade. 1.10 Revision History This lab project was conceived and verified by Xiong Zhi Lin, EE348L Monday laboratory section TA. B. Madhavan Page 7 of 7 EE348L, Spring 2005