CMOS Analog Design LECTURE NOTES Prof. Dr. Bernhard Hoppe Introduction Prof. Dr. Hoppe CMOS Analog Design 2
Analog Integrated Circuits Design Steps: 1. Definition 2. Implementation 3. Simulation 4. Geometrical description 5. Simulation including the geometrical parasitics 6. Fabrication 7. Testing and verification Prof. Dr. Hoppe CMOS Analog Design 3 Analog Integrated Circuits Design: Tools & Methods: Simulation Design Capture Hand Calculations Bottom Up Flow Prof. Dr. Hoppe CMOS Analog Design 4
Discrete Analog Circuit Design - Using breadboards Integrated Analog Circuit Design - Using computer simulation techniques Prof. Dr. Hoppe CMOS Analog Design 5 Pros and Cons of Computer simulations Advantages: 1. No breadboards required 2. Every node in the circuit is accessible 3. Feedback loops may be opened 4. Modification of the circuit is easy 5. Modification of processes and ambient conditions is possible Prof. Dr. Hoppe CMOS Analog Design 6
Pros and Cons of Computer simulations Drawbacks: 1. Accuracy of models 2. Convergence problems of the simulator: circuit may not converge to a stable operating point 3. Time required to perform simulations of large circuits 4. Use of the computer as a substitute for thinking Prof. Dr. Hoppe CMOS Analog Design 7 The PN junction Prof. Dr. Hoppe CMOS Analog Design 8
PN junction Used for: 1. Insulation purposes 2. Diodes and zeners 3. Basic structure of MOS and Bipolar transistor Prof. Dr. Hoppe CMOS Analog Design 9 Important features for device properties And modelling aspects Depletion region width Depletion region capacitance Reverse bias breakdown voltage Diode equation i D Vs V D Prof. Dr. Hoppe CMOS Analog Design 10
Diode Model: Step function change of impurity concentration => Idealization Prof. Dr. Hoppe CMOS Analog Design 11 Diode Model: Space charge width X d = X n -X p Equilibrium condition: Field forces = Diffusion forces Prof. Dr. Hoppe CMOS Analog Design 12
X d =?, E 0 =?, Φ 0 =? Due to electrical neutrality, the charge on either side of the junction must be equal Thus, qn D X n = qn A X p where q = 1.6 x 10-19 C To calculate the fieldstrength from the charge, Gauss equation: de(x) = qn dx where ε Si = 11.7x8.85x10-14 F/cm Si dielectric constant ε Si Prof. Dr. Hoppe CMOS Analog Design 13 On integration we get the max electric field at the junction, E 0 E 0 = 0 E 0 de = Xp 0 qn A / ε Si dx Therefore, E 0 = -qn X D n = qn X A p εsi εsi Prof. Dr. Hoppe CMOS Analog Design 14
Voltage is found by integrating the electric field, resulting in Φ 0 -V D = -E 0 (X n X p ) 2 where V D = applied external voltage Φ 0 = barrier potential Prof. Dr. Hoppe CMOS Analog Design 15 Barrier potential Φ 0 is given as Φ 0 = (kt / q) ln (N A N D / n i2 ) = (V t ) ln (N A N D / n i2 ) where k = Boltzmann s constant 1.38 x 10-23 J/K n i = intrinsic concentration of silicon 1.45 x 10 10 /cm 3 at 300K V t = 25.9 mv at 300K Prof. Dr. Hoppe CMOS Analog Design 16
Using equations for E 0 and Φ 0 V D, and solving for X n or X p we get X n = ( 2ε Si (Φ 0 V D )N A ) 1/2 qn D (N A +N D ) and X p = - ( 2ε Si (Φ 0 V D )N D ) 1/2 qn A (N A +N D ) Prof. Dr. Hoppe CMOS Analog Design 17 Width of the depletion region X d is given as X d = X n X p = ( 2ε Si(N A + N D) ) 1/2 (Φ 0 -V D ) 1/2 qn A N D Prof. Dr. Hoppe CMOS Analog Design 18
Conclusions: 1. X d is proportional to (Φ 0 -V D ) 1/2 or (- V D ) 1/2 2. If N A >> N D then X d ~ X n 3. If N D >> N A then X d ~ X p 4. Lower doped side determines X d Prof. Dr. Hoppe CMOS Analog Design 19 Depletion charge and depletion layer capacitance: Depletion charge Q j is given as Q j = AqN A X p = AqN D X n Q j = A( 2ε SiqN A N D ) 1/2 (Φ 0 -V D ) 1/2 (N A +N D ) where A is the cross sectional area of the pn junction Prof. Dr. Hoppe CMOS Analog Design 20
Depletion charge and depletion layer capacitance: Magnitude of the electric field at the junction E 0 = ( 2 qn A N D ) 1/2 (Φ 0 - V D ) 1/2 ε Si ( NA +N D ) Prof. Dr. Hoppe CMOS Analog Design 21 Depletion charge and depletion layer capacitance: Depletion layer capacitance C j is given as C j = dq j = A( ε SiqN A N D ) 1/2 (Φ 0 -V D ) -1/2 dv D 2(N A +N D ) = C j0 [1-(V D /Φ 0 )] m Prof. Dr. Hoppe CMOS Analog Design 22
Depletion charge and depletion layer capacitance: where C j0 is capacitance when V D = 0 m is a grading coefficient m = 1/2 => step junction m = 1/3 => linearly graded junction 1/3 <= m <= 1/2 => real junctions (experimental fit) Prof. Dr. Hoppe CMOS Analog Design 23 Plot of the space charge capacitance: Ideal Actual Prof. Dr. Hoppe CMOS Analog Design 24
Example: Calculate X d, X n,x p, E 0, C j0, and C j for V D = -4 V, N A = 5 x 10 15 /cm 3, N D = 10 20 /cm 3, A = 10 µm x 10 µm Temperature = 300 K Prof. Dr. Hoppe CMOS Analog Design 25 Breakdown voltage of a reverse biased diode: BV = ( ε Si(N A + N D) )(E max ) 2 2qN A N D assuming V D > Φ 0 E max is the maximum electric field that can exist across the depletion region For silicon, E max ~ 3 x 10 5 V/cm Prof. Dr. Hoppe CMOS Analog Design 26
Breakdown mechanisms: 1. Avalanche breakdown: Multiplication of carrier concentrations due to collisions of minority carriers with the lattice electrons. It has a negative temperature coefficient. 2. Zener breakdown: Valence band breakdown. It occurs at comparatively lower voltages. It does not depend upon temperature (tunneling effect). Prof. Dr. Hoppe CMOS Analog Design 27 Breakdown mechanisms: Reverse biased current (due to avalanche effect) i RA = Mi R = ( 1 [1- (V R /BV) n ) ] x i R where M = avalanche multiplication factor n = empirical parameter 3 <= n <= 6 i R = normal reverse current Prof. Dr. Hoppe CMOS Analog Design 28
Typical pn junction characteristics: Prof. Dr. Hoppe CMOS Analog Design 29 Voltage-Current relationship of diode: Impurity concentration profile for diffused pn junction: Prof. Dr. Hoppe CMOS Analog Design 30
Voltage-Current relationship of diode: Terminologies: p n0 and n p0 = equilibrium concentrations of the minority carriers in n-type and p-type regions p n (0) = p n0 exp(v D /V t ) is value of the excess concentration at x = 0 n p (0) = n p0 exp(v D /V t ) is value of the excess concentration at x = 0 Prof. Dr. Hoppe CMOS Analog Design 31 Voltage-Current relationship of diode: The total current in an pn junction diode is given as i D = qa ( D pp n0 + D nn p0 )(exp(v D /V t ) L 1) p L n Or i D = I s (exp(v D /V t ) 1) Prof. Dr. Hoppe CMOS Analog Design 32
Voltage-Current relationship of diode: where I s = qa ( D pp n0 + D nn p0 L p L n ) is a constant called the saturation current A = area of the pn junction D p = diffusion constant of holes in n-type semiconductor D n = diffusion constant of electrons in p-type semiconductor L p = diffusion length for holes in n-type semiconductor L p = diffusion length for el in p-type semiconductor Prof. Dr. Hoppe CMOS Analog Design 33 Example: Calculate the saturation current of a pn junction diode with N A = 5 x 10 15 /cm 3, N D = 10 20 /cm 3, A = 1000 µm 2, D n = 20 cm 2 / s, D p = 10 cm 2 / s, L n = 10 µm, L p = 5 µm. Prof. Dr. Hoppe CMOS Analog Design 34
The MOS transistor Prof. Dr. Hoppe CMOS Analog Design 35 N-well technology: Physical structure of an n-mos and p-mos device: Prof. Dr. Hoppe CMOS Analog Design 36
N-well technology: pmos formed within a lightly doped n - material called the N-well nmos formed within a lightly doped p - substrate Both types of transistors are four terminal devices The p-bulk connection is common throughout the integrated circuit and is connected to V ss (the most negative supply) Multiple n-wells can be connected to different potentials (but +ve w.r.t. V ss ) nmos and pmos devices are complementary: nmos equations can be mapped to pmos equations Prof. Dr. Hoppe CMOS Analog Design 37 nmos threshold voltage equation: Cross section of an n-channel transistor with all terminals grounded: Prof. Dr. Hoppe CMOS Analog Design 38
nmos threshold voltage equation: Terminologies: C ox = Area specific oxide capacitance in F/m 2 Φ F = Equilibrium electrostatic potential (Fermi potential) in the semiconductor Φ S = Surface potential of the semiconductor Φ MS = Difference in the work functions between the gate material and bulk silicon in the channel region Q SS = Undesired +ve charge present in the interface between the oxide and the bulk silicon Q b0 = Fixed charge in the depletion region V SB = Substrate bias (V Source -V Substrate ) Prof. Dr. Hoppe CMOS Analog Design 39 nmos threshold voltage equation: Threshold voltage V T consists of following contributions: 1. Φ MS = Φ F (substrate) - Φ F (gate) where Φ F (metal) = 0.6 V 2. [-2Φ F (Q b /C ox )]: voltage required to change the surface potential and offset the depletion layer charge 3. Undesired +ve charge Q SS due to impurities and imperfections at the interface must be compensated by a gate voltage of Q SS /C ox Prof. Dr. Hoppe CMOS Analog Design 40
nmos threshold voltage equation: Summation of the contributions: V T = Φ MS + [-2Φ F (Q b /C ox )] + ( Q SS /C ox ) = Φ MS -2Φ F (Q b0 /C ox ) (Q SS /C ox ) - (Q b -Q b0 ) / C ox The threshold voltage can be rewritten as V T = V T0 + γ [ -2Φ F + V SB - -2Φ F ] where V T0 = Φ MS -2Φ F (Q b0 /C ox ) (Q SS /C ox ) Prof. Dr. Hoppe CMOS Analog Design 41 Body effect coefficient: The body factor, body effect coefficient, or bulk-threshold parameter γ is defined as γ = 2qε Si N A (unit: V 1/2 ) C ox Prof. Dr. Hoppe CMOS Analog Design 42
Sign conventions in threshold voltage equation: n-channel device p type substrate p-channel device n type substrate Parameter + + + + + + + + Φ MS metal n+ Si p+ Si Φ F Q b0, Q b Q SS V SB γ Prof. Dr. Hoppe CMOS Analog Design 43 Example: Calculate the threshold voltage and body factor γ for an n-channel transistor with an n+ silicon gate if t ox = 200 A 0, N A = 3 x 10 16 /cm 3, gate doping N D = 4 x 10 19 /cm 3, surface charge density N SS = 10 10 /cm 2, temperature = 300 K. Prof. Dr. Hoppe CMOS Analog Design 44
Current voltage relation of the MOS transistor: 1. Linear mode: - Sah equation i D = (W/L)µ n C ox [(V GS V T ) (V DS /2)] V DS holds good for (V GS V T ) >= V DS and V GS >= V T 2. Saturation mode: i D = (W/2L)µ n C ox [(V GS V T ) 2 ] holds good for (V GS V T ) <= V DS Prof. Dr. Hoppe CMOS Analog Design 45 Device transconductance parameter: The factor µ n C ox is defined as the device transconductance parameter, given as K = µ n C ox = µ n ε ox / t ox Prof. Dr. Hoppe CMOS Analog Design 46
CMOS device modeling Prof. Dr. Hoppe CMOS Analog Design 47 Pinch-off Saturation: Voltage drop in the channel is constant The Field pulling the electrons from the source remains constant i D remains constant Electrons are injected from the channel into the space charge region => ballistic transport to drain node Prof. Dr. Hoppe CMOS Analog Design 48
How large is the saturation current?: Saturation condition: V DS =(V GS V T ) Saturation current equation: i D = (W/2L)µ n C ox [(V GS V T ) 2 ] holds good for 0 <= (V GS V T ) <= V DS Prof. Dr. Hoppe CMOS Analog Design 49 Output characteristics of the MOSFET for V T = 1V: Prof. Dr. Hoppe CMOS Analog Design 50
Channel length modulation effect: Constant saturation current only for long channel devices i.e. Pinch-off point close to the drain Long channel devices have length L >= 10 µm For lengths shorter than 1 µm, short channel effects are observed Most important effect: Channel length modulation effect Prof. Dr. Hoppe CMOS Analog Design 51 Channel length modulation effect: In reality, the saturation current depends linearly on V DS Modified current equation: i D = (W/2L) µ n C ox [(V GS V T ) 2 (1 + λv DS )] where λ = channel length modulation factor (unit: 1/V) Prof. Dr. Hoppe CMOS Analog Design 52
Transfer characteristics of the MOSFET: i D plotted against V GS for fixed V DS, V T = 2V Prof. Dr. Hoppe CMOS Analog Design 53 Short channel effects: As technology scaling reaches channel lengths shorter than 1 µm, second order effects become significant MOSFETs with L < 1 µm are called short channel devices Main effects: 1. velocity saturation 2. threshold voltage variation 3. hot carrier effect Prof. Dr. Hoppe CMOS Analog Design 54
Review of classical derivation of i D : V DS << V GS and V GS > V T The induced charge at position y and voltage V(y) is Q(y) = C ox [V GS - V(y) - V T ]...(1) Current i D (y) is given by the product of the drift velocity of the carriers V n and the charge Prof. Dr. Hoppe CMOS Analog Design 55 Review of classical derivation of i D : i D = - V n (y)q(y)w...(2) Electron velocity V n ~ E, therefore V n = - µ n E(y) = - µ n dv/dy...(3) Substituting eq.(1) and (3) in (2) and rearranging the terms, we get i D dy = µ n C ox W[V GS - V(y) - V T ] dv...(4) Prof. Dr. Hoppe CMOS Analog Design 56
Review of classical derivation of i D : Integrating eq.(4) along the channel for 0 to L gives i D = (W/L)µ n C ox [(V GS V T ) (V DS /2)] V DS Prof. Dr. Hoppe CMOS Analog Design 57 Velocity saturation effect: Measurements of V n as a function of E The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the channel. A plot of electron drift velocity versus electric field is shown above. Prof. Dr. Hoppe CMOS Analog Design 58
Impact of velocity saturation (first impact): Velocity of electrons as a function of E: V n = µ n E 1 + E/Ec for E < E c V n = V sat for E >= E c where E c is the critical electric field at which velocity saturation occurs Inserting a factor in the equation of i D, we get: i D = K(V DS )(W/L)µ n C ox [(V GS V T ) (V DS /2)] V DS Prof. Dr. Hoppe CMOS Analog Design 59 Impact of velocity saturation (first impact): where 1 K(V DS ) = 1 + V DS /E c L is a SPICE parameter for modeling. For L >> 1 µm, K(V DS ) ~ 1 For short channel devices, K(V DS ) < 1 resulting into smaller i D than expected Prof. Dr. Hoppe CMOS Analog Design 60
Impact of velocity saturation (second impact): Short channel transistors enter the saturation region before V DS = V GS V T Assuming V DS is quite large, V n = V sat i Dsat = V sat C ox W[V GS V T V DSsat ] i Dsat = K(V DSsat )(W/L)µ n C ox [(V GS V T ) (V DSsat /2)] V DSsat Solving for V DSsat we get, V DSsat = K(V GS V T )[(V GS V T )] Prof. Dr. Hoppe CMOS Analog Design 61 Impact of velocity saturation (second impact): For short channel devices, K(V GS V T ) < 1 Two transistors with same W/L and V GS = V DD will have the following characteristics: Prof. Dr. Hoppe CMOS Analog Design 62
A simple model for hand calculations: (1) Velocity saturation occurs abruptly at E = E c V n = µ n E for E < E c V n = V sat = µ n E c for E >= E c (2) V DSsat at which E c is reached is given as V DSsat = LE c = LV sat /µ n (3) Approximate saturation current for a short channel device is given as i Dsat = V sat C ox W[V GS V T V DSsat ] Prof. Dr. Hoppe CMOS Analog Design 63 i D Vs V GS characteristics for long and short channel devices: Two transistors, both with W/L = 1.5 will have the following characteristics: Prof. Dr. Hoppe CMOS Analog Design 64
Threshold voltage variations in long and short channel devices: Long channel nmos: V T = f (technology, source bulk voltage) Short channel nmos: V T = f (technology, source bulk voltage, L, W, V DS ) Prof. Dr. Hoppe CMOS Analog Design 65 Disadvantages of short channel devices: Reduction in gain Cannot switch off properly due to reduction in V T More leakage current in the off condition More dependence on transistor variables Prof. Dr. Hoppe CMOS Analog Design 66
Hot carrier effect: During the last decade, transistor dimensions were scaled down but not the power supply Increase in the field strength causes increase in the kinetic energy of electrons (hot electrons) Some of the electrons become so hot that they can jump over the barriers and tunnel into the oxide Electrons are trapped in the oxide and these additional charges increase V T of the transistors This leads to a long term reliability problem For an electron to become hot, a field strength greater than 10 4 V/cm is needed, which is easily possible for technologies with L < 1 µm Prof. Dr. Hoppe CMOS Analog Design 67 i D Vs V DS characteristics degradation: Hot carrier effect degrades the V-I characteristics of short channel transistors due to extensive usage or aging problem Prof. Dr. Hoppe CMOS Analog Design 68
Process variations: Device parameters vary between different wafer runs and even on the same die!...why? Answers : (1) Variations of process parameters: impurity concentrations oxide thickness diffusion depths (2) Temperature effects due to non uniform conditions: variations in sheet resistances variations in threshold voltages variations in parasitic capacitances Prof. Dr. Hoppe CMOS Analog Design 69 Process variations: (3) Variations in geometry of the devices: limited resolution of the lithographic processes results into variations in W/L ratios for the neighbouring transistors device mismatch in circuits built on the basis of transistor pairs, for ex: differential stages Prof. Dr. Hoppe CMOS Analog Design 70
Transistor typical parameter values: 0.25 µm technology, V DD = 2.5V, Minimum channel length device n-channel device 0.43 0.4 0.65 115 0.06 p-channel device -0.40-0.4-1.0-30 -0.1 Parameter V T0 (V) γ (V 1/2 ) V DSsat (V) K (µa/v 2 ) λ (V -1 ) Prof. Dr. Hoppe CMOS Analog Design 71 Passive components Prof. Dr. Hoppe CMOS Analog Design 72
Passive components for building analog circuits in CMOS technology: MOS technology planar technology Capacitors and resistors are compatible with MOS technology fabrication steps Inductors are not compatible Prof. Dr. Hoppe CMOS Analog Design 73 Capacitors: Used more frequently in analog integrated circuits than in discrete designs Applications: compensation capacitors in amplifiers used in gain determining components in charge amplifiers charge storage devices in switched capacitor filters and digital to analog converters Prof. Dr. Hoppe CMOS Analog Design 74
Desired characteristics for capacitors: Good matching accuracy Low voltage coefficient High ratio of desired capacitance to parasitic capacitance High capacitance per unit area Low temperature dependence Note: Analog CMOS processes meet these criteria, pure digital processes do not! Prof. Dr. Hoppe CMOS Analog Design 75 Types of capacitances in analog CMOS processes: (1) Poly Si / oxide / channel capacitor (MOS cap) - like a gate capacitance of MOS transistor, but n+ implant introduced to form a well between electrodes for this plate capacitor Prof. Dr. Hoppe CMOS Analog Design 76
Types of capacitances in analog CMOS processes: (2) Poly / oxide / poly capacitor - top and bottom plates are made up of poly silicon Prof. Dr. Hoppe CMOS Analog Design 77 Types of capacitances in analog CMOS processes: (3) Metal 3 / oxide / metal 2 capacitor - structure similar to the poly 2 / poly 1 capacitor Prof. Dr. Hoppe CMOS Analog Design 78
Types of resistors: (1) Diffused resistor: Prof. Dr. Hoppe CMOS Analog Design 79 Types of resistors: (1) Diffused resistor: - Standard process: sheet resistance is in the range 50 Ω/sq to 150 Ω/sq - Salicided process: surface layer on silicon containing TaSi or TiSi compounds. Sheet resistance is in the range 5 Ω/sq to 15 Ω/sq - Problems: (a) capacitance to n-well (b) voltage coefficient 100...250 ppm/v Prof. Dr. Hoppe CMOS Analog Design 80
Types of resistors: (2) Polysilicon resistor: Prof. Dr. Hoppe CMOS Analog Design 81 Types of resistors: (2) Polysilicon resistor: - surrounded by a thick oxide layer - sheet resistance is in the range 30 Ω/sq to 200 Ω/sq, depending on doping levels - Polysilicide process: sheet resistance is around 10 Ω/sq Prof. Dr. Hoppe CMOS Analog Design 82
Types of resistors: (3) N-well resistor: Prof. Dr. Hoppe CMOS Analog Design 83 Types of resistors: (3) N-well resistor: - n-well is not heavily doped, hence the sheet resistance is high in the range 1 kω/sq to 10 kω/sq - Voltage coefficient is very high, so it acts as a good pull up resistor...but not suitable for generating a precise voltage drop Prof. Dr. Hoppe CMOS Analog Design 84
Performance summary of passive components in a 0.8 µm CMOS technology: Component type Range of process values Matching accuracy Temperature coefficient Voltage coefficient MOS cap 2.2 to 2.7 ff/µm 2 0.05 % 50 ppm/k 50 ppm/v Poly-poly cap 0.8 to 1.0 ff/µm 2 0.05 % 50 ppm/k 50 ppm/v M1-M2 cap 0.021 to 0.025 ff/µm 2 1.5 % - - P+ diffusion resistor 80 to 150 Ω/sq 0.4 % 1500 ppm/k 200 ppm/v Prof. Dr. Hoppe CMOS Analog Design 85 Performance summary of passive components in a 0.8 µm CMOS technology: Component type Range of process values Matching accuracy Temperature coefficient Voltage coefficient n+ diffusion resistor 50 to 80 Ω/sq 0.4 % 1500 ppm/k 200 ppm/v Polysilicon resistor 20 to 40 Ω/sq 0.4 % 1500 ppm/k 200 ppm/v N-well resistor 1 to 2 kω/sq? 8000 ppm/k 10,000 ppm/v Prof. Dr. Hoppe CMOS Analog Design 86
Temperature dependence of MOS devices Prof. Dr. Hoppe CMOS Analog Design 87 Temperature dependence of MOS components: Temperature dependence of MOS components important performance characteristic in analog circuit design The temperature behavior of passive components is usually expressed in terms of a fractional temperature coefficient TC F defined as: TC F = 1.dX XdT X can be resistance or capacitance of the passive component. Usually TC F is multiplied by 10 6 and expressed in units of part per million per o C Prof. Dr. Hoppe CMOS Analog Design 88
Temperature dependence of drain current i D of a MOS transistor: Most sensitive parameters in the drain current equation are µ (mobility) and V T (threshold voltage) Due to scattering at thermally induced lattice vibrations, temperature dependence of µ is given as µ = K µ T -1.5 Temperature dependence of V T is approximated as V T (T) = V T (T 0 ) α (T - T 0 ) α = 2.3 mv/ o C and the expression is valid over the range 200-400 K Thus i D decreases with increasing temperature i D 125 o C = 0.7 i D 25 o C Prof. Dr. Hoppe CMOS Analog Design 89 Temperature dependence of reverse biased diode current: When V D < 0, the diode current is given as -i D = I s = qa ( D p p n0 + D n n p0)= qad.(n i ) 2 L p L n L N = KT 3 exp(- V G0 / V t ) where D, L, N are diffusion constant, diffusion length and impurity concentration of the dominant term (either n or p) V G0 = band gap voltage of Si at 300 K (1.205V) V t = thermal voltage kt/q Prof. Dr. Hoppe CMOS Analog Design 90
Temperature dependence of reverse biased diode current: Differentiating with respect to T results in di s /dt = (3KT 3 /T)exp(-V G0 / V t ) + (qkt 3 V G0 /KT 2 )exp(-v G0 / V t ) = 3I S + I S V G0 T TV t The T CF for the reverse diode current is 1 di S = 3 + V G0 I S dt T TV t Reverse diode current doubles for every 5 o C increase Prof. Dr. Hoppe CMOS Analog Design 91 Example: Calculate the T CF for the reverse diode current for 300 K and V t = 0.025 V Prof. Dr. Hoppe CMOS Analog Design 92
Analog CMOS subcircuits Prof. Dr. Hoppe CMOS Analog Design 93 MOS switch: MOS switch a very useful device Analog circuits: the MOS switch is used in multiplexers, modulation and switched capacitor filters Digital circuits: used in transmission gate logic, dynamic latches, etc. MOS transistor as a switch: Prof. Dr. Hoppe CMOS Analog Design 94
Model for a switch: An ideal switch is a short circuit when ON and an open circuit when OFF Equivalent circuit for a voltage controlled non ideal switch: Prof. Dr. Hoppe CMOS Analog Design 95 Model for a switch: V C = control voltage A, B, C = terminals; C being the control terminal r ON r OFF V OS I A, I B I OFF = ON resistance = OFF resistance (very high) = offset voltage between A and B when the switch is ON = leakage currents = offset current when the switch is OFF C A, C B = parasitic capacitances at the terminals to GND C AC, C BC = capacitive coupling between A and B, contribute to the effect called charge feedthrough big problem in MOS switches! Prof. Dr. Hoppe CMOS Analog Design 96
ON resistance of a MOS switch: r ON consists of the series combination of r D, r S and the channel resistance r D, r S parasitic drain and source resistances (~ 1Ω) r channel channel resistance (~ 50Ω)...dominant! Expression for small-signal channel resistance: r ON = 1 L = di D /dv DS Q K W(V GS -V T -V DS ) where Q designates the quiesent point of the transistor Prof. Dr. Hoppe CMOS Analog Design 97 Range of voltages at the terminals of a MOS switch compared to the gate (control) voltage: nmos: V G larger than the source to drain voltage to switch the transistor ON (atleast higher by V T ) pmos: V G has to be less than the source to drain voltage to switch the transistor ON nmos: Bulk has to be connected to the most negative voltage pmos: Bulk has to be connected to the most positive voltage Consider nmos switch: V G = V DD, V Bulk = V SS, then the transistor is ON until V DD V T >= V BA = V SD Prof. Dr. Hoppe CMOS Analog Design 98
Single stage amplifiers Prof. Dr. Hoppe CMOS Analog Design 99 Applications of CMOS amplifiers: Analog applications: - to overcome noise - to drive a next stage - used in feedback systems - to provide logic levels for interfacing to digital circuits Digital applications: - to drive a load Prof. Dr. Hoppe CMOS Analog Design 100
Basic notions: Generalised system transfer curve: x may be current or voltage y(t) = α 0 + α 1 x(t) + α 2 x 2 (t) +... + α n x n (t) for x1 <= x <= x2 In a narrow range of x, y can be approximated with a linear relationship: y(t) ~ α 0 + α 1 x(t) where α 0 = operating point α 1 = linear (small signal) gain Prof. Dr. Hoppe CMOS Analog Design 101 Basic notions: If α 1 x(t) << α 0, then the operating point OP is very slightly disturbed and linearization around OP is possible small signal analysis y = α 1 x : linear relationship between increments of input and output If x(t) varies over a large range, then the higher order terms become important large signal analysis If the slope of the characteristics varies with the signal - Nonlinearity Prof. Dr. Hoppe CMOS Analog Design 102
Competing design targets for amplifiers: 1. Gain 2. Speed 3. Power consumption 4. Supply voltage 5. Linearity 6. Noise 7. Maximum voltage swing at the output 8. Input and output impedance Prof. Dr. Hoppe CMOS Analog Design 103 Amplifier design octagon: - Several targets...and complex dependencies! Prof. Dr. Hoppe CMOS Analog Design 104
Digital circuit design targets: Three targets: - die size - speed - power consumption Prof. Dr. Hoppe CMOS Analog Design 105 CMOS amplifiers Prof. Dr. Hoppe CMOS Analog Design 106
Basic principles: MOSFET translates variations in its gate-source voltage to a small signal drain current If a resistive load is used, these current variations in turn produce variations in the output voltage Prof. Dr. Hoppe CMOS Analog Design 107 Amplifier configurations: 1. Common source stage (CS) 2. Source follower or common drain stage (SF) 3. Common gate stage (CG) 4. Cascode stage: cascade of CS and CG stage 5. Differential amplifiers Prof. Dr. Hoppe CMOS Analog Design 108
Common source amplifier configuration (CS): Small signal model for the saturation region: Prof. Dr. Hoppe CMOS Analog Design 109 Input output characteristics: 1. V in < V TH : V out = V DD 2. V in >= V TH : M1 is ON saturation region 3. V in >= V out + V TH : M1 in linear region Prof. Dr. Hoppe CMOS Analog Design 110
Input output characteristics: 1. V in < V TH : V out = V DD 2. V in >= V TH : V out = V DD R D 1 2 µ n C ox W L ( ) 2 V in V TH 3. V in >= V out + V TH : V out = V DD R D 1 2 µ n C ox W L 2 [ 2( in TH ) out out ] V V V V Prof. Dr. Hoppe CMOS Analog Design 111 Supressing short channel effects: Analog circuits: L min of technology is not utilized. Instead analog circuits use 4...5 times L min For C35 process analog L min ~ 1.5 µm Longer transistor length results in (1) negligible subthreshold current (2) small channel length modulation effect (3) small velocity saturation effect Prof. Dr. Hoppe CMOS Analog Design 112
Deep triode region: If V in is high enough to drive M1 into deep triode region, V out << 2(V in -V TH ) and from the equivalent circuit V out = V DD = 1 + µ on R R + on R n C ox D V W R L DD D ( ) V in V TH Prof. Dr. Hoppe CMOS Analog Design 113 Small signal gain: In deep triode region, we have a voltage divider while in the saturation region we have the proper amplifier operation: V out = V DD R D 1 2 µ n C ox W L The small signal gain is given as: A ν V = V = R out in D µ n = g m R D C ox W L ( ) 2 V in V ( ) V in V TH TH Prof. Dr. Hoppe CMOS Analog Design 114
Transconductance g m : Small signal parameter In saturation, g g m m ID = VDS fixed Vin W = µ n Cox ( VGS VTH) L W 2ID = 2µ ncox I = D L VGS V = f VGS VTH ( ) TH Prof. Dr. Hoppe CMOS Analog Design 115 Transconductance g m : Thus transconductance g m is dependent on input voltage! Gain Aν varies with Vin...Nonlinearity problem for large signals! Prof. Dr. Hoppe CMOS Analog Design 116
How to maximize the voltage gain? W VRD Aν = 2 µ n Cox ID L ID Where V RD is voltage drop across load resistance A ν = W V 2 µ n Cox L I To increase the gain: - make W/L larger -make V RD large... make R D large -make I D smaller (make transistor weaker) RD D Prof. Dr. Hoppe CMOS Analog Design 117 Trade-offs in maximizing the voltage gain: Larger W/L larger input capacitance Larger V RD smaller output swing If V RD is kept constant I D has to be made smaller R D must be increased higher time constants at the output! Trade-off: gain, BW, voltage swing! Prof. Dr. Hoppe CMOS Analog Design 118
Trade-offs in maximizing the voltage gain: For large values of R D, the effect of channel length modulation in M1 becomes significant V out V V = V out in DD = R R R 1 µ 2 C ox Using the approximation D D I µ 1 2 D D n C µ n ox C n W L ox W L 2 ( ) ( 1+ λ ) V in V TH ( )( 1+ λ ) W L V in V TH ( ) V in V TH 2 V V λ V out out in V out ( 1 2) µ C ( W L)( V ) 2 n ox V in TH Prof. Dr. Hoppe CMOS Analog Design 119 Trade-offs in maximizing the voltage gain: We obtain: A Hence A ν ν = R g R I λa D gmr D = 1+ R λi λ m D D D D Thus decreases the amplification factor! ν Prof. Dr. Hoppe CMOS Analog Design 120
Small signal model for channel length modulation: gmr D Aν = 1+ R λi D D λi D =1 r O ror D = gm r + R Since, A ν O D Prof. Dr. Hoppe CMOS Analog Design 121 Intrinsic gain: Intrinsic gain = upperbound of the overall gain Ideal current source infinite impedance lim R A ν D = g, A m r O ν = g m r ro R D O results in + 1 Todays technology: g m r O is between 10 to 30 Prof. Dr. Hoppe CMOS Analog Design 122
CS stage with diode connected load: In MOS technology, resistors are complicated to implement Hence active loads or so called diode connected transistors are used MOSFET acts as small signal resistor when gate and drain is shorted Diode connected transistors are always in saturation because V DS = V GS Prof. Dr. Hoppe CMOS Analog Design 123 Small signal equivalent circuit: As V DS = V GS V 1 = V X V X I X = + ro g m V Impedence X 1 g m r O g 1 m Prof. Dr. Hoppe CMOS Analog Design 124
Active load with body effect: X ( g + g ) I = V + m mb X V r X O Prof. Dr. Hoppe CMOS Analog Design 125 Active load with body effect: Impedance = V I X X = g m + g 1 mb + 1 r O = g m 1 + g mb r O g m 1 + g mb Thus the body effect reduces the impedance! Prof. Dr. Hoppe CMOS Analog Design 126
Voltage gain of CS stage with diode connected load: For negligible λ, A ν = g m1 g = g m1 m2 1 gm2 + gmb2 1 where η = 1+ η g g mb2 m2 Considering device dimensions, A ν = 2 µ 2 µ n n C C ox ox ( W L) 1ID1 1 ( W L) I 1+ η 2 D2 Prof. Dr. Hoppe CMOS Analog Design 127 Voltage gain of CS stage with diode connected load: Since I = I, D1 D2 A ν = ( W L) 1 1 ( W L) 1+ η 2 Prof. Dr. Hoppe CMOS Analog Design 128
CS stage with diode connected load Large signal analysis: 1 2 I = I µ D1 n C ox W L 1 D2 W L 1 2 ( V V ) = µ C ( V V V ) 2 in TH1 Note: If V TH2 depends only slightly on V out (weak body effect), then we have a linear behavior and Vout is proportional to V in 1 2 n ox W L ( V V ) = ( V V V ) in TH1 W L 2 DD 2 out DD TH2 out TH2 Prof. Dr. Hoppe CMOS Analog Design 129 CS stage with diode connected load Large signal analysis: Differentiating both sides w.r.t V in W W Vout V = L 1 L 2 Vin Vin With application of the chain rule V TH2 VTH2 Vout Vout = = η Vin Vout Vin Vin we get A ν V = V out in = ( W L) 1 1 ( W L) 1+ η The result matches with the small signal analysis! Prof. Dr. Hoppe CMOS Analog Design 130 2 TH2
Input / output characteristics of active load CS stage: At point A, M1 enters the triode region (strong nonlinearity!) Above V TH1 and below V A, (linear behavior) V out V in Prof. Dr. Hoppe CMOS Analog Design 131 CS stage with pmos active load: To improve amplification we use CS stage with pmos active load pmos output node can charge upto full VDD...more voltage swing! No body effect η = 0 A ν = µ µ n ( W L) W L 1 p ( ) 2 Gain depends very weakly on device dimensions Prof. Dr. Hoppe CMOS Analog Design 132
Source follower: CS stage has a good voltage gain, but load impedance has to be high If the load impedance is low, a buffer is needed for impedance matching Prof. Dr. Hoppe CMOS Analog Design 133 Source follower: Source follower (or common drain stage ) may operate as a voltage buffer Prof. Dr. Hoppe CMOS Analog Design 134
Source follower input/output characteristics: Vout follows V in with a voltage difference (level shift) equal to V GS 2 out = µ ncox ( Vin VTH Vout ) R S V 1 2 W L Prof. Dr. Hoppe CMOS Analog Design 135 Small signal gain (large signal analysis): V out in = 1 2 µ n C ox W L 2 ( Vin VTH Vout ) R S Differentiating both sides w.r.t. V in Vout 1 W = µ ncox 2 V 2 L V TH Vout since = η Vin Vin W µ C V V V n ox in out = L V W in 1+ µ ncox Vin V L V V TH out ( Vin VTH Vout ) 1 R S Prof. Dr. Hoppe CMOS Analog Design 136 ( V ) R ( V ) R ( 1+ η) TH TH out out S S in V V in
Small signal gain (large signal analysis): W With g ( ) we get: m = µ ncox Vin VTH Vout L A ν = 1+ g m R S ( gm + gmb ) R S Prof. Dr. Hoppe CMOS Analog Design 137 Small signal gain (small signal analysis): since V in V V 1 bs = V out = V out Prof. Dr. Hoppe CMOS Analog Design 138
Small signal gain (small signal analysis): Vout g m1v1 gmb1vout = R A = ν A ν V V = 1+ out in will result in ( gm + gmb ) R S Maximum possible gain = 1 g m R S S Prof. Dr. Hoppe CMOS Analog Design 139 Drawback of R S implemented as ohmic resistor: I D1 depends strongly on input DC level If V in changes from 1.5 to 2.0 V (10 % increase) then I D1 increases by a factor of 2 Hence V GS V TH increases by 2 highly non linear I/O characteristics! Improvement: instead of R S we take a constant current source M2 to get a linear behavior Prof. Dr. Hoppe CMOS Analog Design 140
Output impedance of SF with constant current source as load: V = 1 V X IX gmvx gmbvx = 0 Prof. Dr. Hoppe CMOS Analog Design 141 Output impedance of SF with constant current source as load: VX 1 Hence = R out = I g + g X m Note: Body effect decreases the output resistance of the source follower! mb Prof. Dr. Hoppe CMOS Analog Design 142
Example: Source follower: W/L = 20µm/0.5µm V TH0 = 0.6 V 2Φ F = 0.7 V µ n C ox = 50 µa/v 2 γ = 0.4 V 2 I 1 = 200 µa Q1: What is V out for V in = 1.2 V? Q2: If I 1 is produced by an nmos device, what is the minimum W/L ratio for which M2 remains saturated? Prof. Dr. Hoppe CMOS Analog Design 143 Solution A1: V TH depends on V out Iterative solution: (1) we calculate V out for V TH0 (2) we calculate V TH for V out obtained in (1) I D = 1 2 µ n C ox W L ( V V V ) in TH out ( 1.2 0.6 V ) out ( V V V ) 2 2 2 = in TH 2ID = W µ ncox L 2*200µ A 50µ A*40 Prof. Dr. Hoppe CMOS Analog Design 144 out
Solution A1: V out = 0.153 V Now, V ( 2φF + VSB φf ) ( 0.7 + 0.153 0.7 ) TH = VTH0 + γ 2 V TH = 0.6 + 0.4 = 0.635 V Using the new V TH the improved value of V out is 0.119 V, which is approximately 35 mv less than the calculated value. Prof. Dr. Hoppe CMOS Analog Design 145 Solution A2: Consider transistor in place of current source: Drain-source voltage of M2 is 0.119 V Device is saturated only if V GS V TH < 0.119 V In the saturation region we have, I 1 W ( 0. ) 2 D = 200 µ A = µ ncox 119 2 L 2 W L 283 µ m = 0.5 m 2 min µ Prof. Dr. Hoppe CMOS Analog Design 146
Drawbacks of the SF configuration: Source followers exhibit a high input impedance and a moderate output impedance, but at the cost of two drawbacks: (1) nonlinearity (2) voltage headroom limitation Prof. Dr. Hoppe CMOS Analog Design 147 Nonlinearity of the SF configuration: Even with an ideal current source I 1 the I/O characteristics display a nonlinearity due to the dependence of V TH on V source Submicron technology: r O of the transistor also changes with V DS additional nonlinear effects! Nonlinearity due to body effect can be eliminated if the bulk is tied to the source Because all nmos devices have a common bulk potential, this is only possible for pmos devices in a n-well technology Prof. Dr. Hoppe CMOS Analog Design 148
Nonlinearity of the SF configuration: pmos source follower with no body effect: Price paid: PFET have a lower carrier mobility leading to higher output impedance than for a nmos source follower Prof. Dr. Hoppe CMOS Analog Design 149 Voltage headroom limitation of SF: Source followers shift the level of the signal by V GS consuming voltage headroom and hence limiting the voltage swing Prof. Dr. Hoppe CMOS Analog Design 150
Voltage headroom limitation of SF: Without source follower: V min at node X is V GS1 V TH1 for having M1 in saturation With the source follower: V min at node X should be greater than V GS2 + (V GS3 V TH3 ) so that M3 is in saturation For same overdrive voltages in M1 and M3, voltage swing allowable at X is reduced by V GS2 Prof. Dr. Hoppe CMOS Analog Design 151 Common gate stage (CG): Prof. Dr. Hoppe CMOS Analog Design 152
Common gate stage (CG): Input is applied to the source terminal and output is taken at the drain terminal Gate is connected to a dc voltage to establish proper operating conditions Bias current may flow directly through the input signal source direct coupling M1 can be biased by a constant current source, with the signal capacitively coupled to the circuit capacitive coupling Prof. Dr. Hoppe CMOS Analog Design 153 Direct coupling Large signal analysis: Assume that V in decreases from a large positive value V in >= V b V TH : M1 is off and V out = V DD For lower values of V in : M1 goes into saturation I D 1 = µ 2 n C ox W L ( V V V ) 2 b in As V in decreases, so does V out, eventually driving M1 into the triode region if V DD 1 µ 2 n C ox W L TH 2 ( Vb Vin VTH ) R D = Vb VTH Prof. Dr. Hoppe CMOS Analog Design 154
CG input output characteristics: If M1 is saturated, output voltage can be expressed as: V out = V DD 1 2 µ n C ox W L 2 ( Vb Vin VTH ) R D Prof. Dr. Hoppe CMOS Analog Design 155 CG stage small signal gain: Small signal gain can be obtained by differentiating w.r.t. V in V V out in = µ V n C ox V W L = η TH ( Vb Vin VTH ) 1 R D = V V Since, we have V V out in A ν = µ = g TH n m C ox in W L R D ( 1+ η) R D TH SB Gain is positive! V V ( V V V )( 1+ η) b in TH in Prof. Dr. Hoppe CMOS Analog Design 156
CG stage input impedance: For λ = 0, the impedance seen at the source of M1 is like in the case of source follower g m 1 1 = + g g 1 mb m ( + η) Thus, the body effect decreases the input impedance! Prof. Dr. Hoppe CMOS Analog Design 157 Cascode stage: Cascade of a common source and a common gate stage is called a cascode stage M1 generates small signal drain current proportional to V in M2 routes this current to R D M1 is the input device M2 is the cascode device M1 and M2 carry the same current Prof. Dr. Hoppe CMOS Analog Design 158
Cascode stage bias conditions: M1 is saturated if V X >= V in V TH1 To keep M1 and M2 both in saturation, V X = V b V GS2 Hence, V b V GS2 >= V in V TH1 Or V b = V in + V GS2 V TH1 M2 in saturation V out >= V b V TH2 Hence V out >= V in V TH1 + V GS2 V TH2 If V b is chosen to keep M1 at the edge of saturation, minimum output voltage for which both transistors operate in saturation is equal to the overdrive voltage of M1 plus that of M2 Prof. Dr. Hoppe CMOS Analog Design 159 Voltages in cascode stage: Prof. Dr. Hoppe CMOS Analog Design 160
Cascode stage large signal analysis: V in = 0 V V out = V DD V in < V TH1 M1 and M2 are off V out = V DD V X = V b V TH2 V in >= V TH1 M1 is on V in sufficiently large V out drops as M1 draws current V GS2 increases as I D2 increases hence V X drops V X drops below V in by V TH1 - M1 enters triode region V out drops below V b by V TH2 - M1 and M2 are in triode region Prof. Dr. Hoppe CMOS Analog Design 161 Cascode stage large signal analysis: Main advantages of cascode structure: - high output impedance - high voltage gain proportional to g 2 m Prof. Dr. Hoppe CMOS Analog Design 162
Cascode stage small signal equivalent circuit: Prof. Dr. Hoppe CMOS Analog Design 163 Cascode stage output impedance: The circuit can be viewed as a common-source stage with a resistor r O 1 Prof. Dr. Hoppe CMOS Analog Design 164
Cascode stage output impedance: Using the equation of output resistance for common source stage, ( 1+ ( g m2 + g mb2 ) ro2 ) ro1 ro 2 R out = + g m r O >> 1 R g + g r r Assuming, we have out ( m2 mb2 ) O2 O1 M2 boosts the output impedance of M1 by a factor of g + g r!! ( m2 mb2 ) O2 Prof. Dr. Hoppe CMOS Analog Design 165 Cascode stage voltage gain: Voltage gain of a cascode stage is given as: A = g g + g r r ν m1 ( m2 mb2 ) O2 O1 The maximum voltage gain is roughly equal to the square of the intrinsic gain of the transistors High output impedance of the cascode stage results in a high voltage gain! Prof. Dr. Hoppe CMOS Analog Design 166
Current sources Prof. Dr. Hoppe CMOS Analog Design 167 Practical current source: For an ideal current source and I out is constant for all output voltages Normally is finite and I out = f(v out ) r O r O = Prof. Dr. Hoppe CMOS Analog Design 168
Requirements of a good performance current mirror: The current-ratio is precisely set by the aspect-ratio (W/L) and is independent of temperature Output impedance is very high, i.e., very high R out and very low C out. As a result, the output current is independent of output voltage (DC and AC) Input resistance R in is very low The voltage compliance is low, i.e., the minimum output voltage V out, for which the output acts as a current source, is low Prof. Dr. Hoppe CMOS Analog Design 169 Basic current mirror: M1 is diode connected transistor which is always in saturation I D1 is mirrored into transistor M2 Prof. Dr. Hoppe CMOS Analog Design 170
Basic current mirror: Since V GS1 = V GS2 and if W L 1 2 ID1 ID2 1 L2 provided the channel length modulation effects are very small I I D1 D2 = 1 2 1 µ n = µ 2 n C C ox ox W1 L1 W L 2 2 Since V GS1 = V GS2, W/L ratios determine D2 2 1 = I D2! = W ( V V ) 2 GS1 TH ( V V ) 2 I I GS2 D1 TH W L W L 1 2 = Prof. Dr. Hoppe CMOS Analog Design 171 Basic current mirror: OR where I = out I REF ( W L) 2 IREF ( W L) = I D1 = 1 V DD V R What is the minimum voltage across M2 such that M2 remains in saturation? - out min GS2 TH What is the output resistance? 1 1 1 where λ is channel - ro2 = = = length modulation factor Prof. Dr. Hoppe CMOS Analog Design 172 GS V = V = V V = V g m2 λi out λi D2 D V DS2 SS
Basic current mirror design example: 5 design variables: L 1, W 1, L 2, W 2, and R = f(v GS ) If we test 10 values per design parameter per simuation, then we need 10 5 simulations! Strategy: step (1): Select a common channel length such that λ is very small L 1 = L 2 = L I I D1 D2 W1 = W λ = f(l) should be as small as possible therefore L >> L min Note: For AMS CSD L analog = 1 µm 2 Prof. Dr. Hoppe CMOS Analog Design 173 Basic current mirror design example: step (2): Select V GS V GS is chosen close to V TH in order to have reasonable currents in large devices V GS V TH = V is overdrive or excess voltage n-channel device 0.5 0.58 175 0.06 p-channel device -0.65 0.42 60 0.06 Parameter V TH (V) γ ( V ) 1 2µ C µ ox 2 ( A V ) λ (1/V) for L = 1µm Prof. Dr. Hoppe CMOS Analog Design 174
Basic current mirror design example: For a reasonable overdrive voltage say, V = 0.2V, we get V GS = V TH + V = 0.7 V step (3): Calculate R R = V DD V I GS D1 V SS For example: to design a current mirror I D1 = I D2 = 10 µa the required R can be calculated as 3.3 0.7 0 2.6 R = = = 260 kω 10 µ A 10 µ A Prof. Dr. Hoppe CMOS Analog Design 175 Basic current mirror design example: How to implement R = 260 kω? sheet resistance: N-well: 1 kω per square NDIFF: 180 Ω per square PDIFF: 160 Ω per square Note: On-chip resistance of such a high value is not possible to implement. To overcome this we usually use externally connected resistances to the IC pins step (4): Calculate W 1 and W 2 1 W1 µ A I 1 = µ ncox * 0.7 0.5 2 2 L1 V 175 µ A 1 *0.04 2 V 1µ m 2 ( ) = 10 A D µ 2 W ( V )* = 10 A 2 µ Prof. Dr. Hoppe CMOS Analog Design 176
Basic current mirror design example: W 2 1 = W = 2.85 µ m 3 µ m step (5): Calculate V min QV V V V DS2 GS TH min = Vout = V = 0.2 V Note: Thus, the minimum output voltage = overdrive voltage selected by the designer step (6): Calculate r out r out = 1 1 = = 1.67 Ω λi 0.06 (1 V)*10 µ A M D2 Prof. Dr. Hoppe CMOS Analog Design 177 Basic current mirror design example: Prof. Dr. Hoppe CMOS Analog Design 178
Cascode curent mirrors: In practice, channel length modulation effect results in significant error in copying currents While V DS1 = V GS1 = V GS2, V DS2 may not equal V GS2 because of the circuitry fed by M2 In order to suppress the effect of channel length modulation, a cascode current source can be used Prof. Dr. Hoppe CMOS Analog Design 179 Cascode curent mirrors: If V b is chosen such that V Y = V X, then I out closely tracks I REF This is because the cascode device shields the bottom transistor from variations in V p Thus, we say that V Y remains close to V X and hence I D2 = I D1 with high accuracy Prof. Dr. Hoppe CMOS Analog Design 180
Cascode curent mirrors: How do we generate V b? Since the objective is to ensure V Y = V X, we must guarantee V b V GS3 = V X or V b = V GS3 + V X This result suggests that if a gate source voltage is added to V X, the required value of V b can be obtained The idea is to place another diode connected device M0 in series with M1, thereby generating a voltage V N = V GS0 + V X Prof. Dr. Hoppe CMOS Analog Design 181 Cascode curent mirrors: Proper choice of the dimensions of M0 w.r.t. M3 yields V GS0 = V GS3 Connecting node N to the gate of M3 we have V GS0 + V X = V GS3 + V Y If the transistor dimensions are properly matched, then we get V X = V Y This result holds even if M0 and M3 suffer from body effect Prof. Dr. Hoppe CMOS Analog Design 182