PD -95487 Typical Applications 42 Volts Automotive Electrical Systems Electrical Power Steering (EPS) Integrated Starter Alternator Lead-Free Benefits Ultra Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Automotive [Q0] Qualified Description Specifically designed for Automotive applications, this Stripe Planar design of HEXFET Power MOSFETs utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings HEXFET Power MOSFET Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 42 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 00 A I DM Pulsed Drain Current 570 P D @T C = 25 C Power Dissipation 380 W Linear Derating Factor 2.5 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 250 mj I AR Avalanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.2 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting Torque, 6-32 or M3 screw 0 lbf in (.N m) Thermal Resistance AUTOMOTIVE MOSFET G IRF607PbF D S TO-220AB V DSS = 75V R DS(on) = 0.0075Ω I D = 42A Parameter Typ. Max. Units R θjc Junction-to-Case 0.40 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 www.irf.com 06/30/04
IRF607PbF Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 75 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.086 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.00580.0075 Ω V GS = 0V, I D = 85A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = 0V, I D = 250µA g fs Forward Transconductance 79 S V DS = 25V, I D = 85A I DSS Drain-to-Source Leakage Current 20 V µa DS = 75V, V GS = 0V 250 V DS = 60V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 200 V GS = 20V na Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge 20 320 I D = 85A Q gs Gate-to-Source Charge 45 68 nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge 73 0 V GS = 0V t d(on) Turn-On Delay Time 22 V DD = 38V t r Rise Time 30 I D = 85A ns t d(off) Turn-Off Delay Time 84 R G =.8Ω t f Fall Time 86 V GS = 0V Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 7750 V GS = 0V C oss Output Capacitance 230 pf V DS = 25V C rss Reverse Transfer Capacitance 30 ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 5770 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 790 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 420 V GS = 0V, V DS = 0V to 60V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 42 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 570 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 85A, V GS = 0V t rr Reverse Recovery Time 30 200 ns T J = 25 C, I F = 85A Q rr Reverse RecoveryCharge 690 040 nc di/dt = 00A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Starting T J = 25 C, L = 0.2mH R G = 25Ω, I AS = 85A, V GS =0V (See Figure 2). ƒ I SD 85A, di/dt 30A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. 2 www.irf.com
I D, Drain-to-Source Current (A) IRF607PbF 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH Tj = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 75 C 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 75 C T J = 25 C V DS= 25V 20µs PULSE WIDTH 4.0 5.0 6.0 7.0 8.0 9.0 0.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 42A 2.5 2.0.5.0 0.5 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) IRF607PbF 2000 0 8000 6000 4000 2000 0 Ciss Coss Crss V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 0 00 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 85A V DS = 60V V DS = 37V V DS = 5V FOR TEST CIRCUIT SEE FIGURE 3 0 0 00 200 300 400 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 75 C T J = 25 C V GS = 0 V 0. 0.2 0.6.0.4.8 2.2 V SD,Source-to-Drain Voltage (V) 0 00 0 Tc = 25 C Tj = 75 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 00µsec msec 0msec 0 00 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
IRF607PbF 60 LIMITED BY PACKAGE V DS R D I D, Drain Current (A) 20 80 40 0 25 50 75 00 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. Fig 0a. Switching Time Test Circuit 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms - V DD Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.00 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th) Gate threshold Voltage (V) IRF607PbF R G V DS 20V V GS tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.0Ω V (BR)DSS 5V DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 3000 2500 2000 500 500 TOP BOTTOM I D 35A 60A 85A 0 25 50 75 00 25 50 75 Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 5.0 V G 4.0 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 3.0 I D = 250µA 2V.2µF 50KΩ.3µF 2.0 V GS D.U.T. V - DS.0-75 -50-25 0 25 50 75 00 25 50 75 200 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage Vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRF607PbF 00 0 Duty Cycle = Single Pulse 0.0 0.05 0.0 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses.0e-07.0e-06.0e-05.0e-04.0e-03.0e-02.0e-0 tav (sec) Fig 5. Typical Avalanche Current Vs.Pulsewidth 400 200 800 600 400 200 0 TOP Single Pulse BOTTOM 0% Duty Cycle I D = 85A 25 50 75 00 25 50 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-005 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2DT/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRF607PbF Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =0V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 7. For N-channel HEXFET power MOSFETs 8 www.irf.com
IRF607PbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - A - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.00) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF00 LOT CODE 789 AS S EMBLED ON WW 9, 997 IN THE AS SEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 997 WEE K 9 LINE C Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q0] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) 252-705 TAC Fax: (30) 252-7903 Visit us at www.irf.com for sales contact information. 06/04 www.irf.com 9
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/