AC : TEACHING DIGITAL FILTER IMPLEMENTATIONS US- ING THE 68HC12 MICROCONTROLLER

AC 2011-549: TEACHING DIGITAL FILTER IMPLEMENTATIONS US- ING THE 68HC12 MICROCONTROLLER Li Tan, Purdue Univerity North Central DR. LI TAN i currently with the College of Engineering and Technology at Purdue Univerity North Central, Wetville, Indiana. He received hi Ph.D. degree in Electrical Engineering from the Univerity of New Mexico in1992. Dr. Tan i a enior member IEEE. Hi principal technical area include digital ignal proceing, adaptive ignal proceing, and digital communication. He ha publihed a number of paper in thee area. He ha authored and co-authored three textbook: Digital Signal Proceing: Fundamental and Application, ElevierAcademic Pre, 2007; Fundamental of Analog and Digital Signal Proceing, Second Edition, AuthorHoue, 2008, and Analog Signal Proceing and Filter Deign, Linu Publication, 2009. Jean Jiang, Purdue Univerity North Central DR. JEAN JIANG i currently with the College of Engineering and Technology at Purdue Univerity North Central, Wetville, Indiana. She received her Ph.D. degree in Electrical Engineering from the Univerity of New Mexico in 1992. Her principal technical area are in digital ignal proceing, adaptive ignal proceing, and control ytem. She ha publihed a number of paper in thee area. She ha co-authored two textbook: Fundamental of Analog and Digital Signal Proceing, Second Edition, AuthorHoue, 2008, and Analog Signal Proceing and Filter Deign, Linu Publication, 2009. c American Society for Engineering Education, 2011 Page 22.1384.1

Teaching Digital Filter Implementation Uing the 68HC12 Microcontroller Abtract We preent our pedagogy for teaching digital filter implementation uing the 68HC12 microcontroller. In the Electrical and Computer Engineering Technology (ECET) curriculum, a microcontroller ha been ued a a popular platform for teaching an embedded ytem coure in the ophomore year. After completing the coure, tudent become familiar with the microcontroller oftware development tool. They are able to program uing aembly and C language, and apply neceary oftware and hardware interface for hand-on application. In fact, mot microcontroller are capable of performing baic digital ignal proceing (DSP) tak uch a digital filtering. Therefore, in thi paper, we firt propoed a imple DSP platform, which conit of the low-cot 68HC12 microcontroller, a ignal condition circuit, and a digital-toanalog converter device for teaching the DSP coure. Uing the propoed DSP platform, we preent our intructional technique for digital filter implementation and related application. Our tudent urvey reult regarding an adoption of the 68HC12 microcontroller for teaching DSP how that the microcontroller i a cot and learning effective tool and can be ued a an alternative when the DSP dedicated hardware i not available. I. Introduction In the Electrical and Computer Engineering Technology (ECET) curriculum, a microcontroller ha been ued a a popular platform for teaching an embedded ytem coure in the ophomore year. After completing the coure, tudent become familiar with the microcontroller oftware development tool. They are able to program uing aembly and C language and apply neceary oftware and hardware interface for hand-on application. In addition, mot microcontroller are capable of performing baic digital ignal proceing (DSP) tak uch a digital filtering. On the other hand, a low-cot DSP olution i preferred in many DSP application. For example, a low ampling rate (100 Hz) i fat enough to proce temperature ignal, light intenity, air preure, mechanical train, or eimic ignal. Meanwhile, a low analog-to-digital (ADC) reolution (8-bit data) in thee application may be ufficient. Hence, an adoption of a low-cot microcontroller intead of a digital ignal proceor with full capability i a cot effective choice. Conidering thee fact, uing a microcontroller for a DSP coure in the junior year could offer the following benefit to ECET tudent: (1) a microcontroller can be an alternative and cot effective olution when a DSP proceor uch a TMS320C67xx i not available; (2) tudent can ave a ignificant amount of time for learning and familiarizing with the new ytem architecture, it correponding development tool and aembly intruction. Intead, they can focu on learning the implementation of digital filter and DSP application; (3) the microcontroller i flexible to ue for variou application including ignal proceing. In thi paper, we preent our pedagogy for teaching digital filter implementation uing the 68HC12 microcontroller. The paper i organized a follow: we firt decribe a imple DSP ytem that conit of the low-cot 68HC12 microcontroller, a ignal condition circuit, and a digital-to-analog (DAC) converter device. A imple program to flexibly et up the ampling rate i then developed and the key aembly intruction for digital filtering are reviewed. Next, we Page 22.1384.2

illutrate the fixed-point data format, finite impule repone (FIR) filter and (infinite impule repone) IIR filter tructure with direct form I and II. After digital filter are deigned by uing MATLAB, real-time FIR and IIR filter implementation are developed uing a linear buffering technique. Finally, we examine tudent urvey regarding adoption of the 68HC12 microcontroller in their DSP coure and dicu the poible improvement baed on the urvey. II. DSP Uing an HC12 Microcontroller A. Hardware Setup and Interface We focu on the development of a imple DSP ytem by uing the 68HC12 microcontroller, which i adopted a a cot and learning effective tool for our DSP coure. The detailed information regarding the 68HC12 microcontroller architecture, interface, and intruction et can be found in the textbook written by D. Pack 1. Figure 1 depict our imple DSP ytem. Analog input ignal ADC channel 6 Range: 0-5 volt Signal conditioning x 68HC12 Microcontroller Output: Sample and hold ignal Range: 0-2.55 volt P-Port y AD557 V in R i R f gain 1 R R f i x AD 6 68HC12 PP 7 PP 6 PP 5 PP 4 PP 3 PP 2 PP 1 PP 0 y Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 AD557 Vout GND GND Vcc CS CE Vout V out Sene A V Sene B out 10 uf Vcc (a) Block diagram. (b) Pin aignment. (c) DSP hardware etup. Figure 1. A imple DSP ytem uing the 68HC12 microcontroller. A hown in Figure 1(a), the propoed DSP ytem conit of the 68HC12 microcontroller, a ignal conditioning circuit, and a digital-to-analog (DAC) unit. Firt, the analog ignal from a enor i conditioned via amplification to fit the voltage range deignated between 0 to 5 volt. Page 22.1384.3

The amplified analog ignal i then fed to the 68HC12 microcontroller via an ADC channel 6 (any other channel can alo be configured) with an 8-bit reolution. The ignal conditioning circuit i a tandard voltage amplifier, which can be eaily deigned uing an Op-Amp circuit [ee Figure 1(b)]. Note that an anti-aliaing low-pa filter i not included, ince the platform need be flexible for variou ampling rate et by internal oftware. The microcontroller procee the converted 8-bit digital value and end the proceed digital output to it 8-bit parallel port. A DAC unit (analog device AD557 circuit) hown in Figure 1(b) applie the 8-bit information and generate a recovered analog ignal. Note that the DAC output i eentially a ample and hold waveform which contain image frequencie. Thee image frequencie can be filtered by a recontruction low-pa filter (alo called the anti-image low-pa filter). Again, a recontruction low-pa filter i not included due to the flexibility requirement for a ampling rate election. The DAC output range i between 0 to 2.55 volt. Figure 1(c) diplay the DSP hardware etup. For lab experiment, an analog input ignal can be produced by a function generator while the analog input and output ignal can be examined via an ocillocope. B. Software Setup Conidering that tudent are familiar with the oftware development tool uch a AxIDE (The detailed information can be found in reference 2 ), aembly and C language, and Motorola 68HC12 intruction et, a imple oftware etup program for real-time ignal proceing depicted in Figure 2 can firt be tudied. clock DAC: y(n) ADC: x(n) DSP Proceing DAC: y(n) ADC: x(n) DSP Proceing t 0 Interrupt ervice routine Interrupt ervice routine T=ampling period T T=ampling period 2T ( ec.) Figure 2. Real-time proce uing the 68HC12 microcontroller. A hown in Figure 2, an interrupt driven application i required and an interrupt ervice routine i executed at the beginning of each ampling period of T econd. During each ampling period, the microcontroller end the proceed digital output y(n) to the DAC unit, perform ADC converion to obtain a new digital input data x(n), and procee the digital input x(n) to produce a digital output y(n). The digital output y(n) will be ent out when the next interrupt i activated. Since the microcontroller ha a low clock rate, aembly coding i required in order to maximize the proceing capability, that i, maximize the uage of machine execution time. For example, if a ampling rate i et up to 8000 Hz, then the ampling period T equal 125 micro econd. Again, ince the 68HC12 microcontroller ha a clock rate of 8 MHz (1 clock tick =18MHz=0.125 micro econd), the maximum number of clock tick for proceing each ample i 1000 (clock cycle). Given the ampling rate, tudent are required to examine execution time available for each filter implementation to enure that the total number of clock tick i within it limit. Figure 3 lit the program egment of ampling, ADC, and DAC converion. Note that the number of tick ued a 1000 can be changed to et a different ampling rate. Uing the machine code information 1, the etup program with a ampling period Page 22.1384.4

of 125 micro-econd lited in Figure 3 take 43 clock tick in total, leaving 957 clock tick for DSP proceing. Of thee 43 clock tick, etting up the interrupt for ampling intant take 22 clock tick, ending a digital output require 6 clock tick, and performing ADC converion cot clock tick. The memory allocation in general i depicted in Figure 4, where data area tart at addre 0x2000 while the program area begin at 0x2100. The data area i deignated between 0x2000 and 0x2100, in which the input buffer, filter coefficient, and output data buffer reide. Beyond the 0x2100 i the program code area, where the executable code reide. Once tudent verify the ampling program, they can begin to change the ampling rate by themelve. At thi tage, uing a function generator to produce an input ine wave, they are able to examine the input and output ignal on an ocillocope. In addition, ince an anti-aliaing low-pa filter i not included in the DSP ytem, tudent are alo able to examine the aliaing effect by inputting a ine wave with it frequency value larger than the Nyquit limit (half of the ampling rate). * data area * #data 0x2000 * ource code area * #code 0x2100 filt_oc2() { #am done LDAA $008E ; ANDA #$04 BEQ done LDD $0094 ADDD #1000 ; et up 8000 Hz ampling rate: T=1000*125 microecond STD $0094 LDAA $008E ORAA #$04 STAA $008E LDAA $2060 ; load the proceed data STAA $0056 ; end the proceed data to Port P and DAC device LDAA #$26 STAA $0065 ; et up the ADC can mode for AN channel 6 wait LDAA $0066 ; tart ADC, and check the completion flag ANDA #$80 BEQ wait ; complete ADC converion LDAA $0074 ; obtain the converted from ADC reultant regiter 2 ; thi area for the DSP algorithm STAA $2060 ; tore the converted data to the output buffer #endam } main() { inita2d(); initoc2(); while(1) { filt_oc2(); } Figure 3. A ample program egment for ampling rate and ADC etup. Page 22.1384.5

$2000 $2001 Data area erved for input data buffer, filter coefficient buffer, and output data buffer $2100 Program area erved for program $20FF Figure 4. Memory allocation for digital filter implementation. C. FIR Filter Implementation Now tudent can begin to implement a finite impule repone (FIR) digital filter deigned uing MATLAB according to the given filter pecification. For example, the following deigned FIR filter i required to be implemented. y( n) 0.0060 0.0493 x( n 1) 0.1733 x( n 2) 0.25 x( n 3) 0.1733 x( n 4) 0.0493 x( n 5) 0.0060 x( n 6) The memory utilization including FIR filter buffer i hown in Figure 5. $2020 $2040 $2060 $2061 $2062 $2063 FIR filter coefficient buffer Input data buffer x(n) Output data buffer y(n) Figure 5. Memory utilization for FIR filter implementation. Each filter i implemented in a fixed-point format 3-5 in which each data contain bit for magnitude and 1 bit for ign bit (Q- format). The 2 complement form i ued for any negative number. The deigned FIR filter coefficient are quantized into 16 bit a following: Page 22.1384.6

b, 0 0.006 2 197 b 1 0.0493 2 16, b 2 0.17331 2 5679, b, 3 0.25 2 8192 b 4 5679, b 5 16, b 6 197 In the program (refer to Figure 4), tudent can enter the quantized filter coefficient in the data area a hown below: -------------------------------------------------------------------------------------------------------- #data 0x2020 int code[7]= {197, 16, 5679, 8192, 5679, 16, 197}; --------------------------------------------------------------------------------------- The FIR filtering require multiplication and accumulation (MAC) operation. Multiplying two 16-bit number (Q- format) will reult in a 31-bit number (Q-30 format). Figure 6 illutrate a fixed-point multiplication uing Q- format. After multiplication, the reult mut be hifted left by 1 bit to form a 32-bit data (Q-31 format). Q- format -bit magnitude Q- format Q- format -bit magnitude x -bit magnitude After MAC operation: Q-30 format 30-bit magnitude After adjutment to Q-31 format by hifting 1 bit to left: Q-31 format 31-bit magnitude 0 Figure 6. MAC operation in Q-format. The filtered output data y(n) i tored tarting at addre 0x2060 with conecutive 4 byte, whoe highet byte will be ent to the parallel port a hown Figure 7. Note that the highet byte i ent out to match the 8-bit ADC reolution. Page 22.1384.7

$2060 $2061 $2062 $2063 Highet byte Lowet byte To P-port Figure 7. Output data byte for DAC. Before coding the digital filtering operation, tudent are intructed to learn how to update input data uing an FIFO buffer (firt in-firt out linear buffering technique) a depicted in Figure 8, where the input buffer ranging from 0x02040 to 0x0204C. New ample x(n) in $2040 $2042 $2044 $2046 $2048 $204A $204C x( n 1) x( n 2) x( n 3) x( n 4) x( n 5) x( n 6) Oldet ample x(n-6) out Figure 8. Input buffer uing FIFO. The digital filtering operation i decribed in Figure 9. A illutrated in the figure, the 68HC12 microcontroller offer a pecial intruction, called EMACS (multiply and accumulate with the multiplier and multiplicand each having 16 bit igned number) operation. The accumulated reult i tored a a 32 bit igned number. Thi intruction require thirteen (13) clock cycle for execution. It ue index X and index Y regiter to hold the addree of multiplier and multiplicand, repectively. The multiplied reult i added to the pecified addre uch a 0x2060 a depicted in Figure 9 and 10. After each EMACS operation, the index regiter mut be increaed four (4) time to fetch the next multiplier and multiplicand for the next EMACS operation until the filtering proceing i completed. Page 22.1384.8

EMACS yntax: [ M(x):M(x+1) ] x [M(y):M(y+1) ] + M~M+3 Initial pointer: $2020 $2022 $2024 $2026 $2028 $202A $202C X=$2020 197 16 5679 8192 5679 16 197 $2040 $2042 $2044 $2046 $2048 $204A $204C Y=$2040 x( n 1) x( n 2) x( n 3) x( n 4) x( n 5) x( n 6) Figure 9. Digital filtering uing the EMACS intruction. Q- format Q- format -bit magnitude x -bit magnitude After EMACS operation: Q-30 format $2060 30-bit magnitude After adjutment to Q-31 format by hifting 1 bit to left: $2060 Q-31 format 31-bit magnitude 0 Add a DC offet $80 to the firt byte: $2060 8 bit data Figure 10. Output data format. Note that a DC offet value of $80 i added to the firt byte (highet byte), ince an ADC557 chip only convert a poitive number. The final 8-bit data at location 0x2060 i now ready to be ent out to the parallel port. Figure 11 lit a program egment. Page 22.1384.9

... ;ampling rate LDAA $2060 ;output filtered data STAA $0056 LDD #$00 ; clear the reult STD $2060 STD $2062 ; done with ADC LDD $204A ;linear buffering STD $204C LDD $2048 STD $204A LDD $2046 STD $2048 LDD $2044 STD $2046 LDD $2042 STD $2044 LDD $2040 STD $2042 LDAA $0074 ;get new input ample LDAB #$00 ADDA #$80 ;ubtract DC offet STD $2040 ;update new ample LDX #$2020 ; the firt coefficient LDY #$2040 ; the firt data ; ; done with filtering LDD $2060 LSLD ;adjut it to Q- format ADDA #$80 ; add DC offet STD $2060 ; tore to output buffer Figure 11. A ample program egment for FIR filter implementation. Page 22.1384.10

After tudying the ample program hown in Figure 11, tudent are required to examine their own code to ee if the execution time i within it limit et by the ampling rate. Then they program the EMACS operation mechanically. Once the program i uccefully implemented, tudent are required to replace the repetition part of the EMACS with a ubroutine and a loop. D. IIR Filter Implementation The infinite impule repone (IIR) filter implementation require more effort. The caling factor mut be incorporated to avoid a poible overflow for each accumulator and a coefficient quantization overflow due to the deigned coefficient value larger than one. An illutrative example i given below: Hz () 0.06747 0.1349z 0.06747 z 1 2 1 1.1429z 0.4128z 1 2 Student are firt required to implement H(z) uing direct form I hown in Figure 12. b 0 C C y(n) x( n 1) z 1 + z 1 b 1 C a a 1 2 C C z 1 z 1 x( n M) z 1 b M C a N C z 1 Figure 12. IIR filter implementation in direct form I. Converting the tranfer function yield the following difference equation: y( n) 0.06747 0.1394 x( n 1 0.06747 x( n 2) 1.1429 y( n 1) 0.4128 y( n 2) Since a coefficient value of 1.1429 i larger than 1, the DSP equation mut be caled down by a factor of 2 to avoid the coefficient quantization overflow. The caled DSP equation are 0.06747 0.1394 0.06747 1.1429 0.4128 y( n) x( n 1 x( n 2) y( n 1) y( n 2) 2 2 2 2 2 y( n) 2 y ( n ) Page 22.1384.11

The quantized coefficient uing 16 bit including a ign bit are lited below: 0.06747 2 1106 2 0.1344 2 2 2210, 1.1429 2 2 18725, 0.4128 2 2 6763, Figure 13 depict the memory and buffer organization. $2020 $2022 $2024 b n 1106 2210 1106 $2030 $2032 a n 18275-6763 Input buffer $2040 $2042 $2044 x( n 1) x( n 2) Pat output buffer y n 1) Output buffer y( n) um $2050 $2052 y(n-1) y(n-2) $2060 $2062 datah datal Output filtered data $2060 8 bit Add a DC offet #$80 P-port Figure 13. Memory arrangement for an IIR filter in direct form I. Page 22.1384.12

Figure 14 illutrate the IIR filter implementation uing linear buffer. Note that both input and output data buffer need to be updated for proceing each input ample. Figure how a ample program egment. Input buffer $2040 $2042 $2044 Subtruct DC offet: ADDA #$80 x( n 1) x( n 2) Output without adding DC offet y( n) $2050 y(n-1) $2052 y(n-2) $2020 $2022 $2024 b n 1106 2210 1106 x x x Input buffer $2040 $2042 $2044 x( n 1) x( n 2) + + $2030 $2032 a n 18275-6763 x x Pat output buffer $2050 $2052 y( n 1) y(n-1) y(n-2) + Output buffer $2060 Q-30 format Shift to left by 1 bit $2060 Q-31 format 0 Figure 14. IIR filter implementation in direct form I. Page 22.1384.13

; ampling rate control LDD $2060 ;output filtered data STAA $0056 ; end y(n) to P-Port LDD #$00 ; clear accumulate STD $2060 STD $2062 ; ADC LDD $2042 ;update the linear buffer for input x(n) STD $2044 LDD $2040 STD $2042 LDAA $0074 ;update ample LDAB #$00 ;clear lower byte ADDA #$80 ; ubtract DC offet =2.5 volt STD $2040 LDX #$2020 ; perform b0x(n)+b1x(n)+b2x(n-2) LDY #$2040 ;done with um of b(n)*x(n) LDX #$2030 ; perform -a1y(n-1)-a2y(n-2) LDY #$2050 LDD $2060; change y(n) in Q- and cale it up by 2 LSLD LSLD ; cale factor ued in quantization STD $2060 LDD $2050 ; update buffer y(n-1) y(n-2) STD $2052 LDD $2060 STD $2050 LDAA $2060 ADDA #$80 ;add DC offet STAA $2060 Figure. A ample program egment for IIR filter implementation in direct form I. Page 22.1384.14

Next, direct form II hown in Figure 16 can be invetigated uing the ame IIR filter tranfer function. 1 S 1 A A w( n) b0 B B S + + a 1 A z 1 b 1 w( n 1) B y( n) a 2 A z 1 b 2 B w( n 2) a M A z 1 b M B w( n M) Figure 16. IIR filter implementation in direct form II. Converting the tranfer function yield the following difference equation in direct form II: w( n) 1.1429 w( n 1) 0.4128 w( n 2) y( n) 0.06747 w( n) 0.1349 w( n 1) 0.06747 w( n 2) To avoid the overflow in the firt equation (correponding to the firt adder), an impule repone equence from it tranfer function can be determined by uing MATLAB a follow: h( n) Z 1 1 1 1.1429z 0.4128z 1 2 The cale factor S hown in Figure 16 i then computed uing the following formula 4 : S h( n ) 4 For thi cae, S=4 i elected. Again, ince the coefficient 1.1429 >1, a cale factor of A=2 i employed to enure all the numerator coefficient in the firt equation are le than 1. B=1 i choen ince all of the coefficient in the econd equation are fraction. Thu, the final implementation equation without coefficient quantization are lited below: Page 22.1384.

Now, quantizing each coefficient lead to 1 x ( n ) 4 input 1 1.1429 0.4128 w ( n) w( n 1) w( n 2) 2 2 2 w( n) 2 w ( n ) y( n) 0.06747 w( n) 0.1349 w( n 1) 0.0647 w( n 2) youtput ( n) 4 y( n ) 1 2 16384 2 1.1429 2 2 18726, 0.4128 2 2 6764 0.06747 2 2211, 0.1349 2 4420 The memory arrangement for input and output data buffer i diplayed in Figure 17. A hown in Figure 17, there are three data buffer: input data buffer, output data buffer, and tate data buffer. Only tate data buffer require the FIFO operation. A detailed implementation i hown in Figure 18.,, $2020 $2022 $2024 Input buffer $2040 b n 2211 4420 2211 State buffer wn ( ) $2042 w( n) $2044 w( n 1) $2046 w( n 2) $2030 $2032 $2034 Output buffer $2060 $2062 a n 16384 18276-6763 yn ( ) um datah datal Figure 17. Memory arrangement for IIR filter implementation in direct form II. Page 22.1384.16

; ampling rate control LDD $2060 ;output the filtered data STAA $0056 LDD #$00 STD $2060 STD $2062 ; done with ADC LDAB $0074 ;update ample LDAA #$00 ADDD #$FF80 ;add DC offet with ign extenion LDY #$0040 ;cale the input x(n) down by 4 (S=4)to avoid overflow emul ;note that A=2 i included in coefficient STD $2040 LDX #$2030 LDY #$2040 ;0.5*x(n) LDY #$2044 ;-a1*w(n-1) ;-a2*w(n-2) LDD $2060 LDY #$0002 ; A=2 emul LSLD ; adjut to Q- STD $2042 ; w(n) LDD #$0 STD $2060 STD $2062 LDX #$2020 ; filtering data LDY #$2042 ;b0*w(n) ;b1*w(n-1) ;done with um of b(n)*w(n) LDD $2044 ;update the linear buffer for w(n) STD $2046 LDD $2042 STD $2044 LDD $2060 LSLD ; change y(n) to Q- LSLD ; cale up by 4, S=4 LSLD ADDA #$80 ;add DC offet STD $2060 Figure 18. A ample program egment for IIR filter implementation in direct form II. Page 22.1384.17

With the etablihed knowledge and ample program, tudent can further conduct their own filter implementation uing their own deigned filter. Finally, a group project can be aigned to tudent to develop more advanced implementation including dual tone multi-frequency (DTMF) tone generation uing IIR filter, FIR filter uing the circular buffering, and ampling rate converion. III. Student Evaluation and Improvement Upon completion of the DSP coure a well a it laboratory experiment, a urvey wa conducted to ak each tudent to evaluate hiher achievement uing the 68HC12 microcontroller a a learning tool. Table 1 how the urvey reult. Note that the rating cale wa baed on the percentage of the overall tudent. Table 1. Student urvey for their achievement. Rating cale Undertanding Tool Excitement of digital filter implementation 4 excellent 85% 90% 80% 3 good % 10% % 2 fair 0% 0% 5% 1 unatified 0% 0% 0% Mot tudent remained excited about lab ince the hand-on real-time lab uing their familiar platform motivated them. Student felt that they can focu on learning filter implementation without putting extra effort to learn the new programming tool and environment. The textbook 4 helped a lot to develop DSP concept uing ample worked numerical example accompanying with handy MATLAB imulation example and program. After learning the digital filter implementation, tudent enhanced their kill in the embedded ytem deign ignificantly o that they could apply their gained knowledge and proficiency into their enior captone project. Our future improvement could include developing more practical project with application of proceing low frequency ignal like intrumentation, vibration, and biomedical ignal. IV. Concluion In thi paper, we have demontrated the feaibility and our pedagogy for teaching a real-time DSP coure uing the 68HC12 microcontroller. We have validated that uing the 68HC12 microcontroller a a platform in our DSP coure i not only cot-effective but alo learning effective. The developed method could be an alternative when the DSP dedicated hardware i not available while offering a DSP coure i in demand. Bibliography 1. D. J. Pack, S. F. Barrett, 68HC12 Microcontroller: Theory and Application. Prentice Hall, 2002. 2. Axiom Manufacturing: http:www.axman.com Page 22.1384.18

3. D. Grover, J. R. Deller, Digital Signal Proceing and the Microcontroller. Prentice Hall, 1999. 4. L. Tan, Digital Signal Proceing: Fundamental and Application. ElevierAcademic, 2007. 5. T. B. Welch, C. H.G. Wright, M. G. Morrow, Real-Time Digital Signal Proceing. CRC Pre, 2006. Page 22.1384.19