Features l Advanced Process Technology l Ultra Low On-Resistance l 175 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. Absolute Maximum Ratings I D @ T C = 25 C HEXFET Power MOSFET V DSS = 40V R DS(on) = 5.5mΩ I D = 75A www.irf.com 1 G TO-220AB IRF4104PbF Parameter Continuous Drain Current, V GS @ 10V (Silicon Limited) D S D 2 Pak IRF4104SPbF IRF4104PbF IRF4104SPbF IRF4104LPbF TO-262 IRF4104LPbF Units I D @ T C = C Continuous Drain Current, V GS @ 10V 84 A I D @ T C = 25 C Continuous Drain Current, V GS @ 10V (Package limited) 75 I DM Pulsed Drain Current c 470 P D @T C = 25 C Power Dissipation 140 W Linear Derating Factor 0.95 W/ C V GS Gate-to-Source Voltage ± 20 V E AS (Thermally limited) Single Pulse Avalanche Energyd 120 mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 220 I AR Avalanche Currentc See Fig.12a, 12b, 15, 16 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) 10 lbfyin (1.1Nym) Mounting Torque, 6-32 or M3 screw i Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.05 C/W R θcs Case-to-Sink, Flat Greased Surface i 0.50 R θja Junction-to-Ambient i 62 R θja Junction-to-Ambient (PCB Mount) j 40 Max. 120 PD - 95468A 07/23/10
IRF4104S/LPbF Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 40 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.032 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 4.3 5.5 mω V GS = 10V, I D = 75A e V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µA gfs Forward Transconductance 63 V V DS = 10V, I D = 75A I DSS Drain-to-Source Leakage Current 20 µa V DS = 40V, V GS = 0V 250 V DS = 40V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 na V GS = 20V Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge 68 I D = 75A Q gs Gate-to-Source Charge 21 nc V DS = 32V Q gd Gate-to-Drain ("Miller") Charge 27 V GS = 10V e t d(on) Turn-On Delay Time 16 V DD = 20V t r Rise Time 130 I D = 75A t d(off) Turn-Off Delay Time 38 ns R G = 6.8 Ω t f Fall Time 77 V GS = 10V e L D Internal Drain Inductance 4.5 Between lead, nh 6mm (0.25in.) L S Internal Source Inductance 7.5 from package and center of die contact C iss Input Capacitance 3000 V GS = 0V C oss Output Capacitance 660 V DS = 25V C rss Reverse Transfer Capacitance 380 pf ƒ = 1.0MHz C oss Output Capacitance 2160 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 560 V GS = 0V, V DS = 32V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 850 V GS = 0V, V DS = 0V to 32V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 75 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 470 integral reverse (Body Diode)Ãc V SD Diode Forward Voltage 1.3 V t rr Reverse Recovery Time 23 35 ns Q rr Reverse Recovery Charge 6.8 10 nc Conditions V GS = 0V, I D = 250µA p-n junction diode. T J = 25 C, I S = 75A, V GS = 0V e T J = 25 C, I F = 75A, V DD = 20V di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 www.irf.com
I D, Drain-to-Source Current ( A) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) Gfs, Forward Transconductance (S) IRF4104S/LPbF 0 V GS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 0 V GS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 10 1 4.5V 20µs PULSE WIDTH Tj = 25 C 0.1 0.1 1 10 V DS, Drain-to-Source Voltage (V) 4.5V 20µs PULSE WIDTH Tj = 175 C 10 0.1 1 10 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 120 T J = 25 C T J = 25 C T J = 175 C 80 60 T J = 175 C 10 40 1 V DS = 15V 20µs PULSE WIDTH 4 6 8 10 12 V GS, Gate-to-Source Voltage (V) 20 0 V DS = 10V 380µs PULSE WIDTH 0 20 40 60 80 I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance Vs. Drain Current www.irf.com 3
C, Capacitance (pf) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) V GS, Gate-to-Source Voltage (V) IRF4104S/LPbF 5000 4000 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 20 16 I D = 75A V DS = 32V VDS= 20V 3000 Ciss 12 2000 8 0 Coss 4 Crss 0 1 10 0 0 20 40 60 80 V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0.0 00 OPERATION IN THIS AREA LIMITED BY R DS (on).0 T J = 175 C 0 10.0 T J = 25 C µsec 1.0 V GS = 0V 0.1 0.2 0.6 1.0 1.4 1.8 V SD, Source-toDrain Voltage (V) 10 1 Tc = 25 C Tj = 175 C Single Pulse 1msec 10msec 0 1 10 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRF4104S/LPbF 120 LIMITED BY PACKAGE 2.0 I D = 75A V GS = 10V 80 1.5 60 40 1.0 20 0 25 50 75 125 150 175 T C, Case Temperature ( C) 0.5-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10. Normalized On-Resistance Vs. Temperature 10 1 D = 0.50 Thermal Response ( Z thjc ) 0.1 0.01 0.001 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) R 1 R 1 R 2 R 2 R 3 R 3 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri 1E-006 1E-005 0.0001 0.001 0.01 0.1 t 1, Rectangular Pulse Duration (sec) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case Ri ( C/W) τi (sec) 0.371 0.000272 0.337 0.001375 0.337 0.018713 www.irf.com 5 τ C τ
V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRF4104S/LPbF V DS L 15V DRIVER 500 400 TOP BOTTOM I D 11A 16A 75A R G 20V V GS tp D.U.T IAS 0.01Ω - V DD A 300 200 Fig 12a. Unclamped Inductive Test Circuit tp V (BR)DSS 0 25 50 75 125 150 175 Starting T J, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V Q GS Q GD 4.0 V G Current Regulator Same Type as D.U.T. Charge Fig 13a. Basic Gate Charge Waveform 3.0 2.0 I D = 250µA 50KΩ 12V.2µF.3µF V GS D.U.T. V - DS 1.0-75 -50-25 0 25 50 75 125 150 175 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRF4104S/LPbF 0 Duty Cycle = Single Pulse 10 0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 140 120 80 60 40 20 0 TOP Single Pulse BOTTOM 1% Duty Cycle I D = 75A 25 50 75 125 150 175 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-5 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRF4104S/LPbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =10V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD 10V Pulse Width 1 µs Duty Factor 0.1 % Fig 18a. Switching Time Test Circuit V DS 90% 10% V GS t d(on) t r t d(off) t f Fig 18b. Switching Time Waveforms 8 www.irf.com
IRF4104S/LPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED ON WW 19, 2000 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead - Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 19 LINE C TO-220AB package is not recommended for Surface Mount Application Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/datasheets/data/auirf4104.pdf 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRF4104S/LPbF D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASS EMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE P = DES IGNAT ES LEAD - F REE PRODUCT (OPTIONAL) YE AR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/datasheets/data/auirf4104.pdf 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ 10 www.irf.com
IRF4104S/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 11
IRF4104S/LPbF D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) 10.90 (.429) 10.70 (.421) 11.60 (.457) 11.40 (.449) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by T Jmax, starting T J = 25 C, L = 0.04mH R G = 25Ω, I AS = 75A, V GS =10V. Part not recommended for use above this value. ƒ Pulse width 1.0ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. This is only applied to TO-220AB pakcage. ˆ This is applied to D 2 Pak, when mounted on 1" square PCB (FR- 4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/2010 12 www.irf.com