l l l l l l Advanced Process Technology Surface Mount (IRFZ44ES) Low-profile through-hole (IRFZ44EL) 75 C Operating Temperature Fast Switching Fully Avalanche Rated PRELIMINARY G PD - 9.74 IRFZ44ES/L HEXFET Power MOSFET D S V DSS = 60V R DS(on) = 0.023Ω I D = 48A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRFZ44EL) is available for low-profile applications. 2 D Pak TO-262 Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 48 I D @ T C = 0 C Continuous Drain Current, V GS @ V 34 A I DM Pulsed Drain Current 92 P D @T C = 25 C Power Dissipation W Linear Derating Factor 0.7 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 220 mj I AR Avalanche Current 29 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.4 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 www.irf.com /8/97
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 60 V V GS = 0V, I D = 250µA DV (BR)DSS /DT J Breakdown Voltage Temp. Coefficient 0.063 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.023 Ω V GS = V, I D = 29A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µA g fs Forward Transconductance 5 S V DS = 30V, I D = 29A I DSS Drain-to-Source Leakage Current 25 V µa DS = 60V, V GS = 0V 250 V DS = 48V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 20V na Gate-to-Source Reverse Leakage -0 V GS = -20V Q g Total Gate Charge 60 I D = 29A Q gs Gate-to-Source Charge 3 nc V DS = 48V Q gd Gate-to-Drain ("Miller") Charge 23 V GS = V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 2 V DD = 30V t r Rise Time 60 I D = 29A ns t d(off) Turn-Off Delay Time 70 R G = 5Ω t f Fall Time 70 R D =.Ω, See Fig. L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 360 V GS = 0V C oss Output Capacitance 420 pf V DS = 25V C rss Reverse Transfer Capacitance 60 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 48 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 92 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 29A, V GS = 0V t rr Reverse Recovery Time 69 4 ns T J = 25 C, I F = 29A Q rr Reverse Recovery Charge 77 266 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 520µH R G = 25Ω, I AS = 29A. (See Figure 2) ƒ I SD 29A, di/dt 320A/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. Uses IRFZ44E data and test conditions ** When mounted on " square PCB ( FR-4 or G- Material ). For recommended soldering techniques refer to application note #AN-994. 2 www.irf.com
I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 75 C V DS= 25V 20µs PULSE WIDTH 4 5 6 7 8 9 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 48A 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 2500 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd 2000 Coss = Cds Cgd C iss 500 C oss 00 500 C rss 0 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 29 V DS = 48V V DS = 30V FOR TEST CIRCUIT SEE FIGURE 3 0 0 20 30 40 50 60 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 75 C T J = 25 C V GS = 0 V 0.5.0.5 2.0 2.5 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms T = 25 C ms C TJ = 75 C Single Pulse 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) I D, Drain Current (A) 50 50 40 40 30 30 20 20 R D V DS V GS D.U.T. R G V Pulse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit V DS 90% V - DD 0 0 25 50 75 0 25 50 75 25 50 75 0 25 50 75 T C, Case Temperature ( C) T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp I AS L D.U.T 0.0Ω 5V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 500 400 300 200 0 TOP BOTTOM I D 2A 2A 29A 0 25 50 75 0 25 50 75 Starting T, Junction Temperature( J C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS www.irf.com 7
D 2 Pak Package Outline.40 (.055) MAX..54 (.45).29 (.405) - A - 2 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048).6 (.400) REF. 6.47 (.255) 6.8 (.243).78 (.070).27 (.050) 3 5.49 (.6) 4.73 (.580) 2.79 (.) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.3) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF. 0.25 (.0) M B A M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIO NS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.0) 2X Part Marking Information D 2 Pak INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S 9246 9B M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK A 8 www.irf.com
Package Outline TO-262 Outline Part Marking Information TO-262 www.irf.com 9
Tape & Reel Information D 2 Pak TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) 0.368 (.045) 0.342 (.035) FEED DIRECTION TRL.85 (.073).65 (.065).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) 24.30 (.957) 23.90 (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) 27.40 (.079) 23.90 (.94) 4 330.00 (4.73) MAX. 60.00 (2.362) MIN. NOTES :. CO M FO RM S TO EIA-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (.039) 24.40 (.96) 3 30.40 (.97) MAX. 4 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) 322 333 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: 44 883 732020 IR CANADA: 732 Victoria Park Ave., Suite 20, Markham, Ontario L3R 2Z8, Tel: (905) 475 897 IR GERMANY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 49 672 96590 IR ITALY: Via Liguria 49, 07 Borgaro, Torino Tel: 39 45 0 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 7 Tel: 8 3 3983 0086 IR SOUTHEAST ASIA: 35 Outram Road, #-02 Tan Boon Liat Building, Singapore 036 Tel: 65 22 837 http://www.irf.com/ Data and specifications subject to change without notice. /97 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/