Semiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy 1
IC Failure Modes Affecting Reliability Via/metallization failure mechanisms Electro migration Stress migration Transistor failure mechanisms Time-dependent dielectric breakdown (TDDB) Hot carrier degradation NBTI and PBTI 2
IC Failure Modes Affecting Reliability Failure Mode Physics System Effect NBTI (PMOS) / PBTI (NMOS) TDDB Negative V t shift Slower speed Soft Breakdown: Slower speed Weakened gate oxide Increased leakage current Hard Breakdown/Punch through Timing Faults in Processors Resettable but increasing severity over time Increased ESD Vulnerability Non resettable timing faults Catastrophic Short Hot Carrier (NMOS) Metal Migration (Stress migration, electromigration) Positive V t shift Change in sub threshold swing Higher resistance in Via connections Open circuits Increased Off state power Increased current draw Decreased data retention time in DRAM Catastrophic Open 3
Electromigration Stress Migration Electromigration Transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. Known for more than 100 years, but became of practical interest with the advent of Semiconductor technologies Effects are occurring primarily at the boundaries and material interfaces Cu is intrinsically less sensitive to EM than Al but scaling and increasing current densities are pushing the limits Stress Migration Results from tensile stress due TCE mismatch of materials Stress relaxation over time through diffusion of vacancies leads to the formation of voids 4
Via/Metallization Failure Mechanisms 5
Electromigration (physical mechanism) 6
Electromigration (temperature dependency) Reported data from fast Wafer Level Reliability (fwlr) tests shows that every 50 C increase in the stress temperature will reduce the electromigration testing time by one order of magnitude. Ki Don Lee, et al., VIA PROCESSING EFFECTS ON ELECTROMIGRATION IN 65 NM TECHNOLOGY, 44th Annual International Reliability Physics Symposium, San Jose, 2006. 7
Transistor Failure Mechanisms MOS transistor 8
Transistor Failure Mechanisms 9
Time Dependent Dielectric Breakdown Failure mechanism in MOSFETs, when the gate oxide breaks down as a result of long-time application of relatively low electric field (as opposite to immediate breakdown, which is caused by strong electric field). The breakdown is caused by formation of a conducting path through the gate oxide to substrate due to electron tunnelling current, when MOSFETs are operated close to or beyond their specified operating voltages. 10
Time Dependent Dielectric Breakdown (TDDB) TDDB influenced by: Smaller Geometry More Tunneling Thinner Oxides (Tox) Substrate Injection (NMOS) Effects: Increased Noise Increased Power Switching characteristics Eventual wear-out and failure 11
TDDB (types of breakdown) 12
TDDB (types of breakdown) 13
TDDB (DC stress vs. AC stress) 14
Hot Carrier Injection (HCI) Degradation A phenomenon in which an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. To become hot and enter the conduction band of SiO2, an electron must gain a kinetic energy of 3.3 ev. For holes, the valence band offset in this case dictates they must have a kinetic energy of 4.6 ev. The term "hot electron" comes from the effective temperature term used when modelling carrier density and does not refer to the actual temperature of anything. High temperatures caused by the effect are unrelated to the phrase "hot electron effect". Carrier is injected from channel into gate dielectric Effects include heating of the device and increased leakage current Heating is caused by hot electrons giving off their excess energy as phonons. 15
Hot Carrier Degradation 3580 West Ina Road, Tucson AZ 85741 520-742-3300 ridgetopgroup.com 16
Hot Carrier Degradation 17
Hot Carrier Degradation 18 3580 West Ina Road, Tucson AZ 85741 520-742-3300 ridgetopgroup.com 18
Hot Carrier Degradation 19
NBTI and PBTI Negative bias temperature instability (NBTI) is a key reliability issue in MOSFETs. Of immediate concern for pmos operate almost always with negative gate-to-source voltage The very same mechanism affects also nmos when biased in the accumulation regime (PBTI) NBTI manifests as An increase in threshold voltage A decrease in drain current and transconductance The degradation has logarithmic dependence on time Two kinds of trap contribute to NBTI: Interface traps cannot be recovered over a reasonable time of operation - permanent traps similar to the ones resulting from HCI In case of NBTI, the electric field breaks Si-H bonds located at the SiO2 interface. H is released and migrates in the substrate. The remaining dangling bond Si- (Pb center) contribute to the threshold voltage degradation. Pre-existing traps located in the bulk of the dielectric (and supposedly nitrogen related), are filled with holes coming from the PMOS channel. Those traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over time. (Annealing effect) 20
NBTI and PBTI 21
NBTI and PBTI (SiO 2 gate) 22
NBTI and PBTI (high k gate) 23
NBTI and PBTI (SiO 2 vs. high k) 24
NBTI and PBTI (relaxation) 25
NBTI and PBTI (relaxation) 26
NBTI and PBTI (DC vs. AC stress) 27
Mitigation: Process Data Semiconductor processing always yield a distribution of parameter values Minimum geometries have larger fluctuations Smaller feature size & lower voltages increase the impact of variation of transistor properties on chip performance and yield Foundry-supplied Process Design Kit (PDK) may not give sufficiently accurate data for critical design parameters 28
Mitigation: Addressing Nanoscale Reliability Issues Use Additional Design Margin Increased power consumption Impacts overall circuit performance Collect Accurate Process information Lifetime Reliability Monitoring Real-time operating embedded sensors Actual State of Health for critical paths Early warning of impending failure 29
ProChek Semiconductor Reliability Characterization System 30
Characteristics of ProChek Targets bulk CMOS, SOI, SiGe reliability concerns NBTI / PBTI, TDDB, HC, EM, SM Test Coupon As little as 1 * 1mm chip area MPW for lower cost 32 1024 devices can be tested in parallel for maximum throughput On chip per transistor heaters to 325 C, greatly reducing test time Synthesizable (except for on chip heaters) to speed deployment Bench top Tester Fully programmable test conditions cover DC and AC stress cases Portable and compact ATE not needed Host Controller Easy to use software GUI Rich suite of built in reliability test templates Data processing capabilities 31
Sentinel Silicon Die Level Prognostic Solutions and Applications 32
Calibrated Prognostic Distance Stress/Accelerate: T1 = 99% failure in canary T2 = 1% failure in host Prognostic Distance = T2 T1 33
Questions? Esko Mikkola, Ph.D. Senior Principal Engineer Esko.Mikkola@RidgetopGroup.com 520-742-3300 x141 (office) Andrew Levy Director, Semiconductor & Precision Instruments Division Andrew.Levy@RidgetopGroup.com 520-742-3300 x115 (office) 503-320-5466 (mobile) Ridgetop Group Inc. 3580 West Ina Road Tucson, AZ 85741 34