Lithography Roadmap without immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 157nm EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
Lithography Roadmap with immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 1.1-1.2 NA 157nm EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
Lithography Roadmap with immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 1.1-1.2 NA 157nm ~1.2 NA EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
157nm has no window Resolution @ k1=0.3 (nm) 65 60 55 50 45 40 35 30 Max Resolution with High Index Fluids with sinθ=0.93 Dry PFPE Water 193nm 157nm Fluid high-n Fluid x needed 1 1.1 1.2 1.3 1.4 1.5 1.6 Refractive Index ArF water immersion replaces F 2 dry ArF fluid high-n immersion replaces F 2 -PFPE
SPIE 2005 Fluid highlights Testing at 32nm with Dupont IF131 and IF132 High-n Immersion Fluids (Initial Fluid Screening) 32nm Lines (pitch 64nm) IF13 1 IF13 2 Similar imaging performance from the two fluids, both very good! SPIE, M arch 1, 2 005
Lithography Roadmap with immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 1.1-1.2 NA 1.3-1.5 NA 157nm ~1.2 NA EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
Lithography Roadmap with immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 1.1-1.2 NA 1.3-1.5 NA 157nm EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
k 1 factor resolution = k 1. λ NA Half Pitch Technology Node [nm] 90 65 45 32 22 NA [@ 193 nm] 0.75 0.35 0.25 0.17 0.12 0.09 0.85 0.40 0.29 0.20 0.14 0.10 0.94 0.44 0.32 0.22 0.16 0.11 1.05 0.49 0.35 0.24 0.17 0.12 1.2 0.56 0.40 0.28 0.20 0.14 1.35 0.63 0.45 0.31 0.22 0.15 1.5 0.70 0.51 0.35 0.25 0.17 1.65 0.77 0.56 0.38 0.27 0.19 1.8 0.84 0.61 0.42 0.30 0.21
Lithography Roadmap with immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 1.1-1.2 NA 1.3-1.5 NA 157nm EUVL 3-year cycle: 2-year cycle: 1999 2002 2001 2004 2003 2007 2005 2010 2007 2013 2009 2016 2011
Rayleigh equation Lord Rayleigh resolution = k1. λ NA k 1 scaling Double exposure techniques
Double dipole imaging Random logic DY DX
Impact of polarization on SRAM active layer print (110 nm pitch) Unpolarized Polarized E=21 CD=59 E=24.6 CD=56 E=22.2 CD=60 E=25.8 CD=51.5 DY40 0.96/0.76 E=23.4 CD=58 23 % EL Dry NA=0.93
Double patterning (2x litho + 2x etch) Pitch = 100nm CD=50nm k 1 =0.19 50 nm L&S with 0.75NA Int. Exposure 1 Exp. 1 Exp. 2 Resist Nitride HM Si & development Transfer to hardmask 100nm pitch Int. Exposure 2 & development Transfer to hardmask
Double patterning complex pattern + = 1 st exposure develop and etch 2 nd exposure develop etch 150-nm pitch NA = 0.75 193 nm k 1 = 0.29
Double exposure technique CoO considerations Requires 2 critical masks Reduces throughput (~ factor 2) Adds cost of hard mask and etch Critical overlay requirement Impacts cycle time (additional photo, etch, )
Outline Introduction 193nm immersion lithography EUV lithography Global collaboration Status, Challenges Conclusions
EUV lithography Main technology challenges Contamination control Pellicle free mask Mask Defect Free Multilayer coated Source induced contamination C x H y, O optics Multilayer coated optics High power source Thin resist Highly sensitive Low LER
EUV tool integration progress service corridor reticle stage sourcecollector module baseframe reticle handler servo, vacuum, water, electronics cabinets wafer stage wafer handler 0.25 NA full field
EUV tool integration progress service corridor reticle stage sourcecollector module baseframe reticle handler servo, vacuum, water, electronics cabinets wafer stage wafer handler
EUV lithography Main technology challenges Mask Defect Free Multilayer coated Contamination control Multilayer coated optics High pow er source Thin resist Highly sensitive Low LER
no pellicle during exposure EUV lithography Main technology challenges High pow er source Contamination control Mask Defect Free Multilayer coated Multilayer coated optics Mask blank Mask making Absorber Absorber Buffer Buffer Multilayer Low thermal expansion Substrate substrate Thin resist Highly sensitive Low LER EUV mask cross section (TEM courtesy of AMD)
EUV lithography Main technology challenges SEMATECH MBDC EUV Blank Defect Progress 100 10 ML Adders + Decoration ML Adders Total D efects PMs Goals Defect Density (d/cm^2 @ 80 nm) 1 0.1 Q104 goal: 0.3 @ 90nm Mask Defect Free Multilayer coated Q204 goal: 0.12 @ 80nm Q404 goal: 0.08 @ 80nm High pow er source 0.01 Contamination control Significant progress in defect reduction Multilayer coated optics 0.001 Sep-03 Dec-03 Mar-04 May-04 Aug-04 Nov-04 Thin resist Highly sensitive Low LER
EUV lithography Main technology challenges Fast progress on system productivity (source power) High power source Contamination control Mask Defect Free Multilayer coated Multilayer coated optics Thin resist Highly sensitive Low LER EUV Power at Intermediate Focus [W] 1000.0 115 W production requirement 100.0 10.0 1.0 Average of reported Exponential fit to data 0.1 Jul-01 Jan-02 Jul-02 Jan-03 Jul-03 Jan-04 Jul-04 Jan-05 Jul-05 Jan-06 Date Data from Sematech EUV Source Workshops
EUV lithography Main technology challenges Multilayer coated optics Optics substrate (Images courtesy of VNL / EUVLLC) Mask Defect Free Multilayer coated Contamination control Multilayer coated optics High power source Thin resist Highly sensitive Low LER
EUV lithography Main technology challenges increasing exposure dose Resist Sensitivity vs. Line Edge Roughness (trade off) Better edge definition Edge variation over certain line length is Line Edge Roughness Mask Defect Free Multilayer coated Contamination control Multilayer coated optics High power source Thin resist Highly sensitive Low LER
EUV lithography Main technology challenges Resist Sensitivity vs. Line Edge Roughness (trade off) Line Edge Roughness Diffusion Length Shot noise statistics Mask Defect Free Multilayer coated Contamination control Multilayer coated optics Resolution Sensitivity High power source Thin resist Highly sensitive Low LER
New Resist Approaches Positive-tone Molecular Glass Resist 2:1 Cornell University 35 40 45 50 60 Shorter polymers may provide a possible solution HO O t-boc 40 nm (2:1) t-boc O O t-boc t-boc O O t-boc HO O t-boc 10.0mJ/cm 2 Bright Field (Courtesy of Prof. Chris Ober, Cornell University)
resolution= k 1. λ NA hp 32nm options NA k 1 λ Critical challenges: ArF Immersion 1.8 NA (k 1 =0.3) Single exposure ArF Immersion 1.35 1.5 NA (k 1 =0.22) Double exposure EUVL 0.25 NA (k 1 =0.6) Single exposure Lens size and cost Liquid (n f >1.8) Cost of mask (2x) Throughput reduction Defect free mask - Mask blank defect density - No pellicle during exposure New lens material (n f >1.8) Cost of additional process steps (hard mask dep/etch) Overlay requirement CoO - Source power - Optics lifetime - Resist sensitivity
Outline Introduction 193nm immersion lithography EUV lithography Global collaboration Conclusions
Research challenges require World-wide Research Partnerships between Research Organization IC Manufacturers Equipment Suppliers
imec 193nm Immersion program The world s largest 193nm immersion lithography effort STMicr oelectronics Lam RESEARCH True global partnership
International EUV Initiative Japan: ASET EUVA MIRAI IEUV I Chairman: Paolo Gargini : IEUVI International EUV Initiative US: EUV LLC SEMATECH VNL SRC Europe: MEDEA+ LETI IMEC IEUVI Technical Working Groups (TWG) Mask TWG Chair: Phil Seidel SEMATECH Organizer: Shinij Okazaki EUVA e.g. Mask handling solutions Optics TWG Chair: Ginger Edw ards SEMATECH / Freescale Co-Chair: Yasuaki Fukuda EUVA / Canon Organzier: Giang Dao SEMATECH / Intel Source TWG Chair: Koichi Toyoda EUVA Co-Chair: Stefan Wurm SEMATECH / Infineon Organizer: Dieter Goltz MEDEA Resist TWG Chair: Kim Dean SEMATEC H Co-Chair: Wolf-Dieter Domke Infineon Organizer: Serge Tedesco CEA / LETI an International Consortium Network
Outline Introduction 193nm immersion lithography EUV lithography Global collaboration Conclusions
Conclusion ArF immersion has eliminated 157nm lithography Phenomenal progress has been obtained for ArF immersion lithography in less than 24 months End 2003: ASML/IMEC demonstrated first data on immersion feasibility prototype scanner (0.75NA AT1150i) End 2004: Two development scanners (0.85NA) have been installed in the field Key challenges for immersion have been identified; solutions have been proposed/demonstrated for all issues In order to cope with the extremely short introduction time, world-wide partnerships and collaboration have proven to be very effective ArF immersion is clearly usable down to at least hp 45nm hp 32nm is unlikely to happen with immersion lithography and is believed to be the introduction node for EUVL Significant progress has been made on the most important critical issues for EUVL (mask defects, source power, )
Acknowledgement Many people have contributed to this presentation IMEC lithography team (K. Ronse, G. Vandenberghe, ) ASML (M. van den Brink) Zeiss Sematech (S. Wurm)
Immersion Lithography However, early 2004: Feasibility study of IMMERSION LITHOGRAPHY successful Several advantages (over 157nm) : Build further on mature 193nm resists Majority of optical material remains fused silica (not CaF 2 ) Same reticle materials continue to be used No thick Qz pellicles needed No modified Qz blanks needed
Resolution outlook 46 half pitch [um] 44 42 40 38 36 34 32 30 38-nm with new fluid and New lens k1=0.3 k1=0.27 32-nm requires very high index 1.5 1.6 1.7 1.8 1.9 2 index [-]