EE 482 Electronics II

EE 482 Electronics II Lab #4: BJT Differential Pair with Resistive Load Overview The objectives of this lab are (1) to design and analyze the performance of a differential amplifier, and (2) to measure the effects of different current sources on the performance. Theory The response of a differential amplifier has a region in which the output is linearly proportional to the differential input component. We will operate in this region by keeping the input range small and operating on the small linear section of the voltage transfer curve (VTC). Ideally, a differential amplifier will reject signals common to both inputs, but this is true only if the current source has infinite output resistance. In an actual differential amplifier, the commonmode gain will be small, but measurable, and its value can be used to estimate the output resistance of the current source. Figure 1 shows a resistively-loaded differential amplifier with the single-ended output taken from the collector of Q 2. V CC = +12 V R C1 R C2 v id 10 kω 100 µf ~ 100 Ω Q 1 Q 2 100 Ω R L v o 6 ma V EE = 12 V Figure 1. Differential Amplifier with Resistive Load Electronics II EE 482 Lab #4: BJT Differential Pair, Resistive Load Rev 1.1 (6/30/09) Page 1 of 5

The differential-mode and common-mode gains for single-ended output from the differential amplifier are given by ( R R ) g m C 2 L A d = and 2 A cm ( R R ) C 2 L 2Rout( CS ), respectively, where g m can be calculated from the DC collector current, and R out(cs) is the output resistance of the current source. There are also a few additional resistors at the input. This is to make a voltage divider at the input (with the output resistance of the source) since you will need to constrain the input to less than 100 mv in order to see an undistorted gain of 600 V/V (the target gain for the multistage amplifier in Lab #5). Also note that we need v be < 5 mv in order for our small-signal assumptions for Q 1 and Q 2 to remain valid. We then need to match the DC resistance to ground at each base because of the base currents. If we ground the base of Q 1, then it will be centered at 0 V, while the base current at Q 2 will pass through the 100 Ω resistor, causing a few mv to appear as a DC voltage at that point. This may seem irrelevant, but this difference will be multiplied by 600 in the full multistage amplifier, and it will greatly affect the DC offset of your circuit. If both bases see the same resistance to ground, they will both have the same DC voltage, and then the common mode gain is taken into account instead of the differential mode gain. Some cautionary notes pertaining to the CA3046 (or equivalent NTE912) array from Lab #3 are worth reviewing here: (1) See the datasheet on the website for a diagram of the CA3046 chip: (http://www.intersil.com/data/fn/fn341.pdf. Alternatively, see the datasheet on the website for a diagram of the NTE912 chip: (http://www.nteinc.com/specs/900to999/pdf/nte912.pdf. (2) The differential pair corresponding to transistors Q 1 and Q 2, or pins 1 5 on the chip pinout from the website given above, are the same as Q 1 and Q 2 in Figure 1. (3) Note that Q 5 in the CA3046 (or NTE912) array has its emitter terminal connected to the substrate. The substrate terminal in this technology (pin 13) must be tied to the most negative potential in the system here, the 12 V supply in order to provide isolation between each of the transistors in the array. Therefore, Q 5 cannot be used for Q 3 in the current-buffered or Wilson sources. (4) Note that you will place the HFA3046 chip in your schematic and then modify the macromodel to create the CA3046 (NTE912) part before running the simulation. Instructions for doing this are located in the Appendix of Lab #3. Electronics II EE 482 Lab #4: BJT Differential Pair, Resistive Load Rev 1.1 (6/30/09) Page 2 of 5

Pre-Lab Review the planned experiments. Using hand calculations and simulation, design a differential amplifier (Figure 1) with a differential gain of 60 V/V ( ± 10%) using a CA3046/NTE912 BJT array and the closest standard value resistors. Note that pins 1-5 correspond to the matched differential pair in the CA3046/NTE912 array. The biasing should be done with a current source of 6 ma (use the current source designs from Lab #3). For the design of the differential amplifier, you may ignore base currents and the Early effect at DC. Design for a load of R L = 8.2 kω. Lab Exercise Build and test the circuit of Figure 1 twice once with the basic current source, and then using the Wilson current mirror. Note that you must remove the load R L from the current mirror circuits that were designed and evaluated in Lab #3. The loads R L from the Lab #3 circuits are replaced here by the differential amplifier. Note also that pins 1-5 correspond to the matched differential pair in the CA3046/NTE912 array. Either version of Figure 1 can be built using a single CA3046/NTE912 array. In each case, measure differential and common mode gain (use a sufficiently small input signal for measuring differential gain; use an input signal of 2 V amplitude for measuring common mode gain). Notes: (1) To measure the common mode gain you will need to use a second capacitor and apply the source voltage to both inputs simultaneously i.e., Q 2 should be driven exactly like Q 1 is in Figure 1. (2) To determine how large the input signals can be, consider the gain (differential or common mode) and the DC supply voltages. (3) Drive with a 1 khz sine wave. Note: Keep the circuit with the Wilson current mirror assembled for Lab #5. Electronics II EE 482 Lab #4: BJT Differential Pair, Resistive Load Rev 1.1 (6/30/09) Page 3 of 5

Tech Memo Analysis The following will refer to two sets of simulations and test measurements. One set comes from the circuit of Figure 1 when the current source is the simple current source from Lab #3. The second set comes from the circuit of Figure 1 when the current source is the Wilson current mirror from Lab #3. In both cases the differential amplifier itself (everything except for the current source) is the same. Address all of the following in your tech memo: Show the calculations for the design of the differential amplifier, based on a DC tail current of 6 ma. (The tail current is the total DC bias current sunk from the differential amplifier by the current source.) Show the results of your design simulations, including the differential and common-mode responses (and inputs) for the two different current sources. From your simulated responses, determine the differential-mode and common-mode gains for each of the two amplifiers, as well as the two CMRRs. Compare the results from the two different current sources, with particular attention to the common-mode gains. Show the results of your test measurements, including the differential and common-mode responses (and inputs) for the two different current sources. From your test measurements, determine the differential-mode and common-mode gains for each of the two amplifiers, as well as the two CMRRs. Compare the results from the two different current sources, with particular attention to the common-mode gains. Using the measured common-mode gain for the differential amplifier with the basic current source, calculate r o for the transistor and determine the value of the Early voltage, V A. (Hint: recall that the common-mode gain is directly affected by the output resistance of the current source.) Electronics II EE 482 Lab #4: BJT Differential Pair, Resistive Load Rev 1.1 (6/30/09) Page 4 of 5

Check-Off Sheet TA Signature: Date: Electronics II EE 482 Lab #4: BJT Differential Pair, Resistive Load Rev 1.1 (6/30/09) Page 5 of 5