Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology node was introduced How does this impact the design flow? Timing Closure problem IIT Madras - C.P. Ravikumar 2 1
Interconnect delays Source - ITRS IIT Madras - C.P. Ravikumar 3 Need for Communication-centric centric Design Flow Communication is THE most critical aspect affecting system performance Communication architecture consumes upto 50% of total on-chip power Ever increasing number of wires, repeaters, bus components (arbiters, bridges, decoders etc.) increases system cost Communication architecture design, customization, exploration, verification and implementation takes up the largest chunk of a design cycle Communication Architectures in today s complex systems significantly affect performance, power, cost and time-to-market! significantly affect performance, IIT Madras - C.P. power, Ravikumar cost and time-to-market! 4 2008 Sudeep Pasricha & Nikil Dutt 4 2
Cu Al 1.72 x 10-8 Ωm 2.82 x 10-8 Ωm Solutions Material with better ρ Moving to copper interconnect Trenches are created in the underlying silicon oxide insulating layer where the metal is desired. A thick coating of copper deposited overfills the trenches Chemical-mechanical Polishing used to remove the copper to the level of the top of the insulating layer Barrier metal needed to prevent spreading IIT Madras - C.P. Ravikumar 5 Interconnect Reliability Metal Migration (EM) Can result in long-term failure of interconnects Reliability problem in integrated circuits Copper is better than Aluminum IIT Madras - C.P. Ravikumar 6 3
Increase metal thickness Solutions Reduce interconnect resistance What side effects does this cause? R = ρl HW IIT Madras - C.P. Ravikumar 7 Solutions to Crosstalk Problem: Reduce parasitic capacitance Low-k Dielectric Silicon Dioxide has a relative permittivity of 3.9 Materials research has yielded dielectrics with lower permittivity Flourine doped SiO 2 3.5 Carbon doped SiO 2 3.0 Crosstalk analysis Crosstalk Delay and Crosstalk Failure Increase metal separation (selectively) Crosstalk aware placement & routing IIT Madras - C.P. Ravikumar 8 4
Interconnect Estimation Logic Synthesis tools need to estimate interconnect lengths and wire delays Statistical Wire Load Model (WLM) Physical Synthesis tools perform placement and routing concurrently with synthesis IIT Madras - C.P. Ravikumar 9 Interconnect Delay Calculation Lumped and Distributed Delay Models IIT Madras - C.P. Ravikumar 10 5
Elmore Delay Model V in R 1 R 2 1 2 R i-1 i-1 R i i R N-1 N-1 R N N V out C 1 C 2 C i-1 C i C N-1 C N τ N = N i= 1 R N i j= i C j = N i= 1 C i i j= 1 R j IIT Madras - C.P. Ravikumar 11 Example Assume N segments, each with resistance r and capacitance c The Elmore Delay can be further extended for interconnects with tree topology IIT Madras - C.P. Ravikumar 12 6
Elmore Delay for RC Tree Delay at a node j = Σ k (C k R jk ) R jk is the sum of all resistances that are common to the path from the source to node j and the path from source to node k Delay at node 1 = C 1 (R 1 ) + C 2 (R 1 ) + C 3 (R 1 ) Delay at node 2 = C 1 (R 1 ) + C 2 (R 1 +R 2 ) + C 3 (R 1 ) Delay at node 3 = C 1 (R 1 ) + C 2 (R 1 ) + C 3 (R 1 +R 3 ) IIT Madras - C.P. Ravikumar 13 When should inductance be considered? Length criteria for including inductance in interconnect model IIT Madras - C.P. Ravikumar 14 2008 Sudeep Pasricha & Nikil Dutt 14 7
Reducing Interconnect Delay Repeater Insertion Where should the buffers be inserted? What are the sizes of the buffers? IIT Madras - C.P. Ravikumar 15 Interconnect Delay with repeaters Consider a wire of length L, divided into N sections Assume that there are N repeaters, one at the beginning of each section Assume that the W/L ratio for a unit-sized driver is β Assume that all drivers are of size M Model for any section must include Self-resistance of the repeater Self-capacitance of the repeater π-model of the Interconnect segment of length L/N Load capacitance presented by the subsequent repeater IIT Madras - C.P. Ravikumar 16 8
RC-model for one segment R 1 = R d /M R 2 = R int L/N C 1 = C d M (1+β) + C int L/(2N) C 2 = C g M (1+β) + C int L/(2N) Elmore Delay at the output of the segment is: t segment = R 1 C 1 + (R 1 +R 2 )C 2 Total delay of the wire with repeaters = N t segment Differentiate the total delay expression w.r.t. N and set it to 0 ; solve for N to get N opt Differentiate the total delay expression w.r.t. M and set it to 0; solve for M to get M opt IIT Madras - C.P. Ravikumar 17 Signal Routing Synchronous digital circuits that use edge-triggered flip-flops Concept of setup delay Period of the clock = T T > t clk-q of launch flop + Path delay from Q launch to D capture + t setup of capture flop Path Delay in deep submicron technologies depends on Gate Delay (which is a function of P, V, T) Interconnect Delay IIT Madras - C.P. Ravikumar 18 9
Logic Synthesis and Physical Design Before 130nm technology, it was possible to separate logic synthesis and physical design Interconnect delays were not as big a component as gate delay before 180nm Estimating interconnect delay through statistical wireload model was reasonably accurate in 180nm technology Timing Closure problems in 130nm technology and beyond Unable to predict interconnect delays accurately without knowledge of placement and routing information Physical Synthesis performs logic synthesis + physical design simultaneously tools are more complex IIT Madras - C.P. Ravikumar 19 Performance-directed Placement and Routing Delays estimated in logic synthesis can be fed as constraints to physical design tools Early physical design tools mainly focussed on minimizing TOTAL wire length There were constraints on routing congestion Placement and routing tools today accept timing constraints IIT Madras - C.P. Ravikumar 20 10
Routing Trees 10 units of wire A multiple-pin net (wire) is routed as a tree Minimum-length Rectilinear Spanning Tree Create an MST using Euclidean distance as a measure Convert the edges to Manhattan routes Minimum-length Rectilinear Steiner Tree Introduce Steiner points Example shows a 4-pin net E.G. One gate driving 3 other gates IIT Madras - C.P. Ravikumar 21 8 units of wire Wireload model Get an estimate of wirelength at logic synthesis stage Model wire-length as a function of fan-out Statistical Wireload model Collect chip data and create a correlation between fanout and wirelength IIT Madras - C.P. Ravikumar 22 11
Driver Sizing Transistor sizing techniques aim to lower delay Wider transistors have a few advantages but also several disadvantages + produce more current + reduce charge time of load capacitance have greater physical area have larger gate capacitance increased circuit area and power IIT Madras - C.P. Ravikumar 23 2008 Sudeep Pasricha & Nikil Dutt 23 Wire Sizing Width of an interconnect affects the power characteristics and propagation delay Consider a CMOS inverter driving an RC interconnect line Simple first order model of delay IIT Madras - C.P. Ravikumar 24 2008 Sudeep Pasricha & Nikil Dutt 24 12
Wire Sizing Increasing the driver transistor width reduces R tr decreasing the circuit delay trading off circuit power and area for higher speed Increasing the width of the interconnect to reduce R int does not significantly reduce the delay caused by the RC interconnect impedance since decrease in wire resistance is offset by increase in wire capacitance IIT Madras - C.P. Ravikumar 25 2008 Sudeep Pasricha & Nikil Dutt 25 Wire Sizing Dynamic power increases with width since line capacitance is greater As line inductance-to-resistance ratio increases with wider lines, short-circuit power decreases due to reduction in signal transition time IIT Madras - C.P. Ravikumar 26 2008 Sudeep Pasricha & Nikil Dutt 26 13
3-D ICs With shorter interconnects in 3D ICs, switching energy and cycle time are expected to be reduced Take advantage of multiple layers in routing critical paths IIT Madras - C.P. Ravikumar 27 Types of interconnects Signal carriers Carry data and control signals Clock carriers Power and Ground IIT Madras - C.P. Ravikumar 28 14
Clock Tree Construction Synchronous circuits require that (ideally) all flipflops toggle at the same time Interconnect Delays along the clock line result in clock skew Clocks are often designed as H-tree to balance the skew from source to sinks T > skew + t clk-q of launch flop + Path delay from Q launch to D capture + t setup of capture flop When number of IP increases, maintaining the synchronous paradigm is a challenge Globally Asynchronous, Locally Synchronous IIT Madras - C.P. Ravikumar 29 Signal Carriers Point-to-point connections One source of data and one sink Sometimes, we may have multiple sources of data and multiple sinks Example multiple CPUs / multiple memories Bus is a way to share data paths Reduces interconnect area As we increase the number of sources/sinks, communication latencies increase IIT Madras - C.P. Ravikumar 30 15
Bus Terminology IIT Madras - C.P. Ravikumar 31 2008 Sudeep Pasricha & Nikil Dutt 31 Bus Terminology Master (or Initiator)? IP component that initiates a read or write data transfer Slave (or Target)? IP component that does not initiate transfers and only responds to incoming transfer requests Arbiter? Controls access to the shared bus? Uses arbitration scheme to select master to grant access to bus Decoder? Determines which component a transfer is intended for Bridge? Connects two busses? Acts as slave on one side and master on the other IIT Madras - C.P. Ravikumar 32 2008 Sudeep Pasricha & Nikil Dutt 32 16
Bus Physical Structure tri-state buffer based bidirectional signals Commonly used in off-chip/backplane buses + take up fewer wires, smaller area footprint - higher power consumption, higher delay, hard to debug IIT Madras - C.P. Ravikumar 33 2008 Sudeep Pasricha & Nikil Dutt 33 Bus Physical Structure MUX based signals Separate read, write channels IIT Madras - C.P. Ravikumar 34 2008 Sudeep Pasricha & Nikil Dutt 34 17
Bus interconnects Routing congestion Example a single controller for a large number of data path elements Higher Bus capacitance implies higher bus power and delay Crosstalk may result in data errors Data encoding techniques exist to reduce such errors and the switching activity on the bus lines IIT Madras - C.P. Ravikumar 35 Bus crosstalk Concept of a victim and an aggressor In a bus with multiple wires, a single wire may have multiple aggressors Shielding can eliminate the crosstalk between two wires Extra area An entire metal layer is sometimes used in between two metal layers to shield wires in the two layers from crosstalk Encoding of data can be used to achieve a similar effect IIT Madras - C.P. Ravikumar 36 18