Integrated Circuit Systems, Inc. ICS954 AMD - K8 System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Output Features: 3 - Differential pair push-pull CPU clocks @ 3.3V 9 - PCICLK (Including free running) @ 3.3V 3 - Selectable PCICLK/HTTCLK @ 3.3V - HTTCLK @ 3.3V - 48MHz @ 3.3V fixed. - 24/48MHz @ 3.3V 2 - REF @ 3.3V, 4.38MHz. Features: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology and RESET# output to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/ write operations. Uses external 4.38MHz crystal. Supports Hyper Transport Technology (HTTCLK). Functionality FS3 FS2 FS FS CPU HTT PCI MHz MHz MHz.9 67.27 33.63 33.9 66.95 33.48 68. 67.2 33.6 22. 67.33 33.67.2 66.8 33.4 33.5 66.75 33.38 66.7 66.68 33.34 2.4 66.8 33.4 5. 6. 3. 8. 6. 3. 2. 7. 35. 24. 6. 3. 27. 67.5 33.75 233.33 66.67 33.33 266.67 66.67 33.33 3. 75. 37.5 ~*FS/REF VDDHTT 2 3 2 4 GND 5 *ModeA/HTTCLK 6 *ModeB/PCICLK8/HTTCLK 7 PCICLK9/HTTCLK2 8 VDDPCI 9 GND PCICLK/HTTCLK3 *FS2/PCICLK 2 PCICLK 3 PCICLK 4 GND 5 VDDPCI 6 PCICLK2 7 PCICLK3 8 VDDPCI 9 GND 2 2 PCICLK4 2 2 PCICLK5 22 2 PCICLK6 23 2 PCICLK7 24 Pin Configuration ICS954 48-SSOP * Internal Pull-Up Resistor ~ This Output has.5x drive 48 REF/FS* 47 GND 46 VDDREF 45 Reset# 44 VDDA 43 GND 42 CPUCLK8T 4 CPUCLK8C 4 VDDCPU 39 CPUCLK8T 38 CPUCLK8C 37 GND 36 VDDCPU 35 CPUCLK8T2 34 CPUCLK8C2 33 GND 32 Turbo# 3 PD#* 3 48MHz/FS3** 29 GND 28 AVDD48 27 24_48MHz/Sel24_48#* 26 SDATA 25 SCLK 2 This Output has 2 Default Drive and can be programmaed lower via IIC PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS954 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION ~*FS/REF I/O Frequency select latch input pin / 4.38 MHz reference clock. 2 VDDHTT PWR Supply for HTT clocks, nominal 3.3V. 3 IN Crystal input, Nominally 4.38MHz. 4 2 OUT Crystal output, Nominally 4.38MHz 5 GND PWR Ground pin. 6 *ModeA/HTTCLK I/O Mode selection latch input pin / Hyper Transport output. 7 *ModeB/PCICLK8/HTTCLK I/O Mode selection latch input pin / PCI clock output / Hyper Transport output. 8 PCICLK9/HTTCLK2 OUT PCI clock output / Hyper Transport output. 9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V GND PWR Ground pin. PCICLK/HTTCLK3 OUT PCI clock output / Hyper Transport output. 2 *FS2/PCICLK I/O Frequency select latch input pin / 3.3V PCI clock output. 3 PCICLK OUT PCI clock output. 4 PCICLK OUT PCI clock output. 5 GND PWR Ground pin. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK2 OUT PCI clock output. 8 PCICLK3 OUT PCI clock output. 9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 2 PCI clock output. This output is default @ 2 drive and can be programmed to lower OUT 2PCICLK4 drive via IIC. 22 PCI clock output. This output is default @ 2 drive and can be programmed to lower OUT 2PCICLK5 drive via IIC. 23 2PCICLK6 OUT PCI clock output. This output is default @ 2 drive and can be programmed to lower drive via IIC. 24 2PCICLK7 OUT PCI clock output. This output is default @ 2 drive and can be programmed to lower drive via IIC. 25 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 26 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 27 24_48MHz/Sel24_48#* I/O 24/48MHz clock output / Latched select input for 24/48MHz output. =48MHz, = 24MHz. 28 AVDD48 PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V 29 GND PWR Ground pin. 3 48MHz/FS3** I/O Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin 3 PD#* IN Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. 32 Turbo# IN Real time input pin to change frequency to a pre-programmed under or over clock entries located in IIC Rom table. 33 GND PWR Ground pin. 34 CPUCLK8C2 OUT Complimentary clock of differential 3.3V push-pull K8 pair. 35 CPUCLK8T2 OUT True clock of differential 3.3V push-pull K8 pair. 36 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 37 GND PWR Ground pin. 38 CPUCLK8C OUT Complimentary clock of differential 3.3V push-pull K8 pair. 39 CPUCLK8T OUT True clock of differential 3.3V push-pull K8 pair. 4 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 4 CPUCLK8C OUT Complimentary clock of differential 3.3V push-pull K8 pair. 42 CPUCLK8T OUT True clock of differential 3.3V push-pull K8 pair. 43 GND PWR Ground pin. 44 VDDA PWR 3.3V power for the PLL core. 45 Reset# OUT Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 46 VDDREF PWR Ref, TAL power supply, nominal 3.3V 47 GND PWR Ground pin. 48 REF/FS* I/O 4.38 MHz reference clock / Frequency select latch input pin. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~.5 Drive Strength 2
ICS954 General Description The ICS954 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS954 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to.mhz increment. Block Diagram PLL2 48MHz / 2 24_48MHz 2 TAL OSC REF (:) PLL Spread Spectrum CPU DIVDER CPUCLKC (2:) CPUCLKT (2:) PD# SDATA SCLK FS (3:) MODE (A,B) SEL24_48# Turbo# Control Logic Config. Reg. PCI DIVDER HTT DIVDER PCICLK (7:, ) PCICLK(,9,8)/HTTCLK (3:) HTTCLK Power Groups Pin Number VDD GND Description 2 5 tal, POR 9 PCICLK, HTTCLK O/p 6,9 5,2 PCICLK Outputs 29 27,3,33 48 MHz, Fix Analog 35,38 34,39 CPU Outputs 43 42 Analog, CPU PLL, MCLK 46 47 REF, Digital Core 3
ICS954 Table: Frequency Selection Table Bit4 Bit3 Bit2 Bit Bit CPU HTT PCI FS4 FS3 FS2 FS FS MHz MHz MHz.9 67.27 33.63 33.9 66.95 33.48 68. 67.2 33.6 22. 67.33 33.67.2 66.8 33.4 33.5 66.75 33.38 66.7 66.68 33.34 2.4 66.8 33.4 5. 6. 3. 8. 6. 3. 2. 7. 35. 24. 6. 3. 27. 67.5 33.75 233.33 66.67 33.33 266.67 66.67 33.33 3. 75. 37.5. 66.67 33.33 33.33 66.67 33.33 66.66 66.66 33.33 2. 66.67 33.33 3. 68.67 34.33 37.33 68.66 34.33 7.66 68.66 34.33 26. 68.67 34.33 54.49 6.79 3.9 85.38 6.79 3.9 26.3 72. 36.5 247.2 6.8 3.9 278. 69.53 34.76 24.34 68.67 34.33 274.68 68.67 34.34 38.97 77.24 38.62 Mode Functionality Tables ModeA ModeB Pin7 Pin8 Pin HTTCLK HTTCLK2 PCICLK HTTCLK HTTCLK2 HTTCLK3 PCICLK8 PCICLK9 PCICLK HTTCLK PCICLK9 PCICLK 4
ICS954 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N + - 5
ICS954 I 2 C Table: Frequency Select Register Byte Pin # Name Control Function Type PWD Bit 7 - SS_EN Spread Enable RW OFF ON Bit 6 - SEL24_48MHz Output Select RW 48MHz 24MHz Latch FS Source Select FS Source Select RW latch I2C FS4 Freq Select Bit 4 RW FS3 Freq Select Bit 3 RW Latch FS2 Freq Select Bit 2 RW See Table: Frequency Selection Table Latch Bit - FS Freq Select Bit RW Latch Bit - FS Freq Select Bit RW Latch I 2 C Table: Output Control Register Byte Pin # Name Control Function Type PWD Bit 7 CPUCLK8T/C2 Output Control RW Disable Enable Bit 6 6 HTTCLK Output Control RW Disable Enable Bit 5 7 PCICLK8/HTTCLK Output Control RW Disable Enable Bit 4 8 PCICLK9/HTTCLK2 Output Control RW Disable Enable Bit 3 PCICLK/HTTCLK3 Output Control RW Disable Enable Bit 2 2 PCICLK Output Control RW Disable Enable Bit 3 PCICLK Output Control RW Disable Enable Bit 4 PCICLK Output Control RW Disable Enable I 2 C Table: Output Control Register Byte 2 Pin # Name Control Function Type PWD Bit 7 7 PCICLK2 Output Control RW Disable Enable Bit 6 8 PCICLK3 Output Control RW Disable Enable Bit 5 2 PCICLK4 Output Control RW Disable Enable Bit 4 22 PCICLK5 Output Control RW Disable Enable Bit 3 23 PCICLK6 Output Control RW Disable Enable Bit 2 24 PCICLK7 Output Control RW Disable Enable Bit 28 24_48MHz Output Control RW Disable Enable Bit 3 48MHz Output Control RW Disable Enable I 2 C Table: Output Control Register Byte 3 Pin # Name Control Function Type PWD Bit 7 37,36 CPUCLK8T/C_ Output Control RW Disable Enable Bit 6 4,4 CPUCLK8T/C_ Output Control RW Disable Enable Bit 5 Reserved Reserved RW - - Bit 4 45,48 REF/REF Output Control RW Disable Enable PCI_Str PCI9,8 Strength RW :.5 Drive :.5 Drive PCI_Str Control only RW :. Drive : 2. Drive Bit - PCI_Str PCI Strength Control RW :.5 Drive :.5 Drive Bit - PCI_Str only RW :. Drive : 2. Drive 6
ICS954 I 2 C Table: Output Control Register Byte 4 Pin # Name Control Function Type PWD Bit 7 - PCIStr All other PCICLK RW :.5 Drive :.5 Drive Bit 6 - PCIStr Strength Control RW :. Drive : 2. Drive PCIStr PCICLK (7:6) Strength RW :.5 Drive :.5 Drive PCIStr Control RW :. Drive : 2. Drive PCIStr PCICLK (5) Strength RW :.5 Drive :.5 Drive PCIStr Control RW :. Drive : 2. Drive Bit - PCIStr PCICLK (4) Strength RW :.5 Drive :.5 Drive Bit - PCIStr Control RW :. Drive : 2. Drive I 2 C Table: Reserved Register Byte 5 Pin # Name Control Function Type PWD Bit 7 - Reserved Reserved RW Reserved Reserved Bit 6 - Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Bit - Reserved Reserved RW Reserved Reserved Bit - Reserved Reserved RW Reserved Reserved I 2 C Table: Byte Count Register Byte 6 Pin # Name Control Function Type PWD Bit 7 - BC7 RW Bit 6 - BC6 RW BC5 RW Writing to this register will configure how BC4 Byte Count RW many bytes will be read back, default is BC3 Programming b(7:) RW 6 = 6 bytes. BC2 RW Bit - BC RW Bit - BC RW I 2 C Table: Byte Count and Vendor ID Register Byte 7 Pin # Name Control Function Type PWD Bit 7 - REV_ID3 RW - - Bit 6 - REV_ID2 RW - - Revision ID REV_ID RW - - REV_ID RW - - Vendor_ID3 RW - - Vendor_ID2 RW - - Vendor ID Bit - Vendor_ID RW - - Bit - Vendor_ID RW - - 7
ICS954 I 2 C Table: Skew Control Register Byte 8 Pin # Name Control Function Type PWD Bit 7 - PCI/HTTSkw3 RW : :5 :3 :45 Bit 6 - PCI/HTTSkw2 CPU-PCI/HTT 7 Step RW :N/A :N/A :N/A :6 PCI/HTTSkw Skew Control (ps) RW :N/A :N/A :N/A :75 PCI/HTTSkw RW :N/A :N/A :N/A :9 PCISkw3 RW : :5 :3 :45 PCISkw2 CPU-PCI 7 Step Skew RW :N/A :N/A :N/A :6 Bit - PCISkw Control (ps) RW :N/A :N/A :N/A :75 Bit - PCISkw RW :N/A :N/A :N/A :9 I 2 C Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # Name Control Function Type PWD Bit 7 - ASEL Async Frequency Select RW 66MHz 75.4MHz Bit 6 - AEN AGP/PCI/ Freq Source Select RW FI PLL CPU PLL REF Strength REF strength control RW x 2x Reserved Reserved RW - - Bit 3 - WDTCtrl Watch Dog Time base Control RW 29ms Base 6ms Base WD2 WD Timer Bit 2 RW These bits represent *29ms (or.6s) Bit - WD WD Timer Bit RW the watchdog timer waits before it goes to Bit - WD WD Timer Bit RW alarm mode. Default is 7 29ms = 2s. I 2 C Table: VCO Control Select Bit & WD Timer Control Register Byte Pin # Name Control Function Type PWD Bit 7 - M/NEN M/N Programming Enable RW Disable Enable Bit 6 - WDEN Watchdog Enable RW Disable Enable WDStatus WD Alarm Status R Normal Alarm WD SF4 RW WD SF3 RW Watch Dog Safe Freq Writing to these bit will configure the safe WD SF2 RW Programming bits frequency as Byte bit (4:). Bit - WD SF RW Bit - WD SF RW I 2 C Table: VCO Frequency Control Register Byte Pin # Name Control Function Type PWD Bit 7 - N Div8 N Divider Prog bit 8 RW The decimal representation of N Divider in Bit 6 - N Div9 N Divider Prog bit 9 RW Byte and 2 M Div5 RW The decimal representation of M and N M Div4 RW Divier in Byte and 2 will configure the M Div3 M Divider Programming RW VCO frequency. Default at power up = M Div2 bits (5:) RW latch-in or Byte Rom table. Bit - M Div RW VCO Frequency = 4.38 x [NDiv(9:)+8] Bit - M Div RW / [MDiv(5:)+2] 8
ICS954 I 2 C Table: VCO Frequency Control Register Byte 2 Pin # Name Control Function Type PWD Bit 7 - N Div7 RW Bit 6 - N Div6 RW The decimal representation of M and N N Div5 RW Divier in Byte and 2 will configure the N Div4 N Divider Programming RW VCO frequency. Default at power up = N Div3 bit (7:) RW latch-in or Byte Rom table. N Div2 RW VCO Frequency = 4.38 x [NDiv(9:)+8] Bit - N Div RW / [MDiv(5:)+2] Bit - N Div RW I 2 C Table: Spread Spectrum Control Register Byte 3 Pin # Name Control Function Type PWD Bit 7 - SSP7 RW Bit 6 - SSP6 RW These Spread Spectrum bits in Byte 3 SSP5 RW and 4 will program the spread SSP4 Spread Spectrum RW pecentage. It is recommended to use SSP3 Programming b(7:) RW ICS Spread % table for spread SSP2 RW programming. Bit - SSP RW Bit - SSP RW I 2 C Table: Spread Spectrum Control Register Byte 4 Pin # Name Control Function Type PWD Bit 7 - Reserved Reserved R - - Bit 6 - SSP4 RW SSP3 RW These Spread Spectrum bits in Byte 3 SSP2 RW and 4 will program the spread Spread Spectrum SSP Programming b(4:8) RW pecentage. It is recommended to use SSP RW ICS Spread % table for spread Bit - SSP9 RW programming. Bit - SSP8 RW 9
ICS954 Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDD_A - V DD +.5V V 3.3V Logic Input Supply Voltage VDD_In - GND -.5 V DD +.5V V Storage Temperature Ts - -65 5 C Ambient Operating Temp Tambient - 7 C Case Temperature Tcase - 5 C Input ESD protection HBM ESD prot - 2 V Guaranteed by design and characterization, not % tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes Input High Voltage V IH 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL 3.3 V +/-5% V SS -.3.8 V Input High Current I IH V IN = V DD -5 5 ua Input Low Current V I IN = V; Inputs with no pull-up IL resistors -5 ua V I IN = V; Inputs with pull-up IL2 resistors -2 ua Low Threshold Input- High Voltage V IH_FS 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input- Low Voltage V IL_FS 3.3 V +/-5% V SS -.3.35 V Operating Supply Current I DD3.3OP Full Active, C L = Full load; 35 ma Operating Current I DD3.3OP all outputs driven 4 ma Powerdown Current I DD3.3PD all diff pairs driven 7 ma all differential pairs tri-stated 2 ma Input Frequency F i V DD = 3.3 V 4.388 MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins 5 pf From V Clk Stabilization T DD Power-Up or deassertion of PD# to st clock STAB.8 ms Modulation Frequency Triangular Modulation 3 33 khz Tdrive_PD# CPU output enable after PD# de-assertion 3 us Tfall_Pd# PD# fall time of 5 ns Trise_Pd# PD# rise time of 5 ns SMBus Voltage V DD 2.7 5.5 V Low-level Output Voltage @ I PULLUP.4 V Current sinking at =.4 V I PULLUP 4 ma SCLK/SDATA (Max VIL -.5) to T Clock/Data Rise Time RI2C (Min VIH +.5) ns SCLK/SDATA (Min VIH +.5) to T Clock/Data Fall Time FI2C (Max VIL -.5) 3 ns *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 4.388MHz to meet ppm frequency accuracy on PLL outputs.
ICS954 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.55 V Output High Current Output Low Current I OH I OL @MIN =. V -33 ma @MA = 3.35 V -33 ma @ MIN =.95 V 3 ma @ MA =.4 V 38 ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Rise Time t r =.4 V, = 2.4 V.5 2 ns Fall Time t f = 2.4 V, =.4 V.5 2 ns Duty Cycle d t =.5 V 45 55 % Group Skew t skew =.5 V 25 ps Jitter, Cycle to cycle t jcyc-cyc =.5 V 5 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 3 Spread Spectrum is off Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Long Accuracy ppm see Tperiod min-max values - ppm,2 Clock period T period 48.MHz output nominal 2.833 2.8354 ns 2 Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.55 V Output High Current Output Low Current I OH I OL @MIN =. V -33 ma @MA = 3.35 V -33 ma @ MIN =.95 V 3 ma @ MA =.4 V 38 ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Edge Rate t slewr/f_usb USB48 Rising/Falling edge rate 2 V/ns Rise Time t r =.4 V, = 2.4 V.5 2 ns Fall Time t f = 2.4 V, =.4 V.5 2 ns Rise Time t r_usb =.4 V, = 2.4 V 2 ns Fall Time t f_usb = 2.4 V, =.4 V 2 ns Duty Cycle d t =.5 V 45 55 % Group Skew t skew =.5 V 25 ps Jitter, Cycle to cycle t jcyc-cyc =.5 V 5 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not % tested in production.
ICS954 Electrical Characteristics - CPUCLKK8T/C K8 3.3V Push Pull Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Rising Edge Rate δv/δt At CPU's test load. V +/- 4 2 V/ns Falling Edge Rate δv/δt mv (diffential measurment) 2 V/ns Differential Voltage V DIFF.4 2.3 V Change in V DIFF_DC Magnitude V DIFF At CPU's test load. (singleended -5 5 mv Common Mode Voltage V CM measurement).5.45 V Change in Common Mode Voltage V CM -2 2 mv Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 2 ps Jitter, Accumulated t ja -,2,3 Measurement from differential Duty Cycle d t3 wavefrom 45 55 % Output Impedance R ON transition. Used for determining Average value during switching series termination value. Measurement from differential Group Skew t skew wavefrom *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 4.388MHz 3 Spread Spectrum is off 5 55 Ω 25 ps Electrical Characteristics - HTTCLK PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Output Impedance Z O V O = V 2 55 Ω Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.4 V Output High Current I OH = 2. V -5 ma Output Low Current I OL =.8 V ma Rise/Fall edge rate between Edge Rate t slewr/f 2% 6% 4 V/ns Rise Time t r =.4 V, = 2.4 V.5 2 ns Fall Time t f = 2.4 V, =.4 V.5 2 ns Duty Cycle d t = 5% 45 55 % Group Skew t skew =.5 V 5 ps Jitter, Cycle-to-cycle t jcyc-cyc2b =.5 V 25 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2
ICS954 Electrical Characteristics - REF-4.38MHz PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 Clock period T period 4.38MHz output nominal 69.827 69.855 ns 2 Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.4 V @MIN =. V, Output High Current I OH @MA = 3.35 V -29-23 ma @MIN =.95 V, Output Low Current I OL @MA =.4 V 29 27 ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Rise Time t r =.4 V, = 2.4 V 2 ns Fall Time t f = 2.4 V, =.4 V 2 ns Skew t sk =.5 V 5 ps Duty Cycle d t =.5 V 45 55 % Jitter t jcyc-cyc =.5 V ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 3
ICS954 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS954 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power- On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 4
ICS954 N c INDE AREA e 2 D b E A A E h x 45 -C- - SEATING PLANE. (.4) C L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A 2.4 2.8.95. A.2.4.8.6 b.2.34.8.35 c.3.25.5. D SEE VARIATIONS SEE VARIATIONS E.3.68.395.42 E 7.4 7.6.29.299 e.635 BASIC.25 BASIC h.38.64.5.25 L.5.2.2.4 N SEE VARIATIONS SEE VARIATIONS α 8 8 VARIATIONS D mm. D (inch) N MIN MA MIN MA 48 5.75 6..62.63 Reference Doc.: JEDEC Publication 95, MO-8 3 mil SSOP Package -34 Ordering Information Example: ICS954yFLF-T ICS y F LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 5
ICS954 Revision History Rev. Issue Date Description Page # A 4/22/25. Updated Byte /2 M/N programming description 2. Updated Ordering Information from "Lead Free" to Annealed Lead Free". 3. Preliminary Release. 8-9,5 6