Precision ma to 0mA CURRENT LOOP RECEIVER FEATURES COMPLETE -0mA TO 0-V CONVERSION INTERNAL SENSE RESISTORS PRECISION 0V REFERENCE BUILT-IN LEVEL-SHIFTING ±0V COMMON-MODE INPUT RANGE 0.% OVERALL CONVERSION ACCURACY HIGH NOISE IMMUNITY: db CMR DESCRIPTION The is a precision current-loop receiver designed to convert a 0mA input signal into a 0 V output signal. As a monolithic circuit, it offers high reliability at low cost. The circuit consists of a premium grade operational amplifier, an on-chip precision resistor network, and a precision 0V reference. The features 0.% overall conversion accuracy, db CMR, and ±0V common-mode input range. The circuit introduces only a.v drop at full scale, which is useful in loops containing extra instrument burdens or in intrinsically safe applications where APPLICATIONS PROCESS CONTROL INDUSTRIAL CONTROL FACTORY AUTOMATION DATA ACQUISITION SCADA RTUs ESD MACHINE MONITORING transmitter compliance voltage is at a premium. The 0V reference provides a precise 0V output with a typical drift of ppm/ C. The is completely self-contained and offers a highly versatile function. No adjustments are needed for gain, offset, or CMR. This provides three important advantages over discrete, board-level designs: ) lower initial design cost, ) lower manufacturing cost, and ) easy, cost-effective field repair of a precision circuit. V+ V Ref In 00kΩ 99kΩ 9kΩ.kΩ Rcv f B Ω Rcv Out Ref Out Ω.0kΩ +0V Ref 0 Ref f B Ref Trim 00kΩ 00kΩ Ref Noise Reduction Rcv Com Ref Com International Airport Industrial Park Mailing Address: PO Box 00, Tucson, AZ Street Address: 0 S. Tucson Blvd., Tucson, AZ 0 Tel: (0) - Twx: 90-9- Internet: http://www.burr-brown.com/ FAXLine: (00) - (US/Canada Only) Cable: BBRCORP Telex: 0-9 FAX: (0) 9-0 Immediate Product Info: (00) - 9 Burr-Brown Corporation PDS-E Printed in U.S.A. October, 99
SPECIFICATIONS ELECTRICAL At T = + C and V S = ±V, unless otherwise noted. KP, JP CHARACTERISTICS MIN TYP MAX UNITS GAIN Initial 0. V/mA Error 0.0 0. % of span Error JP Grade 0. % of span vs Temp ppm/ C Nonlinearity () 0.000 0.00 % of span OUTPUT Rated Voltage (I O = +0mA, ma) 0 V Rated Current (E O = 0V) +0, ma Impedance (Differential) 0.0 Ω Current Limit (To Common) +9, ma Capacitive Load 000 pf (Stable Operation) INPUT Sense Resistance.. Ω Input Impedance (Common-Mode) 00 kω Common-Mode Voltage ±0 V CMR () 0 0 db vs Temp (DC) (T A = T MIN to T MAX ) db AC 0Hz 0 db OFFSET LTAGE (RTO) () Initial mv vs Temp 0 µv/ C vs Supply (±.V to ±V) 90 db vs Time 00 µv/mo ZERO ERROR () Initial 0.0 0.0 % of span Initial JP Grade 0. % of span vs Temp 0 ppm of span/ C OUTPUT NOISE LTAGE f B = 0.Hz to 0Hz 0 µvp-p f O = 0kHz 00 nv/ Hz DYNAMIC RESPONSE Gain Bandwidth 0 khz Full Power Bandwidth 0 khz Slew Rate. V/µs Settling Time (0.0%) 0 µs LTAGE REFERENCE Initial 9.99 0.0 V Trim Range () ± % vs Temp ppm/ C vs Supply (±.V to ±V) 0.000 %/V vs Output Current (I O = 0 to +0mA) 0.000 %/ma vs Time ppm/khz Noise (0.Hz to 0Hz) µvp-p Output Current +0, ma POWEUPPLY Rated ± V Voltage Range (), +. ± V Quiescent Current ( = 0V) ma TEMPERATURE RANGE Specification 0 +0 C Operation + C Storage 0 + C Thermal Resistance, θ JA 0 C/W NOTES: () Nonlinearity is the max peak deviation from best fit straight line. () With 0 source impedance on Rcv Com pin. () Referred to output with all inputs grounded including Ref In. () With ma input signal and Voltage Reference connected (includes S, Gain Error, and Voltage Reference Errors). () External trim slightly affects drift. () I O Ref = ma, I O Rcv = ma.
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS () Top View V V+ Rcv fb Rcv Out Rcv Com DIP Supply... ±V Input Current, Continuous... 0mA Input Current Momentary, 0.s... 0mA, % Duty Cycle Common-Mode Input Voltage, Continuous... ±0V Lead Temperature (soldering, 0s)... +00 C Output Short Circuit to Common (Rcv and Ref)... Continuous NOTE: () Stresses above these ratings may cause permanent damage. Ref Com NC Ref Noise Reduction Ref Trim 0 9 Ref In Ref Out Ref fb NC PACKAGE INFORMATION PACKAGE DRAWING PRODUCT PACKAGE NUMBER () KP -Pin Plastic DIP 0 JP -Pin Plastic DIP 0 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PERFORMANCE PRODUCT GRADE PACKAGE KP 0 C to +0 C -Pin Plastic DIP JP 0 C to +0 C -Pin Plastic DIP The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
TYPICAL PERFORMANCE CURVES At T A = + C, V S = ±V, unless otherwise noted. STEP RESPONSE NO LOAD SMALL SIGNAL RESPONSE NO LOAD SMALL SIGNAL RESPONSE R L =, C L = 000pF Positive Common-Mode Range (V) 0 0 0 0 0 POSITIVE COMMON-MODE LTAGE RANGE vs POSITIVE POWEUPPLY LTAGE T A = + C T A = C T A = + C Max Rating = 0V V S = V to 0V 0 9 0. Positive Power Supply Voltage (V) Negative Common-Mode Range (V) 0 0 0 0 0 0 0 NEGATIVE COMMON-MODE LTAGE RANGE vs NEGATIVE POWEUPPLY LTAGE Max Rating = 0V T A = + C T A = C to + C +V S = +.V to +0V 0 0 0 Negative Power Supply Voltage (V) 00 COMMON-MODE REJECTION vs FREQUENCY 00 POWER-SUPPLY REJECTION vs FREQUENCY 90 0 0 CMR (db) 0 PSR (db) 0 V+ V 0 0 00 k 0k 00k Frequency (Hz) 0 0 00 k 0k 00k Frequency (Hz)
THEORY OF OPERATION Refer to the figure on the first page. For 0 to V output with 0mA input, the required transimpedance of the circuit is: UT /I IN = V/mA = 0.V/mA. To achieve the desired output (0V for ma and V for 0mA), the output of the amplifier must be offset by an amount: S = (ma)(0.v/ma) =.V. The input current signal is connected to either or, depending on the polarity of the signal, and returned to ground through the center tap,. The balanced input two matched Ω sense resistors, provides maximum rejection of common-mode voltage signals on and true differential current-to-voltage conversion. The sense resistors convert the input current signal into a proportional voltage, which is amplified by the differential amplifier. The voltage gain of the amplifier is: A D = V/(mA)(Ω) =.V/V. The tee network in the feedback path of the amplifier provides a summing junction used to generate the required.v offset voltage. The input resistor network provides high-input impedance and attenuates common-mode input voltages to levels suitable for the operational amplifier s common-mode signal capabilities. necessary level shifting. If the Ref In pin is not used for level shifting, then it must be grounded to maintain high CMR. GAIN AND OFFSET ADJUSTMENT Figure shows the circuit for adjusting the gain. Increasing the gain of the is accomplished by inserting a small resistor in the feedback path of the amplifier. Increasing the gain using this technique results in CMR degradation, and therefore, gain adjustments should be kept as small as possible. For example, a % increase in gain is typically realized with a Ω resistor, which degrades CMR by about db. A decrease in gain can be achieved by placing matched resistors in parallel with the sense resistors, also shown in Figure. The adjusted gain is given by the following expression UT /I IN = 0. x R X /(R X + ). A % decrease in gain can be achieved with a.kω resistor. It is important to match the parallel resistance on each sense resistor to maintain high CMR. The TCR mismatch between the two external resistors will effect gain error drift and CMR drift. There are two methods for nulling the output offset voltage. The first method applies to applications using the internal 0V reference for level shifting. For these applica- BASIC POWEUPPLY AND SIGNAL CONNECTIONS Figure shows the proper connections for power supply and signal. Both supplies should be decoupled with µf tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. The input signal should be connected to either or, depending on its polarity, and returned to ground through the center tap,. The output of the voltage reference, Ref Out, should be connected to Ref In for the 0kΩ () 0kΩ () R X R X 00Ω () FIGURE. Optional Gain Adjustment. R ±0.% Gain Adjustment Rcv Out NOTE: () Typical values. See text. I IN 0mA Ω Ω +0V Reference Ref In Rcv fb Rcv Out Ref Out 0 Ref f B Ref Trim Ref Noise Reduction (0 V) V+ V µf µf Rcv Com Ref Com FIGURE. Basic Power Supply and Signal Connections.
tions, the voltage reference output trim procedure can be used to null offset errors at the output of the. The voltage reference trim circuit is discussed under Voltage Reference. When the voltage reference is not used for level shifting or when large offset adjustments are required, the circuit in Figure can be used for offset adjustment. A low impedance on the Rcv Com pin is required to maintain high CMR. ZERO ADJUSTMENT Level shifting the output voltage can be achieved using either the Ref In pin or the Rcv Com pin. The disadvantage of using the Ref In pin is that there is an : voltage attenuation from this pin to the output of the. Thus, use the Rcv Com pin for large offsets, because the voltage on this pin is seen directly at the output. Figure shows the circuit used to level-shift the output of the ±0mV adjustment at output. OPA 00kΩ kω +V V 00kΩ FIGURE. Optional Output Offset Nulling Using External Amplifier. using the Rcv Com pin. It is important to use a low-output impedance amplifier to maintain high CMR. With this method of zero adjustment, the Ref In pin must be connected to the Rcv Com pin. MAINTAINING COMMON-MODE REJECTION Two factors are important in maintaining high CMR: () resistor matching and tracking (the internal resistor network does this) and () source impedance. CMR depends on the accurate matching of several resistor ratios. The high accuracies needed to maintain the specified CMR and CMR temperature coefficient are difficult and expensive to reliably achieve with discrete components. Any resistance imbalance introduced by external circuitry directly affects CMR. These imbalances can occur by: mismatching sense resistors when gain is decreased, adding resistance in the feedback path when gain is increased, and adding series resistance on the Rcv Com pin. The two sense resistors are laser-trimmed to typically match within 0.0%; therefore, when adding parallel resistance to decrease gain, take care to match the parallel resistance on each sense resistor. To maintain high CMR when increasing the gain of the, keep the series resistance added to the feedback network as small as possible. Whether the Rcv Com pin is grounded or connected to a voltage reference for level shifting, keep the series resistance on this pin as low as possible. For example, a resistance of 0Ω on this pin degrades CMR from db to approximately 0dB. For applications requiring better than db CMR, the circuit shown in Figure can be used to adjust CMR. PROTECTING THE SENSE RESISTOR The Ω sense resistors are designed for a maximum continuous current of 0mA, but can withstand as much as 0mA for up to 0.s (see absolute maximum ratings). There are several ways to protect the sense resistor from V ZERO ±V adjustment at output. OPA 0 0kΩ 0kΩ +0V Use 0V Ref for + and 0V Ref with INA0 for. = (0.)(I IN ) + V ZERO INA0 0kΩ 0V kω kω OPA kω kω Procedure:. Connect CMV to CT.. Adjust potentiometer for near zero at the output. 00Ω CMR Adjust FIGURE. Optional Zero Adjust Circuit. FIGURE. Optional Circuit for Externally Trimming CMR.
overcurrent conditions exceeding these specifications. Refer to Figure. The simplest and least expensive method is a resistor as shown in Figure a. The value of the resistor is determined from the expression R X = V CC /0mA Ω and the full scale voltage drop is V RX = 0mA x R X. V+ V RX R X 0mA For a system operating off of a V supply R X = Ω and V RX =.V. In applications that cannot tolerate such a large voltage drop, use circuits b or c. In circuit b a power JFET and source resistor are used as a current limit. The 00Ω potentiometer, R X, is adjusted to provide a current limit of approximately 0mA. This circuit introduces a V drop at full scale. If only a very small series voltage drop at full scale can be tolerated, then a 0.0A series fast-acting fuse should be used, as shown in Figure c. For automatic fold-back protection, use the circuit shown in Figure. V+ R X a) R X = (V+)/0mA Ω N90 00Ω 0mA LTAGE REFERENCE The contains a precision 0V reference. Figure shows the circuit for output voltage adjustment. Trimming the output will change the voltage drift by approximately 0.00ppm/ C per mv of trimmed voltage. Any mismatch in TCR between the two sides of the potentiometer will also affect drift, but the effect is divided by approximately. The trim range of the voltage reference using this method is typically ±00mV. The voltage reference trim can be used to trim offset errors at the output of the. There is an : voltage attenuation from Ref In to Rcv Out, and thus the trim range at the output of the receiver is typically ±0mV. The high-frequency noise (to MHz) of the voltage reference is typically mvp-p. When the voltage reference is used for level shifting, its noise contribution at the output of the receiver is typically µvp-p due to the : attenuation from Ref In to Rcv Out. The reference noise can be reduced by connecting an external capacitor between the Noise Reduction pin and ground. For example, 0.µF capacitor reduces the high-frequency noise to about 00µVp-p at the output of the reference and about µvp-p at the output of the receiver. V+ f b) R X set for 0mA current limit at C. 0mA c) f is 0.0A, Lifflefuse Series fast-acting fuse. Request Application Bulletin AB-0 for details of a more complete protection circuit. FIGURE. Protecting the Sense Resistors. 0 V REF 0kΩ ±00mV adjustment at output of reference, and ±0mV adjustment at output of receiver if reference is used for level shifting. FIGURE. Optional Voltage Reference External Trim Circuit.
V LIN I + R V IN I R 0 V REG V+ N +V µf Pt00 00 C to 00 C RTD R LIN 0Ω R Z Ω 0Ω V IN I RET XTR0 B 9 Q 0.0µF E I O I O = ma 0mA 0 µf = 0 to V V R CM = kω 0.0µF NOTE: A two-wire RTD connection is shown. For remotely located RTDs, a three-wire RTD conection is recommended. becomes Ω, R LIN is 00Ω. See Figure and Table I. FIGURE. Used in Conjunction with XTR0 to Form a Complete Solution for -0mA Loop. RTD R LIN R Z R LIN V LIN I + R V IN V IN I RET I R 0 V REG V+ XTR0 9 B E I O Q I O = ma 0mA N 0.0µF NOTE: A three-wire RTD connection is shown. For a two-wire RTD connection eliminate R LIN. 0 µf µf ISO +V Isolated Power 0 from PWS0 V 9 0 V+ 0 V V R CM = kω 0.0µF FIGURE 9. Isolated -0mA Instrument Loop (RTD shown).
0mA 0 () (0 V) 0mA 0 ( 0V) +0V kω 0 +.V OPA +.V 0kΩ () (N) (0 V) =.V (0.) (I IN ) FIGURE. -0mA to -0V Conversion. R CM () I L NOTE: () R CM and are used to provide a first order correction of CMR and Gain Error, respectively. Table gives typical resistor values for R CM and when as many as three s are stacked. Table II gives typical CMR and Gain Error with no correction. Further improvement in CMR and Gain Error can be achieved using a 00kΩ potentiometer for R CM and a 00Ω potentiometer for. R CM (kω) (Ω) 0 00 TABLE. Typical Values for R CM and. R X () Load Power Supply 0V (max) +0V (max) R S R () X (0-V) CMR (db) GAIN ERROR % 9 0.0 0.0 0.00 TABLE II. Typical CMR and Gain Error Without Correction. FIGURE 0. Series -0mA Receivers. R X () Power Supply Load R () C X T (0-V) I L I ( I L MAX NOTE: () R X = / ma ) FIGURE. Power Supply Current Monitor Circuit. I R S = 0. (I I ) Max Gain Error = 0.% (BG) FIGURE. Differential Current-to-Voltage Converter. 9
+V V 00kΩ 99kΩ 9kΩ Ω Ω 00kΩ.0kΩ 00kΩ.kΩ 0.0V Reference 0 0.0V.kΩ UT 0 V +V +V 0kΩ AT&T LH9 Solid-State Relay MΩ 0kΩ 0kΩ Timer µf 0.0µF LM9 0kΩ 0kΩ.9V 0mA Input µf 0Ω kω N90 0.V 0Ω.9kΩ Overrange Output Underrange Output See Application Bulletin AB-0 for more details. FIGURE. -0mA Current Loop Receiver with Input Overload Protection. +V V 0Ω 00kΩ Ω 99kΩ 9kΩ 0-0mA Input 0Ω Ω 00kΩ 00kΩ.0kΩ.kΩ 0.0V Ref 0 0-V See Application Bulletin AB-0 for more details. FIGURE. 0-0mA/0-V Receiver Using. 0