Dual-Frequency GNSS Front-End ASIC Design Ed. 01 15/06/11 In the last years Acorde has been involved in the design of ASIC prototypes for several EU-funded projects in the fields of FM-UWB communications and Radio Front-End development for dual-frequency GPS/Galileo receivers. The following designs are a sample of the work done in GNSS receivers using the UMC 0.18µm MM/RF process for the FP6 and FP7 projects GREAT and GRAMMAR.
FRONT-END DEVELOPMENT Reconfigurable Dual-Frequency Front-End In the frame of the GREAT project a dual-frequency front-end was developed. Two ASICs were designed, one with two LNAs tuned with external SMD inductors at 1176.45MHz and 1575.42MHz (L5/E5a and L1/E1 respectively), and another with the front-end itself. The architecture of the FE is a low-if structure with a single conversion using an integer-n PLL with integrated Quadrature VCO The pair of I/Q mixers is followed by their respective reconfigurable low-pass filters with a variable 3dB-bandwidth between 5 and 12MHz approximately, and variable-gain amplifiers with differential outputs.
FRONT-END DEVELOPMENT Test setup with real GPS signals and measurements Fully-Integrated Dual-Frequency Front-End As the first step of the integration process in the project GRAMMAR all the blocks were implemented on a single chip, as well as 3-bit ADCs.
FRONT-END DEVELOPMENT Dual-Channel Dual-Frequency Front-End The final design in the GRAMMAR project was the integration of two channels in the same chip. Instead of providing I/Q outputs, image rejection filters were designed at IF, with bandwidths of 3MHz and 13MHz (adjustable in about ±30%). The wideband QVCO was replaced by two modified versions, each tuned to its respective band. LNAs with lower power consumption were integrated with the mixers. The functionality of the whole chip has been verified, even though a true characterization of this front-end has not been possible due to two minor design faults. An updated version is to be measured by September 2011. It is expected an overall noise figure of less than 4.5dB with a power consumption under 50mW with both channels active and a sampling frequency of 26MHz. The local oscillator is synthesized with an integer-n PLL accessed through a simple SPI controller, which configures most of the other analog blocks as well.
Description of the main building blocks LNA Operating Frequency range... 1000-1700 MHz (external tuning) Gain... 16-18dB Noise Figure... <1.2dB Input/Output Reference Impedance... 50Ω Power Consumption... <8mW Area... 450x450µm 2 LNA S-parameters measurements with two different matching networks (L1/E1 & L5/E5a)
LNA noise measurements (L1/E1 & L5/E5a) Wideband Quadrature Mixer Frequency... 800-2500MHz* Voltage Gain... 23-25dB (1175MHz-1575MHz) Noise Figure... 8-12dB Quadrature error... <0.5dB / <1º P1dB... -20dBm Input/Output Reference Impedance... 50Ω/1kΩ Power Consumption... 5.7mW Area... 800x1000µm 2 * S11<-10dB. Wider band possible with increased bias current Wideband mixer power gain measurements
Wideband Mixer S 11 (db) measured for different bias voltages Wideband Mixer I/Q outputs sample measurement Low Noise Quadrature Mixer Frequency... 1000-1700MHz (external tuning) Voltage Gain... 32dB Noise Figure... 2.5dB P1dB... -20dBm Input/Output Reference Impedance... 50Ω/1kΩ Power Consumption... 4.7mW Area... 0.6mm 2 This mixer is a low-power low-noise update of the previous design optimized for narrow-band operation. Wideband Quadrature VCO Frequency... 1000-1900MHz* Phase noise... <-112dBc/Hz @ 1MHz Power Consumption... 10mW Load... Capacitive (mixer inputs) Area... 1350x750µm 2 * 16 overlapped intervals of about 100-200MHz each (4-bit digital control)
Wideband QVCO phase noise at L1/E1 and L5/E5a bands L1/E1 Quadrature VCO Frequency... 1575.42MHz* Phase noise... <-110dBc/Hz @ 1MHz Power Consumption... 6mW Load... Capacitive (mixer inputs) Area... 1300x700µm 2 * Tunable in about 200MHz, 1 switched capacitor in the tank to compensate for tolerances L5/E5a Quadrature VCO Frequency... 1176.45MHz* Phase noise... <-110dBc/Hz @ 1MHz Power Consumption... 6.5mW Load... Capacitive (mixer inputs) Area... 1300x700µm 2 * Tunable in about 140MHz, 1 switched capacitor in the tank to compensate for tolerances Fully-Differential VGA 3dB Bandwidth... >18MHz (Max. gain) Gain... 40-70dB (1dB steps) Power Consumption... 2.25mW Area... 800x170µm 2 Input Impedance... 16kΩ Test Load... 400fF VGA gain steps measured at the ADC outputs of the FE (Note ADC saturation)
Fully Differential Complex Band-pass Filters 3dB Bandwidth... 3MHz/13MHz Intermediate Frequency... 3MHz/6.5MHz Ripple... 0.5-0.8dB Image Rejection... 10dB Gain... 6dB Power Consumption... 0.75mW Area... 700x500µm 2 Input Impedance... 25fF Test Load... 100fF Prescaler (Modulus 32/33) Input/Output... CML/1.8V-CMOS Maximum Operation frequency... 2.5GHz Power Consumption... 3mW@2.5GHz... 1.8mW@1.2GHz Test Load... 100fF Area... 50x100µm 2 Other blocks Charge Pump, Phase-Frequency Detector, 3-bit ADC