Electronic-Photonic ICs for Low Cost and Scalable Datacenter Solutions Christoph Theiss, Director Packaging Christoph.Theiss@sicoya.com 1 SEMICON Europe 2016, October 27 2016
Sicoya Overview Spin-off from the TU Berlin 5.7 M federal funding 2008-2016 9 years R&D experience First part of A-round (4.5M ) closed Team of 24 photonics and electronics design engineers/physicists Experienced executive management from global optoelectronics player Embedded into Berlin s photonic network Sicoya is developing Silicon Photonics based application specific IC s and transceivers 2
The Quest for a New Data Center Interconnect Technology Mobile devices the driver for the explosive growth of digital data Global mobile data traffic grew 69% in 2014 In 2015 the digital data traffic was 30 times larger than the total internet in the year 2000 Approximately 497 Million additional mobile devices added to the network in just a year 3
The Three Data Center Challenges + One Data Center Interconnects need Better Energy Efficiency 2x capacity << 2x energy consumption Higher Bandwidth 10G and 40G today to >100G per link Larger Reach beyond 1 km for inter-pod and 40 km for inter datacenter interconnects + Cost of ownership 4
Sicoya s Approach to Silicon Photonics 5
Sicoya s Approach to Silicon Photonics A fully integrated silicon chip that converts electrical data into light pulses Today: $2-3/Gb/s 3 m (copper) 85 mj/gb/s Complex assembly Sicoya: $0.3/Gb/s 2 km (fiber) 25 mj/gb/s Pure chip integration 7x less in cost 3-4x less in power 6
Sicoya s Approach to Silicon Photonics Fab process available with BiCMOS electronics and optics on the same chip based on 9 years in-depth cooperation with IHP as a foundry. A vertical approach to silicon photonics for strongly reduced packaging costs. Library of ultra-small and ultra low power components that allow for miniaturization, cost and power reduction and performance increase. 7
Silicon Photonic Modulators Depletion Modulator p-n diode in reverse bias Fast transition times Low doping - weak effect SiO 2 p Reverse bias n Injection Modulator p-i-n diode in forward bias High doping - strong effect Slow transition times SiO 2 Forward bias p + i n + 8
Sicoya s Unique Silicon Modulator Conventional: Mach-Zehnder modulator Structure: pn, pin, MOS capacitor Data rate: ~40 Gb/s demonstrated Large size: few 100 µm to cm Complicated electrode design Ring modulator Structure: pin, (pn) Data rate: 25 Gb/s demonstrated Small: Ring diameter 5-60 μm Spectrum not reproducible Temperature sensitive Sicoya NMD modulator: Photonic crystal Fabry-Pérot modulator Ultra-small: Resonator length 3-18 μm Data rate: >25 Gb/s 0.06 mm 0.01 mm 1.8 mm Optical attenuation and power consumption scales with size! 9
Sicoya s Node-Matched-Diode Modulator 1D photonic crystal cavity Waveguide width: 450 nm Waveguide height: 220 nm Footprint: < 100 µm² 10
Resonator Modes and Modulation Principle V n λ T on-off modulation 11
Data transmission using Pre-Emphasis Pre-emphasized 25 Gb/s electrical driving signal (NRZ) 25 Gb/s data signal Extinction ratio: 3.6 db Signal / noise ratio: 10.2 Insertion loss: 2-3 db 12
High Speed Germanium Photodetector Responsivity @ λ = 1.55 µm 0.84 A/W for 0 V bias > 1 A/W for -2 V bias Dark current < 100 na for -2 V bias 13 Lischke, S., High bandwidth, high responsivity waveguide-coupled germanium p-i-n photodiode, Opt. Express 23(21), 27213-27220 (2015).
Frequency Response of the Germanium Photodetector Bandwidth > 40 GHz @ 0 Vbias > 67 GHz @ -1 Vbias 14 Knoll, D., High-Performance Photonic BiCMOS Process for the Fabrication of High-Bandwidth Electronic -Photonic Integrated Circuits, Tu15.6. In IEDM, IEEE International Electron Devices Meeting, (2015)
Beam-Forming using Backend-Lenses Lithographically formed backend-lens Cross section through the BEOL 15
Silicon Photonics Integration Approaches Hybrid High packaging cost Electrical performance suffers from parasitics Semi-hybrid Full co-integration Optimal technology choice for pure digital CMOS chip and E/O functions One chip E/O engine Co-packaging with ASIC, µ-processors, gearbox, Ethernet or Infiniband switches Trade-off between optical and electronic performance Complex IC design high design risk 16
3 mm Fully integrated PSM4 100G Transceiver Chip 4 mm 8 cm Waveguides 4x25G Modulators 4x25G PIN Detectors I 2 C Management interface 4x25 Gb/s electrical and optical interfaces Fully integrated modulator driver and trans-impedance amplifier 17
EPIC Cointegration Technology FEOL + BEOL cross-section with bulk (electronic) and local SOI (photonic) areas 1. Metal layer Ge PIN PD EPIC Si-WG Local SOI Bulk Si SiGe:C HBT Si Substrate 18 Knoll, D., Fabrication of High Bit Rate, Monolithically Integrated Receivers in Photonic BiCMOS Technology, IEEE, (2015).
Optical Communication Market $9 billion market by 2021 Market by technology Source: LIGHTCOUNTING 2016 19
Summary Cointegrated solution for optical data center interconnects Vertical chip approach with a unique cost and performance proposition Comprehensive library of 25 Gb/s building blocks for 100Gb/s transceivers. Visions & Perspectives of Sicoya s technology: A scalable solution towards 400 Gb/s, i.e. PAM4 at 56 GBd line rate utilizing linear transmitters and receivers Massively parallel on-board transceivers 20
Acknowledgement Supporting grants: BMBF in the frame of project 03V0381 Silimod BMWi in the frame of project 03EFCBE065 exist BMBF in the frame of project 13N13752 Speed 21
Thank You! Contact: Christoph Theiss, Director Packaging Christoph.Theiss@sicoya.com 22