Scheduling and Communication Synthesis for Distributed Real-Time Systems Department of Computer and Information Science Linköpings universitet 1 of 30
Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions 2 of 30
Embedded Systems General purpose systems Embedded systems Microprocessor market shares in 1999 99% 1% 3 of 30
Distributed Real-Time Systems Safety critical applications (e.g. Drive-by-Wire): timing constraints, data and control dependencies. Communication protocols: Time Triggered Protocol (TTP), Controller Area Network (CAN). Scheduling of processes and communication of messages: guaranteeing timing constraints. 4 of 30
Hardware/Software Codesign Hardware Synthesis System Specification Architecture Selection Partitioning Scheduling Integration Software Synthesis Goals of the thesis: Scheduling... Scheduling of processes and messages for distributed hard real-time applications with control and data dependencies in the context of a given communication protocol. Communication synthesis... Optimization of the parameters of the communication protocol so that the overall system performance is increased and the imposed timing constraints are satisfied. 5 of 30
Related Work Scheduling: Static cyclic non-preemptive scheduling: P. Eles, G. Fohler, D. D. Gajski, H. Kasahara, H. Kopetz, K. Kuchcinski, J. Madsen, J. Xu. Fixed priority preemptive scheduling: J. Axelsson, S. Baruah, A. Burns, J. W. Layland, C. L. Liu, K. Tindell, J. A. Stankovic,, W. Wolf, T. Y. Yen. Communication synthesis: G. Borriello, R. Ernst, H. Hansson, J. Madsen, R. B. Ortega, K. Tindell. 6 of 30
Characteristics and Message Distributed hard real-time applications. Heterogeneous system architectures. Systems with data and control dependencies. Scheduling of processes: Time triggered: Static cyclic non-preemptive scheduling, Event triggered: Fixed priority preemptive scheduling. Communications using the time-triggered protocol (TPP). The performance of the system can be significantly improved by considering the communication protocol and the control dependencies during scheduling. 7 of 30
Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions 8 of 30
Conditional Process Graph (CPG) Subgraph corresponding to D C K P 0 P 1 D P 11 D C P 2 C P 3 C P 2 P 3 P 4 P 5 P 6 P 12 K K P 13 P 7 P 8 P 9 P 8 P 9 P 14 P 16 P 14 P 16 P 15 First processor Second processor ASIC P 10 P 18 P 17 9 of 30
Hardware Architecture Hard real-time distributed systems. Nodes interconnected by a broadcast communication channel. Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface. Communication between nodes is based on the time-triggered protocol. I/O Interface CPU RAM ROM ASIC TTP Controller Node 10 of 30
Time Triggered Protocol Node I/O Interface RAM CPU ROM ASIC TTP Controller H. Kopetz, Technical University of Vienna. Intended for distributed real-time control applications that require high degree of dependability and predictability. Recommended by the X-by-Wire Consortium for use in safety critical applications in vehicles. Integrates all the services required in the design of fault-tolerant distributed real-time systems. S 0 S 1 S 2 S 3 S 0 S 1 S 2 S 3 Slot TDMA Round Cycle of two rounds Bus access scheme: time-division multiple-access (TDMA). Schedule table located in each TTP controller: message descriptor list (MEDL). 11 of 30
Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions 12 of 30
Input Time Triggered Processes Safety-critical application with several operating modes. Each operating mode is modelled by a CPG. The system architecture and mapping of processes to nodes are given. The worst case delay of each process is known. Output Local schedule tables for each node and the MEDL for the TTP controllers. Delay on the system execution time for each operating mode, so that this delay is as small as possible. Note Problem Formulation Processes scheduled with static cyclic non-preemptive scheduling, and messages according to the TTP. 13 of 30
Scheduling Example P 1 P 4 24 ms P 2 P 3 S 1 S 0 m 1 m 2 m 3 m 4 Round 1 Round 2 Round 3 Round 4 Round 5 P 1 P 4 P 1 22 ms Round 1 P 2 P 3 S 0 S 1 m 1 m 2 m 3 m 4 Round 2 Round 3 Round 4 m 1 m 2 P 2 P 3 20 ms P P 4 1 P 2 P 3 S 0 m 1 m 2 m 3 m 4 S 1 Round 1 Round 2 Round 3 m 3 m 4 P 4 14 of 30
Scheduling Strategy 1. The scheduling algorithm has to take into consideration the TTP. Priority function for the list scheduling. 2. The optimization of the TTP parameters is driven by the scheduling. Sequence and lengths of the slots in a TDMA round are determined to reduce the delay. Two approaches: Greedy heuristic, Simulated Annealing (SA). Two variants: Greedy 1 tries all possible slot lengths, Greedy 2 uses feedback from the scheduling algorithm. SA parameters are set to guarantee near-optimal solutions in a reasonable time. 15 of 30
Experimental Results Deviations from the near-optimal schedule lengths obtained by SA: 60 Average Percentage Deviation [%] 50 40 30 20 10 0 80 160 240 320 400 Number of processes Naive Designer Greedy 1 Greedy 2 16 of 30
Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven Systems Real Life Example Conclusions 17 of 30
Input An application modelled using conditional process graphs. Each process has an execution time, a period, a deadline, and a priority. The system architecture and mapping of processes are given. Output Schedulability analysis for systems modelled using CPGs. Schedulability analysis for the time-triggered protocol. The MEDL for the TTP controllers so that the process set is schedulable on an as cheap (slow) as possible processor set. Note Event Triggered Processes Problem Formulation Processes scheduled with fixed priority preemptive scheduling, and messages according to the TTP. 18 of 30
Example P 0 27 P 1 30 P 2 C C 30 P 6 P 9 CPG Worst Case Delays 24 P 4 25 P 3 22 P 7 25 P 10 32 P 11 No conditions Conditions G 1 120 100 19 P 5 P 12 G 2 : 150 G 2 82 82 P 8 G 1 : 200 Deadline: 110 19 of 30
Experimental Results Average Percentage Deviation [%] 100 80 60 40 20 0 Cost function: degree of schedulability 80 160 240 320 400 Number of processes Ignoring Conditions Conditions Separation Relaxed Tightness 1 Relaxed Tightness 2 Brute Force 20 of 30
Average execution time [s] 450 360 270 180 90 0 Experimental Results (Cont.) 80 160 240 320 400 Number of processes Brute Force Ignoring Conditions Relaxed Tightness 2 Conditions Separation Relaxed Tightness 1 21 of 30
Scheduling of Messages over TTP messages are dynamically produced by the processes frames are statically determined by the MEDL m 1 m 2 m 3 m 4 m 5 S 0 Round 1 S 1 Round 2 Round 3 1. Single message per frame, allocated statically: Static Single Message Allocation (SM) 2. Several messages per frame, allocated statically: Static Multiple Message Allocation (MM) 3. Several messages per frame, allocated dynamically: Dynamic Message Allocation (DM) 4. Several messages per frame, split into packets, allocated dynamically Dynamic Packets Allocation (DP) 22 of 30
Average Percentage Deviation [%] 16 12 8 4 0 Experimental Results Cost function: degree of schedulability 80 160 240 320 400 Number of processes Ad-hoc Single Message Dynamic Message Dynamic Packets Multiple Messages 23 of 30
Optimizing Bus Access (SM and MM) p 1 Process p 2 misses its deadline! p 2 p 3 m 1 m 2 p 1 p Swapping m 2 1 with m 2 : all processes meet their deadlines. p 3 m 2 m 1 p 1 p 2 p 3 Putting m 1 and m 2 in the same slot: all processes meet their deadline, the communication delays are reduced. m 1 m 2 24 of 30
OptimizeDM OptimizeDM: Find the slot sizes that maximize the degree of schedulability for each node N i do MinSize Si = max(size of messages m j sent by node N i ) end for for each slot S i BestSize Si = MinSize Si for each SlotSize in [MinSize Si...MaxSize] do calculate the CostFunction if the CostFunction is best so far then end if end for BestSize Si = SlotSize Si size Si = BestSize Si end for end OptimizeDM Initialization: the size of a slot in a TDMA round has to accommodate the largest message sent by the corresponding node. Greedy heuristic: finds the local optimum for each slot. Local optimum: find the best size for this slot, the size that leads to the best so far cost function. 25 of 30
Experimental Results The quality of the greedy optimization heuristics: Average percentage deviations [%] 2 1,5 1 0,5 0 80 160 240 320 400 Number of processes OptimizeSM OptimizeMM OptimizeDM OptimizeDP 26 of 30
Outline Motivation System Model and Architecture Scheduling and Communication Synthesis Time Driven Systems Event Driven System Real Life Example Conclusions 27 of 30
Real Life Example Vehicle cruise controller. Modelled with a CPG of 32 processes and two conditions. Mapped on 5 nodes: CEM, ABS, ETM, ECM, TCM. Time triggered processes: (deadline 400 ms) Ad-hoc: Greedy 1: Greedy 2: SA: 429 ms 314 ms 323 ms 302 ms Event triggered processes: (no messages, deadline 130 ms) Ignoring Conditions: 138 ms Conditions Separation: 132 ms Relaxed Tightness 1, 2: 124 ms Brute Force: 124 ms 28 of 30
Time triggered processes: Conclusions and Future Work Extension to static scheduling for CPGs to handle TTP. Improved schedule quality by using new priority function that considers the time triggered protocol. Significant performance improvements can be obtained by optimizing the access to the communication channel. Event triggered processes: Schedulability analysis with the TTP: four message scheduling approaches compared based on the issue of schedulability. Significant improvements to the degree of schedulability through the optimization of the bus access scheme. The pessimism of the analysis can be drastically reduced by considering the conditions. Mapping of processes and architecture selection. 29 of 30
Contributions Time triggered processes: Static scheduling strategy for systems with both control and data dependencies. Optimization strategies for the synthesis of the bus access scheme. Event triggered processes: Less pessimistic schedulability analysis for hard real-time systems with both control and data dependencies Schedulability analysis for the time-triggered protocol. Optimization strategies for the synthesis of the bus access scheme. 30 of 30