October 13, 2006 Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report (with Optional TEM Analysis) For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Process Review Report Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Embedded SRAM Analysis 5.1 Cell Schematic 5.2 SRAM Plan-View Analysis 6 Materials Analysis 6.1 TEM-EDS Analysis of the Lenses and Optical Layers 6.2 TEM-EDS Analysis of the Inter-level Dielectrics 6.3 TEM-EDS Analysis of the MIM Capacitor 6.4 Transistors and Contacts
Process Review Report 7 ToF-SIMS Analysis of Lenses and Filters 7.1 ToF-SIMS Methodology 7.2 ToF-SIMS Results 8 Critical Dimensions 8.1 Package and Die 8.2 Vertical Dimensions 8.3 Horizontal Dimensions 9 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 MCNEX CIS Assembly Tilt-View 2.1.2 MCNEX CIS Assembly Top-View 2.1.3 MCNEX CIS Assembly Open-View 2.1.4 MCNEX CIS Assembly Bottom-View 2.1.5 MCNEX CIS Assembly Top-View 2.2.1 Die Photograph 2.2.2 Die Markings 2.2.3 Annotated Die Photograph 2.3.1 Die Corner a Intact 2.3.2 Pixel Array Corner Intact 2.3.3 Die Corner a 2.3.4 Die Corner b 2.3.5 Die Corner c 2.3.6 Die Corner d 2.3.7 Minimum Pitch Bond Pads 2.3.8 Single Bond Pad Detail 2.3.9 SRAM Block 2.3.10 Pixel Array Corner 2.3.11 Die Thickness 3 Process 3.1.1 Array Edge General Structure 3.1.2 Peripheral General Structure 3.1.3 Die Edge 3.1.4 Cut-Out and Dielectrics Detail 3.1.5 Organic Spacer Edge 3.1.6 Blue Color Filter Edge 3.2.1 Bond Pad 3.2.2 Bond Pad Edge 3.2.3 Bond Pad Edge Detail 3.3.1 Passivation Oxide 3.3.2 ILD 4 3.3.3 ILD 3 3.3.4 ILD 2 3.3.5 ILD 1 3.3.6 ILD 1 TEM 3.3.7 ILD 1 Detail TEM 3.3.8 PMD and STI 3.4.1 Metal 5 3.4.2 Minimum Pitch Metal 4 3.4.3 Metal 4 Seal TEM 3.4.4 Minimum Pitch Metal 3
Overview 1-2 3.4.5 Minimum Pitch Metal 2 3.4.6 Metal 2 Ta-Based Liner TEM 3.4.7 MIM Capacitors on Metal 1 3.4.8 MIM Capacitor Detail TEM 3.4.9 Minimum Pitch Metal 1 3.4.10 Metal 1 TEM 3.4.11 Metal 1 Ta-Based Liner TEM 3.5.1 Minimum Pitch Via 3s 3.5.2 Minimum Pitch Via 2s 3.5.3 Via 2 TEM 3.5.4 Minimum Pitch Via 1s 3.5.5 Minimum Pitch Contacts to Polysilicon 3.5.6 Contact to Polysilicon TEM 3.5.7 Contact to Polycide TEM 3.5.8 Minimum Pitch Contacts to Substrate 3.5.9 Contact Top TEM 3.5.10 Contact Bottom TEM 3.5.11 Peripheral Contact TEM 3.6.1 Peripheral MOS Transistor (Glass-Etch) 3.6.2 Peripheral NMOS (Si-Etch) 3.6.3 Peripheral PMOS (Si-Etch) 3.6.4 Peripheral Transistor TEM 3.6.5 Peripheral Gate Oxide TEM 3.6.6 Pixel Array NMOS Transistor (Glass-Etch) 3.6.7 Pixel Array NMOS Transistor TEM 3.6.8 Pixel Array NMOS Transistor Spacing TEM 3.6.9 Pixel Array NMOS Gate Oxide TEM 3.7.1 Minimum Width STI 3.7.2 STI TEM 3.7.3 Poly over STI TEM 3.8.1 Peripheral Wells 3.8.2 Peripheral Wells SCM 3.8.3 SRP Peripheral N-Well 3.8.4 SRP Peripheral P-Well 3.8.5 Pixel Array P-Well 4 Pixel Array Analysis 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Lenses 4.2.3 Pixel Array Lenses AFM Tilt-View 4.2.4 Pixel Array Lenses AFM Cross-Section 4.2.5 Pixel Array at Metal 3 4.2.6 Pixel Array at Metal 2 4.2.7 Pixel Array at Metal 1 4.2.8 Pixel Array at Poly
Overview 1-3 4.2.9 Pixel Array at Substrate 4.2.10 Pixel Array at Photocathode SCM 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan-View 4.3.2 Pixel Array General Structure (S1) 4.3.3 Pixel Array Dielectric Structure (S1) 4.3.4 Pixel Array Dielectric Structure TEM (S1) 4.3.5 Sealant Layer over ILD 3-1 TEM (S1) 4.3.6 Pixel Array Bottom Edge (S1) 4.3.7 Pixel Array Top Edge (S1) 4.3.8 Pixel Array Bottom Edge Detail (S1) 4.3.9 Pixel Read Out Transistors (S1) 4.3.10 Lenses and Red Color Filters (S1) 4.3.11 Lenses and Green Color Filters (S1) 4.3.12 Lenses and Blue Color Filters (S1) 4.3.13 Lenses and Color Filters TEM (S1) 4.3.14 Pixel and T1 Transfer Transistor (S2) 4.3.15 T1 Transfer Transistor Detail (S1) 4.3.16 T1 Transfer Transistor Gate Contact (S2) 4.3.17 T1 Transfer Transistor Maximum Length (S1) 4.3.18 T1 Transfer Transistor Edge TEM (S1) 4.3.19 T1 Transfer Transistor Minimum Width (S1) 4.3.20 Pixel Through Transfer Transistors and Pixel SCM (S2) 4.3.21 Transistors T2, T3 and T4 (Glass-Etch; S1) 4.3.22 Transistors T2, T3 and T4 (Si-Etch; S1) 4.3.23 T2 Reset Transistors Length TEM (S1) 4.3.24 T2 Reset Transistor Width (S2) 4.3.25 T3 Source Follower Transistor TEM (S1) 4.3.26 T3 Source Follower Transistor Width (S2) 4.3.27 T4 Row Select Transistor TEM (S1) 4.3.28 T4 Row Select Transistor Width (S2) 4.3.29 T2, T3 and T4 Gate Contacts (S1) 4.3.30 Column Out Contact (S2) 4.3.31 MIM Cap (S1) 4.3.32 MIM Cap (S2) 5 Embedded SRAM Analysis 5.1.1 6T-SRAM Cell 5.2.1 SRAM at Metal 2 5.2.2 SRAM at Metal 1 5.2.3 SRAM at Poly 5.2.4 SRAM at Diffusion
Overview 1-4 6 Materials Analysis 6.1.1 Lens Assembly TEM 6.1.2 TEM-EDS Passivation and Lenses 6.1.3 TEM-EDS Organic Spacer Layers 6.1.4 TEM-EDS Filter A and B 6.1.5 TEM-EDS Pixel Mesa Filler 6.2.1 TEM-EDS ILD 4-2 and ILD 4-1 Dielectrics 6.2.2 TEM-EDS ILD 3-3 and ILD 3-2 Line Dielectrics 6.2.3 TEM-EDS ILD 3-2 and 3-1 Via Dielectrics 6.2.4 TEM-EDS ILD 2-2 and ILD 2-1 Via Dielectrics 6.2.5 TEM-EDS ILD 1-4 and ILD 1-3 Line Dielectrics 6.2.6 TEM-EDS ILD 1-2 and ILD 1-1 Via Dielectrics 6.2.7 TEM-EDS PMD 5 and PMD 4 Dielectrics 6.2.8 TEM-EDS PMD 3, PMD 2 and PMD 1 Dielectrics 6.3.1 TEM-EDS Capacitor Dielectric and Hard Mask 6.3.2 TEM-EDS Capacitor Plates 6.4.1 Transistor EDS Analyses Areas 6.4.2 TEM-EDS Top of Buffer Oxide 6.4.3 TEM-EDS Contact Liner 6.4.4 TEM-EDS Contact Bottom 6.4.5 SEM-EDS Peripheral Transistors 7 ToF-SIMS Analysis of Lenses and Filters 7.2.1 Negative Ion ToF-SIMS Depth Profile 7.2.2 Negative Ion ToF-SIMS Image of Color Filters
Overview 1-5 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.3.1 Package and Die Dimensions 3 Process 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Composition and Thicknesses 3.4.2 Minimum Metal Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 Isolation Horizontal Dimension 3.8.1 Wells and Epi Vertical Dimensions 4 Pixel Array Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 5 Embedded SRAM Analysis 5.2.1 SRAM Transistor Sizes 6 Materials Analysis 6.2.1 Summary of TEM-EDS Analysis Results for Dielectrics and Organic Layers 7 ToF-SIMS Analysis of Lenses and Filters 7.2.1 Summary of Color Filter Composition 8 Critical Dimensions 8.1.1 Package and Die Dimensions 8.2.1 Dielectric Composition and Thicknesses 8.2.2 Metallization Composition and Thicknesses 8.2.3 Transistor and Polysilicon Vertical Dimensions 8.2.4 Wells and Epi Vertical Dimensions 8.3.1 Minimum Metal Horizontal Dimensions 8.3.2 Via and Contact Horizontal Dimensions 8.3.3 Transistor and Polysilicon Horizontal Dimensions 8.3.4 Isolation Horizontal Dimension 8.3.5 Pixel Horizontal Dimensions
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