Applied Electronics II

Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 1 / 29

Overview 1 Introduction 2 The MOS Differential Pair Operation with a Common-Mode Input Voltage Operation with a Differential Input Voltage Large-Signal Operation 3 Small-Signal Operation of the MOS Differential Pair Differential Gain The Differential Half-Circuit The Differential Amplifier with Current-Source Loads Cascode Differential Amplifier Common-Mode Gain and Common-Rejection ratio (CMRR) Differential versus Single-Ended Output Current Source, Biasing Techniques 4 Exercise Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 2 / 29

Introduction Introduction The purpose of a differential amplifier is to amplify the difference between two signals. The differential-pair of differential-amplifier configuration is widely used in IC circuit design. One example is input stage of op-amp. Another example is emitter-coupled logic (ECL). Technology was invented in 1940s for use in vacuum tubes the basic differential-amplifier configuration was later implemented with discrete bipolar transistors. However, the configuration became most useful with invention of modern transistor / MOS technologies. V 1 V 2 Differntial Amplifier V o Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 3 / 29

The MOS Differential Pair The MOS Differential Pair Two matched transistors (Q 1 and Q 2 ) joined and biased by a constant current source I. MOSFET s should not enter triode region of operation. Figure: The basic MOS differential-pair configuration. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 4 / 29

The MOS Differential Pair Operation with a Common-Mode Input Voltage Operation with a Common-Mode Input Voltage Consider case when two gate terminals are joined together. Connected to a common-mode voltage (V CM ). v G1 = v G2 = V CM Q 1 and Q 2 are matched. Current I will divide equally between the two transistors. I D1 = I D2 = I /2, V S = V CM V GS where V GS is the gate-to-source voltage. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 5 / 29

The MOS Differential Pair Operation with a Common-Mode Input Voltage Operation with a Common-Mode Input Voltage Neglecting channel-length modulation, V GS and I /2 are related by I 2 = 1 2 k W n L (V GS V t ) 2 in terms of the overdrive voltage V OV, The voltage at each drain will be I 2 = 1 2 k W n L V OV 2 or V OV = I k n W L v D1 = v D2 = V DD I 2 R D As long as Q 1 and Q 2 remain in the saturation region, the current I will divide equally and the voltages at the drains will not change. Thus the differential pair does not respond to (i.e., it rejects) common-mode input signals. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 6 / 29

The MOS Differential Pair Operation with a Common-Mode Input Voltage Operation with a Common-Mode Input Voltage An important specification of a differential amplifier is its input common-mode range.this is the range of V CM over which the differential pair operates properly. The highest value of V CM is limited by the requirement that Q 1 and Q 2 remain in saturation, which means v DS V OV max(v CM ) = V t + V DD I 2 R D The lowest value of V CM is determined by the need to allow for a sufficient voltage across the current source I for it to operate properly. If a voltage V CS is needed across the current source, then min(v CM ) = V SS + V CS + V t + V OV Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 7 / 29

The MOS Differential Pair Operation with a Differential Input Voltage Operation with a Differential Input Voltage If v id is applied to Q 1 and Q 2 is grounded, following conditions apply: v id = v GS1 v GS2 > 0 i D1 > i D2 if v id is positive, v GS1 will be greater than v GS2 and hence i D1 will be greater than i D2 and the difference output voltage (v D2 v D1 ) will be positive. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 8 / 29

The MOS Differential Pair Operation with a Differential Input Voltage Operation with a Differential Input Voltage The differential pair responds to difference-mode or differential input signals by providing a corresponding differential output signal between the two drains. To find the v id that causes the entire bias current I to flow in one of the two transistors. v GS1 reaches the value that corresponds to i D1 = I, v GS2 is reduced to a value equal to the threshold voltage V t, at which point v S = V t. The v GS1 can be found as I = 1 ( ) k W n (v GS1 V t ) 2 2 L v GS1 = V t + 2I /k n(w /L) = V t + 2V OV Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 9 / 29

The MOS Differential Pair Operation with a Differential Input Voltage Operation with a Differential Input Voltage The corresponding max(v id ) is max(v id )= v GS1 + v S max(v id )= V t + 2V OV V t = 2V OV To steer the current completely to one side of the pair, a difference input voltage v id of at least 2V OV (4V T for bipolar) is needed. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 10 / 29

The MOS Differential Pair Large-Signal Operation Large-Signal Operation Objective is to derive expressions for drain current i D1 and i D2 in terms of differential signal v id = v G1 v G2. Assumption taken Differential pair is perfectly matched Channel-length Modulation is Neglected (λ = 0) The circuit maintains Q 1 and Q 2 in the saturation region of operation at all times. Load Independence Step 1 Expression drain currents for Q 1 and Q 2. i D1 = 1 2 k W n L (v GS1 V t ) 2 and i D2 = 1 2 k W n L (v GS2 V t ) 2 Step 2 Take the square roots of both sides of both 1 id1 = 2 k W n L (v GS1 V t ) and 1 id2 = 2 k W n L (v GS2 V t ) Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 11 / 29

The MOS Differential Pair Large-Signal Operation Large-Signal Operation Step 3 (v GS1 v GS2 = v G1 v G2 = v id ) Subtract and perform appropriate substitution. id1 1 i D2 = 2 k W n L v id Step 4 Squaring both sides and substituting for i D1 + i D2 = I 2 i D1 i D2 = I 1 2 k W n L v id 2 Step 5 Replacing i D2 = I i D1, squaring both sides and solving the quadratic and substituting V OV = I / ( k n W ) L i D1 = I 2 + ( i D2 = I 2 ( I V OV I V OV ) (vid 2 ) (vid 2 ) ( vid /2 1 V OV ) ( vid /2 1 V OV Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 12 / 29 ) 2 ) 2

The MOS Differential Pair Large-Signal Operation Large-Signal Operation The Transfer characteristics are nonlinear due to the term involving v 2 id Figure: Normalized plots of the currents in a MOSFET differential pair. Since Linear amplification is desirable v id will be as small as possible. For a given value of V OV, the only option is to keep v id /2 much smaller than V OV. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 13 / 29

The MOS Differential Pair Large-Signal Operation The approximation is i D1 I 2 + ( I V OV ) (vid 2 ) Large-Signal Operation and i D2 I 2 ( I V OV ) (vid 2 ) Figure: The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of V OV. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 14 / 29

Figure: Small-signal analysis of MOS deferential amplifier. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 15 / 29 Small-Signal Operation of the MOS Differential Pair Small-Signal Operation of the MOS Differential Pair

Small-Signal Operation of the MOS Differential Pair Differential Gain Differential Gain From Figure (a) v G1 = V CM + 1 2 v id and v G2 = V CM 1 2 v id causes a virtual signal ground to appear on the common-source (common-emitter) connection where V CM denotes a common-mode dc voltage where v id denotes a differential input applied complementarily (or balanced) Also note that each of Q 1 and Q 2 is biased at a dc current of I /2 and is operating at an overdrive voltage V OV. Assuming v id /2 V OV, the drain current will be ( ) I (vid ) ( I i d1 = and i d2 = 2 V OV The transconductance of MOSFET is g m = 2I D V OV = Combining the equations ( vid ) i d1 = g m 2 and 2(I /2) V OV = I V OV V OV ( vid ) i d2 = g m 2 ) (vid Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 16 / 29 2 )

Small-Signal Operation of the MOS Differential Pair Differential Gain Differential Gain The output can be taken between the drain and the ground,refereed as single-ended outputs v o1 and v o2. ( vid ) ( vid ) v o1 = i d1 R D = g m R D and v o2 = i d2 R D = g m R D 2 2 The output can e taken between the two drain terminals, refereed as differential output v od v od = v o2 v o1 = g m v id R D The differential gain A v = v od = g m R D v id When the output resistance of the MOSFET is taken into account A v = v od v id = g m [R D r o ] Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 17 / 29

Small-Signal Operation of the MOS Differential Pair The Differential Half-Circuit The Differential Half-Circuit The performance can be determined by considering only half the circuit since the circuit is symmetrical and balanced. It is easier for analysis. Q1 is biased at I /2 and is operating at V OV. This circuit may be used to determine the differential voltage gain of the differential amplifier A v = g m [R D r o ] Figure: Half-circuit of the differential amplifier. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 18 / 29

Small-Signal Operation of the MOS Differential Pair The Differential Amplifier with Current-Source Loads The Differential Amplifier with Current-Source Loads To obtain higher gain, the passive resistances (R D ) can be replaced with current sources. The current sources are realized with PMOS and biased to conduct I /2. A v = g m1 [r o1 r o3 ] Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 19 / 29

Small-Signal Operation of the MOS Differential Pair Cascode Differential Amplifier Cascode Differential Amplifier Gain can be increased via cascode configuration. The differential Gain A v = g m1 [R on R op ] where R on = [g m3 r o3 ]r o1 R op = [g m5 r o5 ]r o7 Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 20 / 29

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 21 / 29

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) In practice there is no ideal current source or symmetrical matching. Non-ideal current source: Assuming the current source have a finite output resistance R SS, and a small common-mode signal v icm is add on V CM. In the ideal case the drain voltage will not change or the common-mode gain is zero. since R SS is very large we can assume Q 1 and Q 2 are operate at a bias current of I/2. v icm = i v icm + 2iR SS and i = g m 1/g m + 2R SS The drain voltage since 2R SS 1/gm R D v o1 = v o2 = R D i = v icm 1/g m + 2R SS v o1 v icm = v o2 v icm R D 2R SS Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 22 / 29

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) v o1 and v o2 are corrupted by v icm,still common-mode signal is rejected v od = v o2 v o1 = 0 Effect of R D Mismatch:Assume Q 1 load is R D and Q 2 load is (R D + R D ). The drain voltage v o1 R D v icm and v o2 R D + R D 2R SS 2R SS Thus v od = v o2 v o1 = R D v icm 2R SS The common-mode gain A cm = v od v icm = R D 2R SS = ( RD 2R SS v icm ) ( ) RD Mismatch in the drain resistances causes the differential amplifier to have a finite common-mode gain. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 23 / 29 R D

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) Common-mode rejection ratio (CMRR) CMMR = A d A cm CMMR for drain resistance mismatch of R D CMMR = 2g mr SS R D /R D For high CMMR R SS Effect of g m Mismatch: Assume g m1 = g m + 1 2 g m, g m2 = g m 1 2 g m from the figure on the next slide ( ) 1 i 1 g m1 = i 2 ( 1 g m2 ) ( and i 1 + i 2 = i 1 1 + g ) m2 g m1 Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 24 / 29

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 25 / 29

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and CMRR Common-Mode Gain and Common-Rejection ratio (CMRR) ( v icm = i 1 /g m1 + (i 1 + i 2 )R SS = i 1 /g m1 + i 1 1 + g ) m2 R SS g m1 rearranging to expressi 1 and i 2 in terms of v icm g m1 v icm g m2 v icm i 1 = and i 2 = 1 + (g m1 + g m2 )R SS 1 + (g m1 + g m2 )R SS The differential output voltage v od = v o2 v o1 = i 2 R D + i 1 R D v od = The common-mode gain (g m1 g m2 )R D 1 + (g m1 + g m2 )R SS v icm = g mr D 1 + 2g m R SS v icm A v = The corresponding CMMR g mr D 1 + 2g m R SS ( RD 2R SS ) ( ) gm CMMR = (2g m R SS )/( g m g m ) Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 26 / 29 g m

Small-Signal Operation of the MOS Differential Pair Differential versus Single-Ended Output Differential versus Single-Ended Output Differential Output: It decreases the common-mode gain and increases the common-mode rejection ratio (CMRR) dramatically It increases the differential gain by a factor of 2 (6 db) because the output is the difference between two voltages of equal magnitude and opposite sign. Single-Ended Output: Needed to connect it to an off-chip load. Advantage of Differential Amplifier: The differential transmission of the signal on the chip also minimizes its susceptibility to corruption with noise and interference. Enables us to bias the amplifier and to couple amplifier stages together without the need for bypass and coupling capacitors. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 27 / 29

Small-Signal Operation of the MOS Differential Pair Current Source, Biasing Techniques Current Source, Biasing Techniques The current source is implemented using a current mirror. Q 3 and Q 4 is the current mirror implementation. Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 28 / 29

Exercise Exercise The following questions in the text book are exercises to be done for the tutorial session. 8.1 8.6 8.17 8.21 8.25 Reading Assignment BJT Differential Amplifier Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 29 / 29