Engineer-to-Engineer Note EE-297 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil processor.support@nlog.com or processor.tools.support@nlog.com for technicl support. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors Contributed by Joe B. Rev. 3 November 21, 2007 Introduction This EE-Note discusses the methodology for estimting totl verge power consumption of ADSP- BF534, ADSP-BF536, nd ADSP-BF537 Blckfin embedded processors. The ADSP-BF536 Blckfin processor is low-power derivtive of the ADSP-BF537 processor nd is referred to s low-power processor in this document. The ADSP-BF537 processors cn run t fster internl clock speeds nd re referred to s high-performnce processors in this document. The ADSP-BF534 processor cn be either low-power (400 MHz models) or high-performnce (500 MHz models). The term Blckfin refers to ll vritions of processors ddressed by this document. Power estimtes re bsed on chrcteriztion dt mesured over power supply voltge, core frequency (CCLK), nd junction temperture (T J ). The intent of this document is to ssist bord designers in estimting their power budget for power supply design nd therml relief designs using Blckfin processors. These processors feture dynmic power mngement control, llowing the regultion of pplied core voltge (V DDINT ) from n externl I/O source (V DDEXT ). The rnges for these supplies differ depending on the prt being used. The totl power consumption of the Blckfin processor is the sum of the power consumed for both of the power supply domins, V DDINT nd V DDEXT. Plese consult the following sections of the ADSP-BF534/ADSP-BF536/ADSP-BF537 Blckfin Embedded Processor Dt Sheet [1] for detils specific to discussions throughout this EE-Note: See the Recommended Operting Conditions section for detils regrding V DDINT nd V DDEXT rnges. See the Timing Specifictions section for detils regrding required V DDINT vlues to support the desired CCLK. See the Ordering Guide section for comprehensive list of the vrious speed nd temperture grde models vilble for ADSP-BF534, ADSP-BF536, nd ADSP-BF537 Blckfin processors. Copyright 2007, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.
Estimting Internl Power Consumption The totl power consumption due to internl circuitry (on the V DDINT supply) is the sum of the sttic power component nd dynmic power component of the processor s core logic. The dynmic portion of the internl power depends on the instruction execution sequence, the dt opernds involved, nd the instruction rte. The sttic portion of the internl power is function of temperture nd voltge; it is not relted to processor ctivity. Anlog Devices provides current consumption figures nd scling fctors for discrete dynmic ctivity levels. System ppliction code cn be mpped to these discrete numbers to estimte the dynmic portion of the internl power consumption for Blckfin processors in given ppliction. Internl Power Vector Definitions The following power vector definitions define the dynmic ctivity levels tht pply to the internl power vectors shown in Tble 1. I DD-IDLE - V DDINT supply current for idle ctivity. Idle ctivity is the core executing the IDLE instruction only, with no core memory ccesses, no DMA, nd no interrupts. I DD-NOP - V DDINT supply current for no-op ctivity. No-op ctivity is the core executing the NOP instruction only, with no core memory ccesses, no DMA, nd no interrupts. This is useful mesurement for softwre-implemented dely loops. I DD-APP - V DDINT supply current for specific ppliction s ctivity. This ctivity is the core executing n ppliction comprised of 30% dul-mac instructions nd 70% lod-store nd no-op instructions. All instructions nd dt re locted in L1 SRAM, nd peripherls re not enbled. I DD-TYP - V DDINT supply current for typicl ctivity. Typicl ctivity is the core executing n ppliction comprised of 75% dul-mac instructions nd 25% dul-alu instructions. All instructions nd dt re locted in L1 SRAM, nd peripherls re not enbled. This is the test vector used for the dissiption numbers found in the dt-sheet. I DD-HIGH - V DDINT supply current for high ctivity. High ctivity is the core executing n ppliction comprised entirely of dul-mac instructions. All instructions nd dt re locted in L1 SRAM, nd peripherls re disbled. I DD-PEAK - V DDINT supply current for pek ctivity. Pek ctivity is the core executing 100% dul-mac instructions fetched from internl memory, with memory DMA moving dt pttern from L1 Dt A memory to L1 Dt B memory. The bit pttern toggles ll bits in ech ccess. The test code used to mesure I DD-PEAK represents worst-cse processor opertion. This ctivity level is not sustinble under norml ppliction conditions. Estimting I DDINT Dynmic Current, I DD-DYN There re two steps required to estimte dynmic power consumption due to internl circuitry (i.e., on the V DDINT supply). The first step is to determine the dynmic bseline current, nd the second step is to determine the percentge of ctivity for ech discrete power vector with respect to the entire ppliction. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 2 of 15
I DD Bseline Dynmic Current, I DD-BASELINE-DYN The grph for the Blckfin processors bseline dynmic current (I DD-BASELINE-DYN ) is shown in Figure 1. The I DD-BASELINE-DYN vlue is derived using the I DD-TYP dynmic ctivity level vs. core frequency. Ech curve in the grph represents bseline I DDINT dynmic current for specified power supply setting. Using the curve specific to the ppliction, I DD-BASELINE-DYN for the V DDINT power supply domin cn be estimted t the CCLK of the processor in the ppliction. For exmple, with V DDINT t 1.2 V nd CCLK t 400 MHz, the corresponding I DD-BASELINE-DYN for the V DDINT power supply domin would be pproximtely 120 ma. ADSP-BF534/6/7 Idd Dynmic Typicl (I DD-BASELINE-DYN ) 250.00 Current (ma) 200.00 150.00 100.00 50.00 1.40V 1.35V 1.30V 1.25V 1.20V 1.15V 1.10V 1.05V 1.00V 0.95V 0.90V 0.85V 0.80V 0.00 0 100 200 300 400 500 600 700 Core Clock Frequency (MHz) Figure 1. Bseline I DDINT Dynmic Current Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 3 of 15
I DD Dynmic Current Running Your Appliction Tble 1 lists the scling fctors for ech ctivity level, which re used to estimte the dynmic current for ech specific ppliction. With knowledge of the progrm flow nd n estimte of the percentge of time spent t ech ctivity level, system developers cn use I DD-BASELINE-DYN vlues shown in Figure 1 nd the corresponding ctivity scling fctors (ASF) from Tble 1 to determine the dynmic portion of the internl current (I DD-DYN ) for ech Blckfin processor in system. Power Vector I DD-PEAK 1.33 I DD-HIGH 1.29 I DD-TYP 1.00 I DD-APP 0.88 I DD-NOP 0.72 I DD-IDLE 0.43 Tble 1. Internl Power Vectors nd Dynmic Scling Fctors Activity Scling Fctor (ASF) The dynmic current consumption for Blckfin processor in specific ppliction is clculted ccording to Eqution 1, where % is the percentge of the overll time tht the ppliction spends in tht stte: Eqution 1. Internl Dynmic Current (I DD-DYN ) ( % Pek ctivity level x I DD-PEAK ASF x I DD-BASELINE-DYN ) ( % High ctivity level x I DD-HIGH ASF x I DD-BASELINE-DYN ) ( % Typ. ctivity level x I DD-TYP ASF x I DD-BASELINE-DYN ) ( % App. ctivity level x I DD-APP ASF x I DD-BASELINE-DYN ) ( % NOP ctivity level x I DD-NOP ASF x I DD-BASELINE-DYN ) + ( % Idle ctivity level x I DD-IDLE ASF x I DD-BASELINE-DYN ) Totl Dynmic Current for V DDINT (I DD-DYN ) For exmple, fter profiling the ppliction code for prticulr system, ctivity is determined to be proportioned s shown in Figure 2. Figure 2. Internl System Activity Levels (10% Pek Activity Level) (20% High Activity Level) (50% Typ. Activity Level) (10% App. Activity Level) (10% NOP Activity Level) + (0% Idle Activity Level) 100% Activity Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 4 of 15
Using the ASF provided for ech ctivity level in Tble 1 (nd with V DDINT t 1.2 V nd CCLK t 400 MHz), vlue for the dynmic portion of the internl current consumption of single processor cn be estimted s follows: Figure 3. Internl Dynmic Current Estimtion (10% x 1.33 x 120) (20% x 1.29 x 120) (50% x 1.00 x 120) (10% x 0.88 x 120) (10% x 0.72 x 120) + (0% x 0.43 x 120) I DD-DYN = 112.82 ma = ~113 ma The totl estimted dynmic current on the V DDINT supply in this exmple is ~113 ma. Estimting I DDINT Sttic Current, I DD-DEEPSLEEP Deep Sleep mode for Blckfin processors is when power is pplied to the core nd L1 memories, but ll clocks re turned off. In this mode, the sttic current (I DD-DEEPSLEEP ) mesurement cn be tken, which is the sttic component of overll verge dissiption. Grphs for I DD-DEEPSLEEP for the Blckfin processors re shown in Figure 4 (high-performnce processors) nd in Figure 5 (low-power processors). Sttic current on the V DDINT power supply domin is function of junction temperture (T J ) nd voltge, but it is not function of frequency or ctivity level. Therefore, unlike the dynmic portion of the internl current, I DD-DEEPSLEEP need not be clculted for ech discrete ctivity level or power vector. Using the I DD-DEEPSLEEP curve corresponding to the ppliction (i.e., t specific V DDINT ), I DD-DEEPSLEEP cn be estimted vs. T J of the Blckfin processor. Appendix A discusses the methodology for estimting T J. This process involves knowing the totl power profile for the processor; therefore, this process will be itertive to rrive t finl clcultion for expected power dissiption. For exmple, in n ppliction with V DDINT t 1.2 V nd high-performnce Blckfin processor t T J of +100 o C, the corresponding I DD-DEEPSLEEP for the V DDINT power supply domin would be pproximtely 375 ma. Similrly, in n ppliction with V DDINT t 1.2 V nd low-power Blckfin processor t T J of +100 o C, the corresponding I DD-DEEPSLEEP for the V DDINT power supply domin would be pproximtely 100 ma. The sttic power of the Blckfin processor is constnt for given voltge nd temperture. Therefore, it is simply dded to the totl estimted dynmic current when clculting the totl power consumption due to the internl circuitry of the Blckfin processor. Note tht the I DD-DEEPSLEEP currents shown in Figure 4 nd Figure 5 represent the worse-cse sttic current s mesured cross the wfer fbriction process for highperformnce nd low-power devices, respectively. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 5 of 15
Figure 4. High-Performnce I DD_DEEPSLEEP Sttic Current Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 6 of 15
Figure 5. Low-Power I DD_DEEPSLEEP Sttic Current Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 7 of 15
Estimting Totl I DDINT Current The totl current consumption due to the internl core circuitry (I DDINT ) is the sum of the dynmic current component nd the sttic current component, s shown in Eqution 2. Eqution 2. Internl Core Current (I DDINT ) Clcultion I DDINT = I DD-DYN + I DD-DEEPSLEEP Continuing with the exmple of the Blckfin processor operting t 1.2 V nd 400 MHz (nd with the code s profiled), ssume tht the resulting T J is estimted to be +100 o C. The totl I DDINT consumed by the high-performnce processor core under these conditions would be: Eqution 3. I DDINT Estimtion (High-Performnce) I DDINT = 113 + 379 = 492 ma The sme estimte for the low-power processor core would be: Eqution 4. I DDINT Estimtion (Low-Power) I DDINT = 113 + 141 = 254 ma Totl Estimted Internl Power, P DDINT The resulting internl power consumption (P DDINT ) is given by Eqution 5. Eqution 5. Internl Power (P DDINT ) Clcultion P DDINT = V DDINT x I DDINT Using Eqution 5, the totl estimted internl power consumed by the high-performnce processor in the ppliction described in this exmple would be: Eqution 6. P DDINT Estimtion (High-Performnce) P DDINT = 1.20V x 492 ma = 590 mw The sme estimte for the low-power processor would be: Eqution 7. P DDINT Estimtion (Low-Power) P DDINT = 1.20V x 254 ma = 305 mw Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 8 of 15
Estimting Externl Power Consumption Externl power consumption (on the V DDEXT supply) is dependent on the enbled peripherls in given system. Ech unique group of peripherl pins contributes to piece of the overll externl power, bsed upon severl prmeters: O - The number of output pins tht switch during ech cycle f - The mximum frequency t which the output pins cn switch V DDEXT - The voltge swing of the output pins C L - The lod cpcitnce of the output pins U - The utiliztion fctor (the percentge of time tht the peripherl is on nd running) In ddition to the input cpcitnce of ech device connected to n output, the totl cpcitnce (C L ) should include the cpcitnce of the processor pin itself (C OUT ), which is driving the lod. Eqution 8 shows how to clculte the verge externl current (I DDEXT ) using the bove prmeters: Eqution 8. Externl Current (I DDEXT ) Clcultion I DDEXT = O x f/2 x V DDEXT x C L x U The worst-cse externl pin power scenrio occurs when the lod cpcitor chrges nd dischrges continuously, requiring the pin to toggle ech cycle. Since the stte of the pin cn chnge only once per cycle, the mximum toggling frequency is f/2. In terms of supply power, the worst-cse V DDEXT vlue is 3.6 V. Tble 2 contins dt for relistic exmple of PPI ppliction, which runs severl peripherls simultneously. Actul results my vry, but gin, the intent of this document is to help designers size the power supplies. Estimted verge externl power consumption (P DDEXT ) cn be clculted s follows. Eqution 9. Externl Power (P DDEXT ) Clcultion P DDEXT = V DDEXT x I DDEXT Using the smple Blckfin system configurtion in Figure 6, the externl current nd, therefore, the externl power consumption cn be estimted. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 9 of 15
Figure 6. Blckfin System Smple Configurtion I DDEXT (Eqution 8) cn be clculted for ech clss of pins tht cn drive, s shown in Tble 2. Peripherl Freq (Hz) # of pins C/pin (F) Toggle Rtio Util Vddext (V) Pout @ 3.6V (mw) PPI 27.00E+06 9 30.00E-12 1 1.00 3.6 47.24 SPORT0 4.00E+06 2 30.00E-12 1 1.00 3.6 1.56 SPORT1 4.00E+06 2 30.00E-12 1 1.00 3.6 1.56 UART 115.00E+03 2 30.00E-12 1 0.25 3.6 0.01 SDRAM 133.33E+06 36 30.00E-12 0.25 0.50 3.6 116.35 Totl Externl Power Dissiption @ 3.6 V (est. mw) 166.71 Tble 2. Smple Clcultion for Totl Averge Externl Power In the bove exmple, the totl verge externl power consumption is estimted to be ~165 mw. This number ws obtined with the prmeters listed in Tble 2 by pplying Eqution 10. The chosen operting frequencies re resonble for ech of the peripherls, including the mximum llowed SDRAM frequency of 133.33 MHz. This model ssumes tht ech output pin chnges stte every clock cycle, which is worst-cse model, except in the cse of the SDRAM (becuse the number of output pins trnsitioning ech clock cycle will be less thn the mximum number of output pins). Tble 2 ws tken from the Externl Power Spredsheet [2], which is ssocited with this EE-Note. It contins clcultions for four smple systems. The reder cn tilor this spredsheet to the ppliction, dding or deleting rows s necessry. Since the eqution provides results in Wtts (W), n dditionl multiplier of 1000 in the spredsheet converts results into mw. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 10 of 15
This eqution is more theoreticlly ccurte version of the one used in the spredsheet: P ext = V 2 DDext C L All Output Pins f Eqution 10. Alternte Externl Power (P DDEXT ) Clcultion Rther thn estimting verge externl power dissipted in ech peripherl, the estimte pplies to ech individul output pin, bsed on the pin s lod cpcitnce nd verge toggling frequency. The voltge swing is uniform cross ll output pins within the V DDEXT supply domin, so it is multiplied by the summtion of the dynmic chrge chnges on ech output. Using the PPI dt in Tble 2, nine output pins chnge every cycle t n verge frequency of 27 MHz. Since toggling between on-to-off nd off-to-on requires two cycles, F AVG (13.5 MHz) is hlf the PPI clock. Since ech pin chnges t the sme rte nd the pin cpcitnce is presumed to be the sme, the summtion is simply nine times the vlue of ny one PPI pin. Applying Eqution 10: 2 P EXT_AVG = V DDEXT * 9 pins * (F AVG * C L ) = (3.6) 2 * 9 * 13.5e6 * 30e-12 = 12.96 * 0.003645 = 0.047239W = 47.239mW As cn be seen, the vlue derived using this eqution is the sme s the vlue estimted in Tble 2. This model obtins the sme estimte on per-pin bsis rther thn per-peripherl bsis. In ddition to the peripherl pins, there is one other output pin on Blckfin processors tht will contribute to the V DDEXT supply domin power profile if the system uses crystl to provide the CLKIN signl to the processor. In this cse, the processor drives the XTAL output pin when the PLL is ctive. The output drive frequency will be exctly the CLKIN rte, nd the pin cpcitnce vlue cn be obtined from the pproprite dt-sheet. Note tht the voltge swing will likely be less thn V DDEXT for most crystls, nd using V DDEXT in computtions would be worst-cse model in terms of profiling power dissiption. Finlly, designers must be mindful of power supply efficiency when sizing the V DDEXT supply. Switching Regultor Design Considertions for ADSP-BF533 Blckfin Processors (EE-228) [3] describes the internl voltge regultor. Rel-Time Clock (RTC) Power Consumption The finl source of totl power consumption comes from the optionl third power domin, the Rel-Time Clock (RTC) power domin (V DDRTC ), which is specified vlue. The RTC cn be powered between 2.25 V nd 3.6 V. For worst-cse nlysis, supply voltge of 3.6 V yields current drw, I DDRTC, of 30 to 50 μa for rnge of mbient temperture from 25 o C to 85 o C. For the ske of including this number in the finl power consumption estimte, the power dissipted in the RTC domin, P DDRTC is: Eqution 11. Totl Power (P DDRTC ) Clcultion P DDRTC = V DDRTC x I DDRTC Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 11 of 15
Knowing this vlue helps in selecting bttery s potentil power source for the RTC. The RTC cn be used to tke the Blckfin processor out of ny low-power operting mode. Hving bttery supply V DDRTC llows the removl of the V DDINT nd V DDEXT supplies, thus significntly reducing totl verge power consumption. As worst-cse exmple, P DDRTC is 180 μw, which is the product of the mximized V DDRTC (3.6 V) nd the high end of the I DDRTC rnge (50 μa) provided in the dt sheet. Totl Power Consumption For given system, totl power consumption is the sum of its individul components - power consumed by internl circuitry, power consumed due to switching I/O pins, nd power consumed by the RTC circuitry, s follows: Eqution 12. Totl Power (P TOTAL ) Clcultion Where: P TOTAL = P DDINT + P DDEXT + P DDRTC P DDINT = Internl power consumption s defined by Eqution 5 P DDEXT = Externl power consumption s defined by Eqution 9 P DDRTC = RTC power consumption s defined by Eqution 11 For exmple, ssuming tht the processor in Figure 6 is operting under the conditions detiled in the exmple (the processor operting t 1.2 V, 400 MHz, nd code s profiled in Figure 2), nd lso ssuming tht the resulting T J hs been estimted to be +100 o C (see Appendix A for estimting T J ), the totl estimted power consumed for the high-performnce processor would be: P TOTAL = 590 mw + 166.71 mw + 0.18 mw = ~757 mw Figure 7. Totl Power (P TOTAL ) Clcultion for Smple Shown in Figure 6 While Running Code Described in Eqution 6 for High-Performnce Processors Similrly, the totl estimted internl power consumed by the low-power processor under these sme conditions would be: P TOTAL = 305 mw + 166.71 mw + 0.18 mw = ~472 mw Figure 8. Totl Power (P TOTAL ) Clcultion for Smple Shown in Figure 6 While Running Code Described in Eqution 7 for Low-Power Processors Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 12 of 15
Conclusion Severl vribles ffect the power requirements of n embedded system. Mesurements published in the Blckfin processor dt sheets re indictive of typicl prts running under typicl conditions. However, these numbers do not reflect the ctul numbers tht my occur for given processor under non-typicl conditions. In ddition to the type of silicon tht the customer could hve, the mbient temperture, core nd system frequencies, supply voltges, pin cpcitnces, power modes, ppliction code, nd peripherl utiliztion contribute to the verge totl power tht my be dissipted. The verge power estimtes obtined from methods described in this EE-Note indicte how much the Blckfin processor lods power source over time. These estimtes re useful in terms of expected power dissiption within system, but designs must support worst-cse conditions under which the ppliction cn be run. Do not use this clcultion to size the power supply, s the power supply must support pek requirements. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 13 of 15
Appendix A For Blckfin processors, the totl power budget is limited by the mximum llowed junction temperture (T J ) of the device. Plese see the processor dt sheet for the mximum T J specifiction. To gurntee correct opertion, ensure tht T J does not exceed the mximum T J specifiction. Use the following eqution to determine T J of the device while on the ppliction s printed circuit bord (PCB): Where: T J = T T + (P TOTAL x ψ JT ) Eqution 13. Junction Temperture (T J ) Clcultion T T = Pckge temperture ( C) mesured t the top center of the pckge P TOTAL = Totl power consumption (W) s defined in Eqution 12 ψ JT = Junction-to-top (of pckge) chrcteriztion prmeter ( C/W) Under nturl convection, ψ JT for thin plstic pckge is reltively low. This mens tht under nturl convection conditions, the typicl T J is just little higher thn the temperture t the top-center of the pckge (T T ). The die is physiclly seprted from the surfce of the pckge by only thin region of plstic mold compound. Unless the top of the pckge is forcibly cooled by significnt irflow, there will be very little difference between T T nd T J. However, note tht ψ JT is ffected by irflow nd vlues for ψ JT under vrious irflow conditions, nd PCB design configurtions re listed in the Therml Chrcteristics section of the Blckfin processor dt sheets for the 182-bll mini-bga nd the 208-bll sprse mini- BGA pckges. The Therml Chrcteristics section of the respective dt sheet lso provides therml resistnce (θ JA ) vlues for ll vilble pckges. Dt sheet vlues for θ JA re provided for pckge comprison nd PCB design considertions only nd re not recommended for verifying T J on n ctul ppliction PCB. Industril pplictions of the mini-bga pckge require therml vis to n embedded ground plne on the PCB. Refer to JEDEC stndrd JESD51-9 for printed circuit bord therml bll lnd nd therml vi design informtion. Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 14 of 15
References [1] ADSP-BF534/ADSP-BF536/ADSP-BF537 Blckfin Embedded Processor Dt Sheet. Rev. D, September 2007. Anlog Devices, Inc. [2] Externl Power Spredsheet. Associted file with Estimting Power for ADSP-BF534/ADSP-BF536/ADSP-BF537 Blckfin Processors (EE-297). Rev 3, November 2007. Anlog Devices, Inc. [3] Switching Regultor Design Considertions for ADSP-BF533 Blckfin Processors (EE-228). Rev 1, Februry 2005. Anlog Devices, Inc. Document History Revision Rev 3 November 21, 2007 by Joe B. Rev 2 My 18, 2007 by Joe B. Rev 1 September 6, 2006 by Joe B. Description Clrified ADSP-BF534 processor offering s either low-power or highperformnce Updted to include full power chrcteriztion dt Initil Relese Estimting Power for ADSP-BF534/BF536/BF537 Blckfin Processors (EE-297) Pge 15 of 15