102726 Design of nalog and Mixed Theory Exercises Francesc Serra Graells http://www.cnm.es/~pserra/uab/damics paco.serra@imb-cnm.csic.es 1 Introduction to the Design of nalog Integrated Circuits 1.1 The characterization engineer of a CMOS foundry has measured the following I/V transfer curve for a 10µm/10µm NMOSFET operating in saturation (V D >V Dsat ) and room temperature (27 C). Can you extract the equivalent subthreshold slope (n), current factor (β) and threshold voltage (V T H ) of its EKV analytical model? damics-exercises F. Serra Graells 1/11
1.2 ssuming a CMOS technology with the design rules and process parameters given below, estimate the required area to integrate a 50kΩ serpentine-type resistor for each of the available design layers. Width Spacing Res. Layer [µm] [µm] [Ω/ ] N-well >5 >4 1k P-Diff >0.5 >0.5 100 HiPo >1 >1 1k Metal >0.3 >0.3 10m 1.3 Compare the area efficiency of triple MIM versus fringing metal capacitors for a CMOS technology with the following characteristics: SiO 2 oxide (ɛ r =3.9), 35nm MIM oxide thickness, 0.2µm metal spacing and width, 1µm metal thickness (drawing not to scale). Vias contribution to fringing capacitance can be neglected. 1.4 For a switched-capacitor circuit, two matched MIM devices of C 1 =10pF and C 2 =50pF are required. a Taking into account the maximum allowed size for a single MIM structure is 900µm 2, and the area and perimeter density is 1fF/µm 2 and 200aF/µm respectively, choose the suitable unitary capacitor element size. b How many of the above unitary capacitors would be required to implement C 1 and C 2? Draw the overall array of unitary elements and choose their distribution to optimize technology matching between the two capacitors. c Supposing a Pelgrom s Law parameter of C =0.4%µm, what would be the maximum relative mismatching between C 1 and C 2 for the 99.7% of IC samples? 2/11 F. Serra Graells damics-exercises
1.5 n integrated Opmp exhibits the following open-loop static and dynamic curves while consuming 1mW under 100pF load conditions: a Which Opmp parameters can you extract from the above graphs? What approximate values can you measure for them? b ccording the the following figure of merit, another Opmp circuit is performing 1F/J. Which of the two designs would you choose? F OM. = C load GW P D 1.6 The datasheet of an Opmp shows GW =1MHz, SR=±1V/µs and CMR=2V pp. If the circuit is configured as a follower: a Calculate the maximum operable frequency at CMR full scale and compare it to the given GW. b What is the maximum input amplitude for the follower at GW frequency? Compare to CMR. 1.7 ssume an Opmp block operated as follower and stimulated with step input at time t 1. Given the black-box specifications SR + and GW, obtain the analytical expression for the output waveform V out (t) from t 1 to t 2 under the following qualitative cases (find also the case condition for each one): a Slew-rate only limited. b Settling time only limited. c General case. damics-exercises F. Serra Graells 3/11
2 Single Satge Opmps 2.1 The following single-transistor Opamp is being integrated in CN5 CMOS technology (i.e. β = 59 W L µ/v2 and n = 1.5, while λ = 0.2V 1 for L = 3µm): a Is working in strong inversion (above threshold)? b Calculate G(DC). How will this value change in case I bias and (W/L) 1 are doubled? c Draw the equivalent ode plot indicating values for W and GW. What would happen under same changes as in b? d Considering thermal noise only and ideal full scale, find the equivalent number of bits (ENO) required by the DC at the output of the Opmp. 2.2 For the following single stage amplifier topologies, with all transistors working in strong inversion and saturation and all bulk terminals connected to their respective power supply rails: a Develop the analytical expressions of voltage DC gain and output range for each case as a function of design parameters (W/L) 1, (W/L) 2, I bias, R S and V DD. b Which of them are inverting amplifiers? Which of them can be considered Opmps? 2.3 Given the fully-differential single-stage Opmp shown below to be integrated in CN5 technology (i.e. β = 59 W L µ/v2 and n = 1.5, while λ = 0.2V 1 for L = 3µm): 1 M5 : : a If we want to achieve 1 1 M7 CMRR = g mg1,2 2 g mg1,2 ( ) 2ngmg1,2 + 1 > 80d, g md4 1 : 2 what is the maximum mismatching in % of the input pair transconductance acceptable for I bias = 10µ, (W/L) all = 15 and L all = 6µm? b In the event of dealing with 5% mismatching due to area restrictions, how would you compensate it by design in order to reach the target CMRR? 4/11 F. Serra Graells damics-exercises
2.4 Taking the Opmp of previous exercise, a CMF loop based on resistive dividers is added to stabilize the output common-mode level at V ref = V DD /2: a Choose the correct sign of the feedback Opmp to ensure CMF stability. b Compare the expression of Opmp differential output range with and without this control loop. c Find the design constraint to avoid any losses in the output range due to CMF. M5?? M7 R1 R2 M8 M9 2.5 Classic, cascode and regulated cascode current sources with I bias =10µ, (W/L)= 30µm 3µm and G reg=50 are designed for CN5 technology (V T H =1V, β = 59 W L µ/v2, n = 1.5 and λ L 3µm = 0.2V 1 ): a Calculate the output resistance of each current source. b Obtain the minimum output voltage to operate them and find the optimum value for V ref. c Draw a comparative plot of their output I/V curves. 2.6 Imagine you are designing a single-stage single-ended double-cascode Opmp as shown here: M5 a Find the optimal matching ratios between transistors in order to maximize the voltage output range. Can you generalize the matching rule for N-cascode topologies? b What is the expression of the output resistance and DC voltage gain compared to the single-transistor Opmp? damics-exercises F. Serra Graells 5/11
2.7 Consider the following folded Opmp with cross-coupled transconductance boosting to be integrated in CN5 technology (i.e. V T H =30mVµm). If all transistors are sized at (W/L)=10 and I bias =10µ: 1 : 1 : 1/N 1/N : 1 : 1 a uild a table with the required N ratios for +6d, +12d and +18d gain improvements. b What is the minimum device area to ensure technology mismatching causes σ( G) 3d? M7 M8 M5 M9 0 3 Multi-Stage Opmps 3.1 two-stage Opmp with Miller frequency compensation is being designed for CN5 CMOS technology (i.e. β N,P = {59, 20} W L µ/v2, n = 1.5, λ L 3µm = 0.2V 1 ): 1 : 1 a Calculate the equivalent capacitance seen from the output of the first stage for C comp =1pF. b What is the maximum load capacitance C load allowed to ensure phase margin m φ 60 for any passive feedback configuration? 1 : 1 : 10 3.2 For the following differential to single ended two-stage Miller Opamp to be optimized for CN5 technology (i.e. β N,P = {59, 20} W L µ/v2, n = 1.5, λ L 3µm = 0.2V 1 ): a Define the minimum set of design variables for device sizing and biasing. M8 M7 M5 b Find a complete solution to verify G(DC) 60d, GW 1MHz, SR± 1.5V/µs and mφ 60 for C load =10pF. 6/11 F. Serra Graells damics-exercises
4 Full-Custom nalog Design Methodology 4.1 n expert layout designer proposes the following physical array structure for a differential pair, whose two transistors ( and ) are segmented in 6 unitary and squared elements: a Demonstrate that this array structure does not exhibit a common centroid. b Propose an alternative arrangement compliant with common centroid guidelines. 4.2 Find the best common centroid array for a multiple current mirror with scaling ratios 1:2:4:4 and squared-shape unitary transistor elements. lso, consider the use of dummy elements. 4.3 For the following inverter amplifier with linear gain 3: a Draw a common-centroid array for both resistors in case of squared unitary elements, i.e. (L/W ) u =1. b Same as in previous point but for (L/W ) u =4. 4.4 Given the 3-to-4 times scaled resistors shown below, where metal resistivity can be neglected: a Compute matching ratios R 3 /R 1 and R 4 /R 2. b Which layout style ensures more accurate scaling? 4.5 switched-capacitor circuit requires a 2:1 PiP capacitors for a CMOS technology with overlap and fringing capacitances C ua =0.42fF/µm 2 and C up =0.041fF/µm, respectively. a What are the real matching ratios C 2 /C 1 and C 3 /C 1? b Propose a 2C 1 shape element. single damics-exercises F. Serra Graells 7/11
5 Low-Power Opmps 5.1 For the Class- telescopic Opmp shown below with both differential pairs biased in weak inversion: M5 a Obtain the analytical expression of the output current as a function of the differential input voltage when the output voltage is centered. b Compare to the classic differential pair with single ended output. 5.2 Supposing weak inversion operation for the following 4-transistor loop, demonstrate the Translinear Principle: in a closed loop containing an even number of translinear elements (TEs) with an equal number of them arranged clockwise and counter-clockwise, the product of the currents through the clockwise TEs equals the product of the currents through the counter-clockwise TEs. 5.3 rail-to-rail Opmp operating in strong inversion incorporates the following 3-times current control circuit to equalize input transconductance: a What is the maximum deviation of g in? b t which V inc values are g in peaks located? c Plot the corresponding g in (V inc ) curve. 8/11 F. Serra Graells damics-exercises
5.4 The following cascode Opamp is designed to be integrated in CN5 CMOS technology (i.e. β = 59 W L µ/v2 and n = 1.5, while λ = 0.2V 1 for L = 3µm) with I bias =10µ, (W/L) 1,2 =60µm/6µm and V DD =+5V: a Design the equivalent two-stage inverter-based Opmp to obtain the same G(DC) and GW for φ m =60. b Compare the output full-scale and current consumption of both circuit topologies. 6 Opmp pplication Examples 6.1 Given the instrumentation amplifier shown below: a Obtain the analytical expression of V out as a function of V inp and V inn. b Supposing perfect matching between. R 2 R 2 = R2 and overall voltage gain of 10, what is the maximum relative deviation between R 1 and R 1 to ensure CMRR > 60d? 6.2 Imagine a variable-gain amplifier, based on MOS resistive circuits (MRC), is going to be integrated in CN5 CMOS technology (i.e. V T H = 1V, β = 59 W L µ/v2 and n = 1.5). a If (W/L)=60µm/6µm, calculate the required V tun1 for an overall voltage gain of 10. b What differential input full-scale value can the resulting circuit handle? c Can this circuit be operated with an input common mode level different from ground? damics-exercises F. Serra Graells 9/11
7 Integrated Data Converters 7.1 Given the following integrated data converter circuits: a flash DC with 8-bit dynamic range at 1GS/s consuming 10mW (DC1), a 12-bit SR DC at 12MHz clock frequency draining 50µ from 1.8V supply (DC2), and a Σ modulator based DC performing 100d SNDR max for 50kHz bandwidth and 10mW power consumption (DC3), a Which of them are performing best according to Schreier and Walden figures of merit? b Can any of them be considered as a state-of-art /D converter? 7.2 flash DC with 1V pp input full-scale and 8-bit resolution is being designed for its integration in CN5 CMOS technology with process parameters V T H =30mVµm, ɛ ox =3.9ɛ o and t ox =38nm: a Estimate the minimum area (W L) of the comparators input MOS transistors, so bubble can not occur at ±2 thermal code distance. For simplification purposes, use the following triangular probability distribution and assume uncorrelated stochastic processes: b For the above case, what is the probability of having bubbles? capacitance? What is the total DC input c ccepting bubble can only occur at ±1 thermal code distance, design the bubble error correction (EC) logic at gate level and verify its behavior with 0 and 1 bubble examples. 7.3 Taking the general block scheme of a 5-bit SR DC: a Represent the equivalent state machine diagram for the digital SR block. S/H b Following the above graph, plot the waveform of DC feedback V dac for V in =0.34375V F S. c What is the resulting output code d out? Flash DC SR logic 5 10/11 F. Serra Graells damics-exercises
7.4 For a 10-bit integrate-and-fire DC operating at 1kS/s sampling rate: a Calculate the maximum INL for a spike reset time of t spike =10µs. b Which is the maximum spike reset time allowed to keep INL below 0.5LS? 0 time 7.5 Consider the design of a 15-bit delta-sigma DC with 2nd-order 1-bit single-loop architecture: a Compute the minimum OSR required. b What will be the improvement in dynamic range if sampling frequency is doubled? c How many levels will require the quantizer to compensate for halving the sampling frequency? damics-exercises F. Serra Graells 11/11