Quad High-Speed Precision Difet OPERATIONAL AMPLIFIER FEATURES WIDE BANDWIDTH:.MHz HIGH SLEW RATE: V/µs LOW OFFSET: ±µv max LOW BIAS CURRENT: ±pa max LOW SETTLING:.µs to.% STANDARD QUAD PINOUT APPLICATIONS PRECISION INSTRUMENTATION OPTOELECTRONICS SONAR, ULTRASOUND PROFESSIONAL AUDIO EQUIPMENT MEDICAL EQUIPMENT DETECTOR ARRAYS DESCRIPTION The is a high performance monolithic Difet (dielectrically-isolated FET) quad operational amplifier. It offers an unusual combination of verylow bias current together with wide bandwidth and fast slew rate. In +V CC Noise, bias current, voltage offset, drift, and speed are superior to BIFET amplifiers. Laser-trimming of thin-film resistors gives very low offset and drift the best available in a quad FET op amp. +In Cascode put The 's input cascode design allows high precision input specifications and uncompromised highspeed performance. Standard quad op amp pin configuration allows upgrading of existing designs to higher performance levels. The is unity-gain stable. Simplified Circuit (Each Amplifier) V CC Difet, Burr-Brown Corp. BIFET, National Semiconductor Corp. International Airport Industrial Park Mailing Address: PO Box Tucson, AZ Street Address: S. Tucson Blvd. Tucson, AZ Tel: () - Twx: 9-9- Cable: BBRCORP Telex: -9 FAX: () 9- Immediate Product Info: () - 9 Burr-Brown Corporation PDS-F Printed in U.S.A. August 99
SPECIFICATIONS ELECTRICAL At V CC = ±VDC and T A = + C unless otherwise noted. AG, KP, KU () BG SG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT NOISE Voltage: f O = Hz * * nv/ Hz f O = Hz 9 * * nv/ Hz f O = khz * * nv/ Hz f O = khz * * nv/ Hz f B = Hz to khz. * * µvrms f B =.Hz to Hz.9 * * µvp-p Current: f B =.Hz to Hz * * fa, p-p f O =.Hz thru khz. * * fa/ Hz OFFSET VOLTAGE Input Offset Voltage V CM = VDC ± ±mv * ± * * µv KP, KU ± ±.mv µv Average Drift T A = T MIN to T MAX ± * * µv/ C KP, KU ± µv/ C Supply Rejection ±V CC = V to V * * * db KP, KU db Channel Separation Hz, R L = kω * * db BIAS CURRENT Input Bias Current V CM = VDC ± ± * ± * * pa KP, KU ± ± pa OFFSET CURRENT Input Offset Current V CM = VDC. * * * pa KP, KU. pa IMPEDAE Differential * * Ω pf Common-Mode * * Ω pf VOTAGE RANGE Common-Mode Input Range ±. +, * * * * V Common-Mode Rejection V IN = ±VDC 9 * * * db KP, KU db OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L kω 9 * * * db FREQUEY RESPONSE Gain Bandwidth Gain =. * * * MHz Full Power Response Vp-p, R L = kω * * khz Slew Rate V O = ±V, R L = kω * * * V/µs Settling Time:.% Gain =, R L = kω. * * µs.% C L = pf, V Step. * * µs RATED OUTPUT Voltage put R L = kω ±. +.,. * * * * V Current put V O = ±VDC ± ± * * * * ma put Resistance MHz, Open Loop * * Ω Load Capacitance Stability Gain = + * * pf Short Circuit Current ± ± ± * * * * * * ma POWER SUPPLY Rated Voltage ± * * VDC Voltage Range, Derated Performance ± ± * * * * VDC Current, Quiescent I O = madc 9 * * * * ma TEMPERATURE RANGE Specification Ambient Temperature + * * + C KP, KU + C Operating Ambient Temperature + * * * * C KP, KU + C Storage Ambient Temperature + * * * * C KP, KU + C θ Junction-Ambient * * C/W KP, KU / C/W *Specifications same as AG. NOTE: () KU may be marked U. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At V CC = ±VDC and T A = T MIN to T MAX unless otherwise noted. AG, KP, KU BG SG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS TEMPERATURE RANGE Specification Range Ambient Temperature + * * + C KP, KU + C INPUT OFFSET VOLTAGE Input Offset Voltage V CM = VDC ± mv * ±.mv ± ±.mv µv KP KU ± ±. mv Average Drift ± * * µv/ C KP, KU ± µv/ C Supply Rejection 9 * 9 db BIAS CURRENT Input Bias Current V CM = VDC ± ± * ± ± ±na pa OFFSET CURRENT Input Offset Current V CM = VDC *.na pa VOLTAGE RANGE Common-Mode Input Range ± ±.,. * * ± +.,. V Common-Mode Rejection V IN = ±VDC 99 * db KP, KU 99 db OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L kω 9 * db RATED OUTPUT Voltage put R L = kω ±. ±.9,. * * ± +.,. V Current put V O = ±VDC ± ±9 * * * ± ma Short Circuit Current V O = VDC ± ± ± * * * * * * ma POWER SUPPLY Current, Quiescent I O = madc 9.. * * 9. ma * Specification same as AG. ORDERING INFORMATION TEMPERATURE MODEL PACKAGE RANGE KP -Pin Plastic DIP C to + C KU () -Pin Plastic SOIC C to + C AG -Pin Ceramic DIP C to + C BG -Pin Ceramic DIP C to + C SG -Pin Ceramic DIP C to + C NOTE: () KU may be marked U. ABSOLUTE MAXIMUM RATINGS Supply... ±VDC Internal Power Dissipation ()... mw Differential Input Voltage ()... ±VDC Input Voltage Range ()... ±VDC Storage Temperature Range... P, U = C/+ C, G = C/+ C PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER () KP -Pin Plastic DIP KU () -Pin Plastic SOIC AG -Pin Ceramic DIP 9 BG -Pin Ceramic DIP 9 SG -Pin Ceramic DIP 9 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. () KU may be marked U. Operating Temperature Range.. P, U = C/+ C, G = C/+ C Lead Temperature (soldering, s)... C SOIC (soldering, s)... + C put Short-Circuit Duration ()... Continuous Junction Temperature... + C NOTES: () Packages must be derated based on θ JC = C/W or θ JA = C/W. () For supply voltages less than ±VDC the absolute maximum input voltage is equal to: V > V IN > V CC V. See Figure. () Short circuit may be to power supply common only. Rating applies to + C ambient. Observe dissipation limit and T J. PIN CONFIGURATION Top View U (SOIC) Package Top View G or P (DIP) Package A D A D In A In D In A A D In D + In A A D +In D + In A +In D + V CC V CC + V CC +In B In B B C V CC +In C 9 In C +In B In B B B C +In C In C C B C 9
DICE INFORMATION PAD FUTION put A Input A +Input A +V CC +Input B Input B put B PAD FUTION put C 9 Input C +Input C V CC +Input D Input D put D Substrate Bias: V CC : No connection MECHANICAL INFORMATION MILS (.") MILLIMETERS 9 Die Size x ±. x. ±. Die Thickness ±. ±. Min. Pad Size x. x. Backing None DIE TOPOGRAPHY TYPICAL PERFORMAE CURVES T A = + C, V CC = ±VDC unless otherwise noted. INPUT CURRENT NOISE SPECTRAL DENSITY POWER SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE Current Noise (fa/ Hz) CMR and PSR (db) 9 PSR CMR. k k k M 9 + + + + + Temperature ( C) k TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT khz vs SOURCE RESISTAE na BIAS AND OFFSET CURRENT vs TEMPERATURE na E O Voltage Noise, E O (nv/ Hz) R S + Resistor Resistor noise only Bias Current (pa) na Bias Current Offset Current na Offset Current (pa) k k k M M M Source Resistance ( Ω). + + + + + Ambient Temperature ( C).
TYPICAL PERFORMAE CURVES (CONT) T A = + C, V CC = ±VDC unless otherwise noted. BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE POWER SUPPLY REJECTION vs FREQUEY Bias Current (pa). Bias Current Offset Current. Offset Current (pa) Power Supply Rejection (db) +.. + + + Common-Mode Voltage (V) k k k M M COMMON-MODE REJECTION vs FREQUEY COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE Common-Mode Rejection (db) Common-Mode Rejection (db) 9 k k k M M + + + Common-Mode Voltage (V) Voltage Gain (db) OPEN-LOOP FREQUEY RESPONSE R L = kω C L = pf A OL Ø 9 Phase Shift (Degrees) Gain Bandwidth (MHz) GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE GBW Slew Rate Slew Rate (V/µs) k k k M M + + + + + Ambient Temperature ( C)
TYPICAL PERFORMAE CURVES (CONT) T A = + C, V CC = ±VDC unless otherwise noted. GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE OPEN-LOOP GAIN vs TEMPERATURE A V = + Gain Bandwidth (MHz) R L = kω GBW Slew Rate (V/µs) Voltage Gain (db) 9 Slew Rate Supply Voltage (±V CC ) + + + + + Ambient Temperature ( C) MAXIMUM OUTPUT VOLTAGE SWING vs FREQUEY LARGE SIGNAL TRANSIENT RESPONSE put Voltage (Vp-p) R L = kω put Voltage (V) k k M M Time(µs) put Voltage (mv) SMALL SIGNAL TRANSIENT RESPONSE Time(µs) Settling Time (µs).%.% SETTLING TIME vs CLOSED-LOOP GAIN R L = kω C L = pf k Closed-Loop Gain (V/V)
TYPICAL PERFORMAE CURVES (CONT) T A = + C, V CC = ±VDC unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE CHANNEL SEPARATION vs FREQUEY Supply Current (ma) 9 Channel Separation (db) R L = R L = kω + + + + + Ambient Temperature ( C) k k k TOTAL HARMONIC DISTORTION vs FREQUEY.kΩ A V = +V/V OPEN-LOOP GAIN vs SUPPLY VOLTAGE Ω.Vrms THD + N (% rms).. kω A V = +V/V Voltage Gain 9 A V = +V/V. Test Limit. k k k 9 Supply Voltage (±V CC ) k INPUT VOLTAGE NOISE SPECTRAL DENSITY Voltage Noise (nv/ Hz) k k k M
APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The offset voltage is laser-trimmed and will require no further trim for most applications. If desired, offset voltage can be trimmed by summing (see Figure ). With this trim method there will be no degradation of input offset drift. In / GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce hum pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the bias current of the. To avoid leakage, utmost care must be used in planning the board layout. A guard pattern should completely surround the high impedance input leads and should be connected to a low-impedance point which is at the signal input potential. (See Figure ). V Non-Inverting Buffer Ω kω kω ±mv Offset Trim +V FIGURE. Offset Voltage Trim. In In INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-tosubstrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of V CC. Unlike BIFET amplifiers, the Difet requires input current limiting resistors only if its input voltage is greater than volts more negative than V CC. A kω series resistor will limit the input current to a safe value with up to ±V input levels even if both supply voltages are lost. (See Figure and Absolute Maximum Ratings). Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. Input Current (ma) + + V I IN INPUT CURRENT vs INPUT VOLTAGE WITH ±V CC PINS GROUNDED Maximum Safe Current Maximum Safe Current In Inverting For input guarding, guard top and bottom of board. FIGURE. Connection of Input Guard. HANDLING AND TESTING Measuring the unusually low bias current of the is difficult without specialized test equipment; most commercial benchtop testers cannot accurately measure the bias current. Low-leakage test sockets and special test fixtures are recommended if incoming inspection of bias current is to be performed. To prevent surface leakage between pins, the DIP package should not be handled by bare fingers. Oils and salts from fingerprints or careless handling can create leakage currents that exceed the specified bias currents. If necessary, DIP packages and PC board assemblies can be cleaned with Freon TF, baked for minutes at C, rinsed with de-ionized water, and baked again for minutes at C. Surface contamination can be prevented by the application of a high-quality conformal coating to the cleaned PC board assembly. + + + Input Voltage (V) FIGURE. Input Current vs Input Voltage with ±V CC Pins Grounded.
BIAS CURRENT CHANGE vs COMMON-MODE VOLTAGE The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure ). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the is not compromised by common-mode voltage. Input Bias Current (pa) T A = + C; curves taken from mfg. published typical data AD LF LF/ LF AD OP-// + + + Common-Mode Voltage (VDC) LF/ FIGURE. Input Bias Current vs Common-Mode Voltage. APPLICATIONS CIRCUITS Figures through are circuit diagrams of various applications for the. In Zero Operate kω Ω kω MΩ / kω Polypropylene µf / FIGURE. Auto-Zero Amplifier. Gain = V OS < µv Drift.µV/ C Zero Droop µv/s Referred to Input pf kω Input () IN9 / MΩ () () IN9 N /.µf Polstyrene Droop.mV/s put NOTE: () Reverse polarity for negative peak detection. FIGURE. Low-Droop Positive Peak Detector. 9
/ Differential Input E E MΩ R put = µa/v I O Load I O = (E E ) /R INA FIGURE. Voltage-Controlled Microamp Current Source. <pf to prevent gain peaking Pin Photodiode UDT Pin-A Guard MΩ +V.µF.µF /.µf put x V/W MΩ V Circuit must be well shielded. FIGURE. Sensitive Photodiode Amplifier. / kω R F kω kω Guard + Input / 9 R G / Ω / R G / Ω Guard A V = µv/v I B pa R IN Ω BW khz Differential Voltage Gain = + (R F /R G ) / R F kω kω kω FIGURE 9. FET Instrumentation Amplifier with Shield Driver.
In µf 9.kΩ.kΩ A.µF µf.kω.kω B.µF µf.kω.9kω 9 C.µF µf.kω kω Gain = +V/V db/octave, Hz LPF Butterworth Response D.µF FIGURE. -Pole Hz Low-Pass Filter..kΩ.kΩ.kΩ.kΩ In A B C D kω kω kω kω A V = + BW khz Gain-Bandwidth MHz FIGURE. Wide-Band Amplifier.
PACKAGE DRAWINGS