DRAM & Flexible RRAM This Week s Subject p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor CMOS Logic Inverter NAND gate NOR gate CMOS Integration & Layout GaAs MESFET (JFET) 1 Flexible Inorganic Semiconductor Technology
DRAM (Dynamic Random Access Memory) Schematic DRAM Chip Architecture: Memory Cell Array Col. Dec. Col. Dec. Row Decoder Row Decoder Row Decoder Row Decoder PAD Col. Dec. Col. Dec. 2 RAS (row access strobe) Supplementary
DRAM cell (Or Display) Word line Transfer gate [access] 1cm Storage node Bit line + + + + ---- Capacitor (or OLED ) Periphery circuits Cell array (core) 3cm DRAM: I/O gate, CMOS TR Data sense/amplifier Data read Data refresh Random access: row decoder Select word line column decoder Select bit line Need to refresh the charge loss in the capacitor (μsec) Display (LCD or OLED): Active Matrix: with transistor in each cell. Fast speed, Large pixel 3 Passive Matrix: w/o transistor. Slow respond speed(~250msec), small pixel
p-channel MOSFET Circuit diagram Gate electrode Source electrode Drain electrode Gate -I DS Transfer curve (Id-Vg curve) Vd=-1V Source (p + ) Drain (p + ) Gate oxide n-type Si substrate p-channel MOSFET (PMOS) Id-Vd curve - - - - 0V -V Th =-0.5V -1.8V -V G - 4 -
CMOS Logic (Inverter) Complementary Metal Oxide Semiconductor: NMOS+PMOS Inverter : building block of integrated circuits Reference 1, 0 Pull-up PMOS 0, 1 Pull-down NMOS Reference (Ground) Vin Vout 5 Vgn=Vin Vdsn=Vout Vtn=-Vtp Vgp=Vin-Vdd Vdsp=Vout-Vdd 0 1 1 0
CMOS Logic (Inverter) 1.8V digital 1 0V digital 0 Reference(1.8V) Vgp=Vin-Vdd 1.8V 1.8V Vgp= 0V Vgn=1.8V Vtp=-0.5V off Vtn=0.5V on Pull down by NMOS 0V 100 Ohm 1 Ohm 0V Reference (Ground) Digital 1 is inverted to digital 0 6
CMOS Logic (Inverter) 1.8V digital 1 0V digital 0 Reference(1.8V) Vgp=Vin-Vdd 1.8V 0V Vgp= -1.8V Vgn=0V Vtp=-0.5V on Vtn=0.5V off Pull up by PMOS 1.79V 1 Ohm 1.79V 100 Ohm Reference (Ground) Digital 0 is inverted to digital 1 7
CMOS Logic (NAND Gate) V DD Pull-up PMOS Pull-down NMOS Pull-down NMOS The output is high when either of inputs A or B is high, or if neither is high. In other words, it is normally high, going low only if both A and B are high. 8
CMOS Logic (NOR Gate) V DD Pull-up PMOS Pull-up PMOS Pull-down NMOS The output is high only when neither A nor B is high. That is, it is normally high but any kind of non-zero input will take it low. 9
CMOS Inverter Layout 10 Ref: CMOS VLSI Design, N.Weste, Addison Wiley,
CMOS Inverter Mask Layout 11
a) Starting Material Dopant type : p-type (boron) Orientation : (100) Resistivity : 13±2 Wafer size : 4 inch b) Initial oxidation Temperature : 1000C 130min. Thickness : 6000±6000Å d) Well mask PR coat, soft bake Align, Exposure Develop, Hard bake Mask 1 12 e) Oxide etch 7:1 BHF 6min f) P/R strip Acetone, IPA, DI wafer g) Well implantation Ion species : P + Dose : 3.6x10 12 /cm 2 Energy : 120keV
(h) (i) (j) i) Gate oxidation Temperature : 950 C, 31min. Thickness : 250±20Å i) Poly deposition Temperature : 625 C Thickness : 3500±300Å j) Gate mask P/R coat, soft bake Align, Exposure Develop, CD check Hard bake j) Poly etch RIE (Plasma etching) Mask 2 (k) k) Oxide Growth l) N+ S/D implantation Ion species : As + Dose : 5x10 15 /cm 2 Energy : 80keV (l) 13 Mask 3
(m) (n) Repeats using p+ diffusion mask Mask 4 (o) o) N+ S/D implantation Ion species : BF 2 + Dose : 3x10 15 /cm 2 Energy : 40keV (p) p) Contact etch RIE : CHF 3 +CF 4 +Ar Mask 5 14
(r) r) Metal deposition Target : Al-1% Si Thickness : 0.7 m r) Metal etch Reactant gas : BCl 3 +Cl 2 RIE Mask 6 15
GaAs MESFET MESFET (Metal Semiconductor Field Effect Transistor): one type of JFET(junction field effect transistor) N type GaAs Normally III-V Sc, High mobility, frequency device Si Ge GaAs InAs n (cm 2 /Vs) 1400 3900 8500 30000 p (cm 2 /Vs) 470 1900 400 500 16
Normally off MESFET (enhancement mode) 17
Flexible Single Crystal Silicon from SOI Si (100 nm) BOX Very thin and flexible High performance similar to Si VLSI technology Well established technology Appl. Phys. Lett. 84, 5398 (2004) 18
Large Area, Selective Transfer of µs-si using PDMS Stamp Contact PDMS stamp µs-si on SOI wafer 1 cm Sacrificial SiO 2 layer 10 mm Mother substrate PET 100 µm 20 cm Transfer µs-si from stamp to PET Remaining SOI wafer 19 Adv. Mater. 17, 2336, 2005
High Performance Device on Plastic Substrate I DS (ua) 300 250 200 150 100 µ= 520 cm 2 /Vs, on/off=10 6 V th = 0.7 V O n 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 I ds (A) 50 0 Off -6-4 -2 0 2 4 6 V GS (V) V ds =0.1V 1E-8 1E-9 1E-10 Appl. Phys. Lett. 90, 213501, 2007 IEEE Elect. Device Letters. 27, 460, 2006 20
Flexible III-V HEMTs Si-doped AlGaAs - Undoped GaAs (Chap 5.8) Id-Vd Id-Vg Journal of Applied Physics, 100, 124507 2006
Flexible 3D Heterogeneous Integration Direct transfer of µs-sc 15 µm µs-gan on Si wafer 3D direct integration Heterogeneous 3D integration on Plastics µs-sc 500 µm Nature Materials, 5, 33, 2006 Science, 314, 1754, 2006 22
Why Flexible Memory? Storage Memory (Essential element) Processing Communication 23 Flexible Electronic Systems
Memristor, Missing Fundamental Circuit Element Resistive Random Access Memory (RRAM) First proposed in 1971 Neuromophic Systems. D. Strukov et al., Nature, 453, 80, 2008 Kim, K. IEEE Tech. Dig. IEDM, 1-4, 2010. 24 Jo, S.H et al. Nano Lett. 10, 1297, 2010
Prior Research of Flexible Resistive Memory Titinium oxide Aluminum oxide Cross-point structure (No switching elements) Graphene oxide GeO/HfO N Cell-to-cell interference Require high performance switching transistor Nanotechnol, APL, Nano Letter, Adv. Mater. 2010 25 (µ> 200 cm 2 /Vs)
Flexible one transistor-one memristor (1T-1M) memory 26 Nano Lett., 11(12), 5438, 2011
1T-1M Structure Circuit Diagram V SET = -2.1 V, V SET = 2.7 V ON/OFF ratio of 50 at -0.5 V (V READ ) 27 Nano Lett., 11(12), 5438, 2011
Random Access Operation 28 Nano Lett., 11(12), 5438, 2011
Flexible LSI for Implantable Devices 29 Using 0.18µm CMOS ACS Nano, 7, 4545, 2013
Electrical Properties of Flexible Devices RFICs (RF Switches) G S G Input Port M1 M2 Output Port G S G 200 μm 30 Stable Operations on Plastics ACS Nano, 7, 4545, 2013
Roll to Roll ACF Packaged Flexible NAND Flash Memory Adv. Mater. 28, 8371, 2016
Flexible NAND Flash Memory Unit Cell Operation Read voltage Transfer Curve Endurance Retention Adv. Mater. 28, 8371, 2016
Flexible one selector-one resistor (1S1R) memory Adv. Mater. 26, 7480, 2014
Flexible Crossbar Memory using ILLO Adv. Mater. 26, 7480, 2014
Flexible Oxide TFTs using ILLO TFT structure IZO thickness of 20 nm GI thickness of 176 nm Adv. Func. Mater. 26, 6170, 2016
Flexible Oxide TFTs using ILLO Transfer Curve Output Curve On glass On plastic μ* (cm 2 /Vs) 37.3 36.8 Negative Bias (-20 V) SS (V/dec) 0.31 0.32 V on (V) -0.6-0.7 ΔV (V) 0.015 0.017 *@ 15 V Adv. Func. Mater. 26, 6170, 2016
Self-Structured Nano-filament for Phase Change Memory ACS Nano 9, 6587, 2015
Comparison between ILED and OLED ILED(Inorganic) OLED(Organic) Merits Stability High efficiency(2x OLED) Long lifetime(50x OLED) Merits Flexibility Simple process Demerits Rigid & Thick Demerits Short lifetime in humid Low efficiency
Fabrication of Flexible GaN LED Blue White 39 Nano Energy 1, 145, 2012
Flexible Vetical micro LED Nano Energy 447, 44, 2018
Flexible VLED on Motor Cortex Behavior Control Nano Energy 447, 44, 2018
Flexible Monolithic GaN LED Fabrication Process Optical output measurements & Device image Adv. Mater. In press