l Logic-Level Gate Drive l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description Fifth Generation HEXFET power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G PD - 95403 IRL04PbF HEXFET Power MOSFET D S V DSS = 40V R DS(on) = 0.0065Ω I D = 30A The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and TO-220AB low package cost of the TO-220 contribute to its wide acceptance throughout the industry. Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 30 I D @ T C = 0 C Continuous Drain Current, V GS @ V 92 A I DM Pulsed Drain Current 520 P D @T C = 25 C Power Dissipation 200 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 6 V E AS Single Pulse Avalanche Energy 700 mj I AR Avalanche Current 78 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case) Mounting torque, 6-32 or M3 srew lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R qja Junction-to-Ambient 62 www.irf.com 6/7/04
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 40 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.04 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.0065 V GS = V, I D = 78A Ω 0.009 V GS = 4.5V, I D = 65A V GS(th) Gate Threshold Voltage.0 V V DS = V GS, I D = 250µA g fs Forward Transconductance 63 S V DS = 25V, I D = 78A I DSS Drain-to-Source Leakage Current 25 V DS = 40V, V GS = 0V µa 250 V DS = 32V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 6V na Gate-to-Source Reverse Leakage -0 V GS = -6V Q g Total Gate Charge 0 I D = 78A Q gs Gate-to-Source Charge 32 nc V DS = 32V Q gd Gate-to-Drain ("Miller") Charge 43 V GS = 4.5V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 6 V DD = 20V t r Rise Time 2 I D = 78A ns t d(off) Turn-Off Delay Time 25 R G = 2.5Ω, V GS = 4.5V t f Fall Time 4 R D = 0.8Ω, See Fig. Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 5330 V GS = 0V C oss Output Capacitance 480 pf V DS = 25V C rss Reverse Transfer Capacitance 320 ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 30 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse (Body Diode) 520 p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 78A, V GS = 0V t rr Reverse Recovery Time 78 20 ns T J = 25 C, I F = 78A Q rr Reverse Recovery Charge 80 270 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ) Starting T J = 25 C, L =0.23mH R G = 25Ω, I AS = 78A. (See Figure 2) ƒ I SD 78A, di/dt 370A/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2% Calculated continuous current based on maximum allowable junction temperature; for recommended current-handling of the package refer to Design Tip #93-4 2 www.irf.com
000 I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 75 C V DS= 25 50V 20µs PULSE WIDTH 0. 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 30A 2.0.5.0 0.5 V GS= V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 000 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd 8000 Coss = Cds Cgd C iss 6000 C oss 4000 2000 C rss 0 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 2 8 6 4 2 I = D 78 A V DS = 32V V DS = 20V FOR TEST CIRCUIT SEE FIGURE 3 0 0 30 60 90 20 50 80 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 75 C T J = 25 C V GS = 0 V 0. 0.0 0.5.0.5 2.0 2.5 3.0 V SD,Source-to-Drain Voltage (V) 000 I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms ms TC = 25 C TJ = 75 C Single Pulse 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) 40 20 0 80 60 40 LIMITED BY PACKAGE R G V GS 4.5V V DS Pulse Width µs Duty Factor 0. % R D D.U.T. Fig a. Switching Time Test Circuit - V DD 20 V DS 90% 0 25 50 75 0 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
L V DS D.U.T. R G V - DD 4.5 V I AS t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E AS, Single Pulse Avalanche Energy (mj) 800 500 200 900 600 300 TOP BOTTOM I D 32A 55A 78A 0 25 50 75 0 25 50 75 Starting T, Junction Temperature ( J C) V DS Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 4.5 V Q GS Q G Q GD 2V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) - A - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.0) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF LOT CODE 789 AS S EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RE CT IFIER LOGO AS S E MB L Y LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.06/04 8 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/