EE241 - Spring 2006 dvanced Digital Integrated Circuits Lecture 7: Logic Families for Performance Notes Hw 1 due tomorrow Feedback on projects will be sent out by the end of the weekend Some thoughts on ISSCC? 2 1
Logical Effort Delay = k R = τ ( p + g f ) unit C unit C 1 + γc L in p intrinsic delay - gate parameter f(w) g logical effort gate parameter f(w) f electrical effort (fanout) Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by τ inv (everything is measured in unit delays τ inv ) ssume γ = 1. 3 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size 4 2
dd ranching Effort ranching effort: C b = on path + C C on path off path 5 Multistage Networks Delay = N ( pi + gi fi ) i = 1 Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 g N ranching effort: = b 1 b 2 b N Path effort: H = GF Path delay D = Σd i = Σp i + Σh i 6 3
Optimum Effort per Stage When each stage bears the same effort: h N = H h = N H Stage efforts: g 1 f 1 = g 2 f 2 = = g N f N Effective fanout of each stage: f = h i g i Minimum path delay Dˆ = i 1/ N ( g f + p ) = NH P i i + 7 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing D N H = N 1/ N D = NH 1/ N + ln( H ) + H P 1/ N P + ( ) = 0 N Substitute best stage effort h = H 1/ Nˆ 8 4
Logical Effort Optimization Methodology For smaller problems, easy to translate into set of analytical expressions Feed them into Matlab optimizer With some careful manipulations, can be turned into a convex optimization problem (Stojanovic) Easily extended to add power/energy 9 Sizing/Supply Voltage Joint optimization of parameters essential Trading off performance for energy 10 5
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Logical Effort: Summary Logical Effort Electrical Effort (Fanout) ranching Effort Effort Effort Delay Number of Stages Intrinsic Delay Delay Stage g f = C out /C in n/a h = fg h 1 p d = h + p Path G = gi F = C out / C in = bi H = FG D H = hi N P = pi D = D H + P 15 Increasing Performance Scaling technology Circuit/logic level: 1. Transistor sizing, buffering 2. Wire optimization, repeaters 3. Supply voltage 4. Threshold voltage 5. Logic styles 6. Logic optimizations 7. Timing, latches Microarchitecture level 16 8
Design Techniques Performance does not come for free Design Effort Dynamic custom Custom design Structured SIC Enhanced SIC SIC/RTL Performance 17 RTL Design Flow HDL RTL Synthesis Manual Design Module Generators Library netlist logic optimization a b 0 1 s d clk q netlist a b 0 1 d q physical design s clk layout [from K. Keutzer] 18 9
RTL/SIC Design Design description in Verilog/VHDL RTL Synthesized logic Standard cells Pre-defined macros Static timing verification, pre- and post-layout Statistical vs. extracted wire loads Physical design Top-level floorplan utomatic place and route Clock tree synthesized Post layout optimization, verification 19 Logic Optimization Library netlist logic optimization a b 0 1 s d clk q Perform a variety of transformations and optimizations Structural graph transformations oolean transformations Mapping into a physical library netlist a b 0 1 s d clk q smaller, faster less power [from K. Keutzer] 20 10
Combinational Logic Optimization Input: Initial oolean network Timing characterization for the module - input arrival times and drive factors - output loading factors Optimization goals - output required times Target library description Output: Minimum-area netlist of library gates which meets timing constraints very difficult optimization problem! [from K. Keutzer] 21 Logic Optimization netlist 2-level Logic opt Library logic optimization netlist tech independent tech dependent multilevel Logic opt Generic Library Real Library [from K. Keutzer] 22 11
Modern pproach to Logic Optimization Divide logic optimization into two subproblems: Technology-independent optimization - determine overall logic structure - estimate costs (mostly) independent of technology - simplified cost modeling Technology-dependent optimization (technology mapping) - binding onto the gates in the library - detailed technology-specific cost model Orchestration of various optimization/transformation techniques for each subproblem 23 Logic Level Optimizations Logic Depth or Techniques: Restructuring, pipelining, retiming, technology mapping R R Well covered by today s logic and sequential synthesis 24 12
Logic Optimizations (2) Fanout Late arriving Tp = O(FO) also effects wiring capacitance Technique: Removal of common sub-expression Start from tree structure/output 25 Technology mapping t p (nsec) 4.0 3.0 2.0 1.0 quadratic linear t phl 0.0 1 3 5 7 9 fan-in t p t plh Fanin T p = O(FI 2 )! Observation: only true if FI translates in series devices - otherwise linear e.g. NND pull-down NOR pull-up VOID LRGE FN-IN GTES! (Typically not more than FI < 4) 26 13
Technology Mapping for Performance lternative coverings Use low FI modules on critical path(s) Library composition? 27 CMOS Logic Styles CMOS tradeoffs: Speed Power (energy) rea Design tradeoffs Robustness, scalability Design time Many styles: don t try to remember the names remember the principles Changing the logic style can it be done without breaking the synthesis flow? 28 14
CMOS Logic Styles Complementary VDD Pass Transistor Logic C PUN OUT C LOGIC NETWORK OUT C PDN GND robust scales large and slow simple and fast not always very efficient versatile 29 CMOS Logic Styles Ratioed Logic VDD Dynamic Logic V DD LOD φ Out GND C PDN OUT R PDN << R LOD In 1 In 2 In 3 PDN C L φ GND small & fast static power Small & fastest! Noise issues Scales? 30 15
Others Current-mode logic diabatic logic 31 Pulsed Static CMOS RH Reset high RL Reset low Fast pull-up Fast pull-down Chen, Ditlow, US Pat. 5,495,188 Feb. 1996. 32 16
PS-CMOS Evaluation and reset waves: reset is 1.5x slower 33 PS-CMOS dvantages: No dynamic nodes good noise immunity Reset delay slower than evaluation No data dependent delay (worst case gets better) No false transitions Disadvantages Width of reset wave limits logic depth Margin in design 34 17
Skewing Gates Different rising and falling delays W W LE = 35 Skewing Gates 4W W LE = 36 18
Ratioed Logic V DD V DD V DD Resistive Load R L F Depletion Load V T < 0 F PMOS Load V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS 37 Pseudo-NMOS V DD 3.0 2.5 PMOS load 2.0 W/L p = 4 F 1.5 In 1 In 2 In 3 PDN V out, V 1.0 0.5 W/L p = 0.5 W/L p =.25 W/L p = 1 W/L p = 2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V in, V Trade-off between performance and power + noise margins 38 19
Differential Logic 39 Differential Logic Differential Cascode Voltage Switch (DCVS) Differential Split-Level Logic (DSL) Regenerative Push-Pull Cascode Logic (PPCL) Pass transistor logic families Dynamic logic families 40 20
Differential Logic + implicit invert, higher logic density 41 Cascode Voltage Switch Logic V DD V DD M1 M2 Out Out PDN1 PDN2 V SS V SS Cascode Voltage Switch Logic (CVSL) Sometimes called Differential Cascode Voltage Switch Logic (DCVSL) 42 21
CVSL V DD -V th Out M 1 Out M 3 M 4 Voltage,V 2.5 1.5 0.5,, Out Out M 2-0.5 0 0.2 0.4 0.6 0.8 1.0 Time, ns Fast (but hysteresis due to latch function) No static power dissipation UT: large cross-over current! 43 CVSL Full adder design How to design for reduced transistor count? 44 22
Karnaugh Map Technique 45 Karnaugh Map Technique x 2 x 3 00 01 11 10 x 1 0 0 0 1 0 1 0 1 1 1 LOD LOD uild shared cubes first! x 1 Q Q x 1 Q Q x 1 x 1 x 2 x 2 x 2 x 2 x 2 x 2 dd other cubes next x 3 x 3 x 3 x 3 46 23
Example Q = x 1 x 2 x 3 x 4 + x 1 (x 2 +x 3 +x 4 ) 47 Push-Pull Cascode Logic Gieseke et al, U.S. Patent 5,023,480 June 1991. 48 24
DSL Differential Split-Level Logic 49 Simulation Results for Different dders 50 25
Pass-Transistor Logic Inputs Switch Network Out Out N transistors No static consumption Transistor implementation using NMOS 0 F = 51 Pass-Transistor Logic Performance of PTL: dvantage over CMOS in implementing XOR, MUX Disadvantage in implementing ND, OR. Datapaths, arithmetic circuits are examples of use: dders and multipliers use XOR, MUX dvantage of complementary implementation Comparisons: When a new logic family is introduced, the examples are chosen to show its advantages; (not disadvantages). Comparison papers sometimes point to the disadvantages Full-custom design 52 26
Examples of PTL Styles Complementary Pass-Transistor Logic NMOS-only pass-transistor network Transmission-gate logic NMOS+PMOS pass gates Double Pass-Transistor Logic NMOS+PMOS network Numerous other logic families 53 NMOS-only switch 3.0 In =2.5V C = 2.5V CL = 2.5 V C = 2.5 V M n M 2 M 1 Voltage, V 2.0 1.0 Out x 0.0 0 0.5 1 1.5 2 Time, ns Threshold voltage loss causes static power consumption 54 27
Solutions Transmission gates adding complexity Low-threshold switches leakage! Level-restoration Level Restorer V DD V DD M r M 2 M n X Out M 1 55 Single-Ended Level Restoring Level Restoration Transistor Output Inverter Input Output Feedback Inverter 56 28
Differential Level Restoring f f Inputs Differential NMOS Logic Tree Inputs Different level restoration leads to different logic families 57 Different Restoration Schemes Swing-Restored Pass-Transistor Logic f f Inputs Differential NMOS Logic Tree Inputs Parameswar, et al CICC 94, JSSC 6/96 58 29
Other Level-Restoring Schemes f f f f Inputs Differential NMOS Logic Tree Inputs Differential NMOS Logic Tree Inputs Energy Economized Pass-Transistor Logic Inputs DCVS with Pass Gates (DCVS-PG) 59 Pass-Transistor Logic Families 60 30
Complementary Pass-Transistor Logic (CPL) Pass-Transistor Network F Complementary Pass-Transistor Network F Complementary functions Reduced number of logic levels Less transistors than CMOS Fast reduced load Complementary inputs complementary outputs V T drop several solutions 61 CPL Level restoration Yano et al, CICC 89, JSSC 4/90 62 31
CPL Same topology of networks Just different signal arrangements 63 Complementary Pass-Transistor Logic (CPL) nfet logic network -Fast - V T drop - Efficient implementation of arithmetic n1 S n2 n3 Q Qb XOR n4 S (a) C C (b) S Sum S 64 32
CPL Karnaugh Maps C 2 C 1 0 0 C 2 C 1 0 1 C 1 C 2 65 CPL vs. CMOS 66 33
Skewing Output Inverter 67 Differential vs. Single-Ended 68 34
Leap Cell Library Yano et al, CICC 94, JSSC 6/96 Goal: Implement full logic functionality with small library Rely on automated design methodology 69 Various Logic Functions of the Leap Library 70 35
LEP Comparison 71 Double Pass-Transistor Logic (DPL) V DD ND/NND O O XOR/XNOR O O 72 36
Designing DPL Gates C 4 C 2 0 0 C 1 0 1 C 3 C 4 C 2 C 3 C 1 73 Designing DPL Gates (2) C 1 C 2 0 1 C 2 Å 1 0 C 1 C 4 C 3 C 3 C 4 0 1 C 3 C 2 C 4 1 0 C 1 C 2 C 4 Å C 1 C 3 74 37
pplications of DPL Full adder: 1.5ns 32-bit LU in 0.25μm CMOS Suzuki, ISSCC 93 JSSC 11/93 75 Comparison of Logic Styles Zimmermann, Fichtner, JSSC 7/97 76 38
Comparison of Logic Styles 77 Comparison of Logic Styles 78 39
Results 79 Results 80 40
Results 81 41