EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture #7 Components Termination, Transmitters & Receivers Jared Zerbe 2/10/04 Outline General issues Termination Transmitters Receivers 2 1
General Issues Single-ended vs. Differential Voltage mode vs. current mode I/O clocking & use of phasors RiCi 3 Single-ended vs. Differential C d d in ref C r rcvr xmtr d out Single-ended signaling compare to shared reference Often used with a bus Issues Generates SSO noise How to make reference How to quiet reference : difference in bypass network if shared Crosstalk cannot be made common-mode Differential must run > 2x as fast as single-ended to make sense Often debated if this always can be done 4 2
Voltage mode vs. current mode Voltage Mode Push/Pull Current Mode Push/Pull In a transmission-line environment does this terminology make sense? A wave has voltage and current, right? Answer is in the driver Z Low Z driver = voltage mode High Z driver = current mode 5 Clock Frequency Limits Pulse amplitude reduction % 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.5 3.5 4.5 5.5 Clock pulse width (FO-4) Min clock period > 8-FO4 (I.e. 1-GHz @ 0.25u) Faster links should use multiple clocks: Critical on mux/demux 6 3
I/O clocking & use of phasors Tx Rx Heavy multiplexing of input & output data streams allows for performance higher than process technology would seem to allow Can get out of hand 7 RiCi & Pad Complexity R s L 1.00 G d C L I C I R I Normalized amplitude 0.80 0.60 0.40 Ci, Ri typically dominate 0.20 0.00 "low_cl" "1_drop" "2_drop" "4_drop" "8_drop" 1e+008 1e+009 Freq (Hz) You can t just add arbitrary complexity at the pad Tx, Rx, ESD & Pad itself have RiCi which makes pole In multi-drop busses, multiple poles at same frequency can stack up! 8 4
Termination Why terminate? External vs. internal Series vs. Parallel AC vs. DC termination Untrimmed poly Active termination 9 Why terminate? Termination keeps energy from bouncing around In current-mode signaling voltage is developed across the terminator Quality of termination can limit system performance 10 5
External vs. Internal Output Voltage (%Vdd) 1.00 0.95 on-chip termination off-chip termination package C pad L bond (a) R term 50Ω Transmission Line 0.90 (a) package R term (b) C pad L bond 50Ω Transmission Line 0.85 2.0 2.1 2.2 2.3 time (ns) (b) + Internal termination makes package L part of T-line + Eliminates package as stub - Increases complexity, poor tolerances for on-die R s 11 Series vs. Parallel Termination V tt Source data pd R T Z o data pd R T Z o End data pd Z o R T V tt - Z o + R T V tt Parallel Series Series often used with voltage mode Driver lower Z than Rt Parallel with current-mode Driver higher Z than Rt Driver Z hard to control across PVT Highest performance is usually through parallel termination 12 6
AC vs. DC Termination With differential signals can terminate to the compliment Potential power savings Can build a higher-z system What sets common-mode? Usually TX Demands large RX common-mode range R AC V TT Rx R CM AC-coupled & AC-term Now can set common mode with parallel large R s R AC Rx R CM V TT 13 Termination With Untrimmed Poly Issue is variation in sheet resistance & C D Typically +/- 15% in sheet-rho at one temperature Also typically varies with temperature BUT At least it s always a resistor (no non-linearities) It s simple It s ESD robust 14 7
Active Termination IV-characteristic of two-element resistor [Dally] 15 Termination Example : SSTL Source 16 8
SSTL Conventional w/o source 1 stubs w/ 1 spacing 1 receivers 0 17 SSTL - with source damping resistors Resistors act like rubber bands Rs=Zo/2 1 receivers 0 18 9
RSL: Compensated short stubs 1 0 19 RSL: Current Mode Terminated @ End Memory reads split 50/50 and go in each direction Then double at the master end to restore full-swing Writes go straight through to terminator Allows for multi-drop memory bus with high-z drivers 20 10
Transmitters Single-ended SSTL RSL GTL Differential LVDS CML Transmitter timing Other TX Design Issues 21 Tx Single-ended Classic inverter why not? Poor Z matching at Tx; very prone to reflections Generates extreme amounts of SSO noise Easily order(vdd) if there is any L and large # of drivers Have to generate term voltage at Rx; burns power 22 11
Single-Ended : SSTL Class-I V TT V TT I o = +/ - 8mA 50Ω 25Ω Zo = 50Ω V TT Class-II V TT V TT 50Ω 50Ω 25Ω Zo = 50Ω I o = +/ - 16mA VTT=0.45*VDDQ (center term) 23 Single-Ended : SSTL characteristics Center-terminated, push-pull Very flexible termination Allows double, single, or no termination But source term slows edgerates & limits speed Very simple Driver can be simple inverter Receiver can be simple inverter but PVT varying output driver means reflections 24 12
Single-Ended : RSL V REF V TERM 28Ω Zo = 28Ω I o = - 30mA V TERM =1.8V V REF =1.4V 25 Single-Ended : RSL characteristics Open drain current-source driver Current-control to keep constant i over PVT Slew-rate control to keep rate low enough to avoid overshoot & ringing Low-swing with reference Relatively expensive and complicated Very short stubs Aggressive Ci, Li Tuned out with loaded/unload sections 26 13
Single-Ended : GTL/GTL+ V TT V REF 25Ω Zo = 50Ω I o = - 40mA V TT =1.2V V REF =0.8V 27 Single-Ended : GTL/GTL+ characteristics Just like Rambus But output driver goes linear No current-control Resistance presents Z-discontinuity to line Lower Vterm doesn t help transmitter Ron Addressed somewhat in GTL+ which shifted term 28 14
Differential : LVDS I o = +/ - 3.5mA Tx Zo = 100Ω Zo = 100Ω 100Ω Rx V CM =1.25V (set by driver) AC terminated @ receiver 29 Differential : LVDS characteristics Differential Eliminates non-common mode reference noise Also (ideally) keeps current at driver constant Low power - only +/- 3.5mA Termination at the RX on-chip or off No references, can ship across cable Requires very wide CM range from RX Unterminated at driver; reflections occur from discontinuities Timing of driver push-pull ckt can be a challenge 30 15
Differential : CML - direct coupled V DD V DD 50Ω 50Ω Tx Zo = 50Ω Zo = 50Ω Rx I o = - 21mA Double-terminated on-chip 31 Differential : CML - AC coupled V DD V TERM 50Ω 50Ω Tx Zo = 50Ω Zo = 50Ω Rx I o = - 21mA Supports different on-chipvterms 32 16
Differential : CML Characteristics Open-drain High common-mode keeps saturation DC or AC coupled AC-coupling requires 8b10b coding Termination DC-term: Better control of CM than LVDS Requires on-chip term network Double-terminated Minimize reflections off driver Driver and receiver both see 25Ω More power 4x LVDS just from 100Ω -> 25Ω term 33 Physical signal swings 2.0V 1.5V CML 2 dc-coupled 1.0V CTT SSTL_3 1 BTL RSL LVDS 2 0.5V HSTL GTL GTL+ 0V 1 swing @ receiver input, driver swing will be higher. 2 differential signalling 34 17
Simple Transmitter Timing DDR: send a bit per clock edge Critical issues: Data_O Data_E 50% duty cycle Tbit > 4-FO4 output pulse width closure (%) 30 20 10 0 1 2 3 4 5 bit time (normalized to FO4) 35 Very Fast Transmitter Timing clock(ck3) ck3 R TERM d0 Limiting time constant 25-Ω*Cpad Cpad = 8*Cdriver + Cesd D0 D1 D2 data(ck0) R TERM d0 out_b out x 8 Off chip time constant smaller than on chip: Generate current pulse at the output Limited only by the output capacitance 0.0 0.50 0.60 0.70 0.80 0.90 1.00 Bit-width (#FO-4) Need to be very careful to match & tune; otherwise can make things worse % eye closure 30.0 20.0 10.0 36 18
More TX Design Issues Saturation Margin Drivers with current sources are limited in common-mode range Must keep tail saturated; otherwise Z is thrown off DC Distortion, ISI generation What drives the driver? How far back to get to CMOS levels? It is easy to amplify errors by unknowingly biasing your circuit to a level or to an edge Edge-rate Control At FF corner your TX can generate edge-rates too fast Higher xtalk (especially NEXT) More reflections (smaller Z discontinuities) 37 Receivers Basic receive architectures StrongARM latch & improved latch Single-ended : reference noise Integrating receivers RX Design Issues 38 19
Two Basic Receive Architectures V i ref + - A D Q D Q f data /2 d in0 d in1 V i ref d in0 Rcv0 d in1 Rcv1 f data /2 d in0 d in0 precharge sample/ regen d in1 d in1 Amplify then sample or Sample, then amplify 39 Rx Example : StrongARM Latch Vo- V o+ V i+ V i- Simple single clock design Grey device show cross-coupled inverters that regenerate. Need a follow-on latch at the output to hold the data for the full clock cycle. 40 20
Rx Example : StrongARM Latch Vo- V o+ V i+ V i- Has sampling noise and charge kickback from switching. Input offset not great : 50-100mV Bit-time is limited by the cycle-time (to have enough gain) Common-mode gain effects through the tail device in linear region 41 Improved Sampling Receiver som sop M2 outp inp bias M1 tail sop/m inp/ref V ref I offp hold sop D t To SR-Latch outm som I offm T cycle outp/m t Improvements in common-mode sensitivity, kickback, offsets through correction port (IoffP, IoffM) 42 21
Receiver Evaluation : Step Response impulse response (V) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 aper =1/4 FO-4 t aper =1/6 FO-4 t aper =1/5 FO-4 t aper =1/3 FO-4 0.00-100 -50 0 50 100 150 t (ps) Can calculate pulse response of Rx front-end Indicates aperture & gain-bandwidth characteristics of the receiver Can be convolved with the channel response 43 Integrating Rx & Reference Noise Sampler Integrator Sampler Integrator used to mute the effect of high-frequency noise Most interesting in single-ended systems High frequency noise is often L*dI/dt switching noise on reference Due to differences in loading between reference & signal 44 22
Integrating Receiver Design Sense Out Outb Pchgb V N V NB i Sense System clock Pchg Sense Integration window 45 Integrating Receiver Windowing Receive clock No windowing With windowing DLL adjusts RClk timing Pchg Pchg Sense Sense Integration window Integration window Input Data V out Input Data V out Anti-data Integration time is windowed to match valid data & minimize anti-data 46 23
RX Design Issues Offset Typically front-ends have 10-30mV of uncorrected offset Heavy MonteCarlo sims and active methods must be used to reduce offsets to ~5mV in multi-receiver designs Aperture ISI Need Gain*BW BW in slicer domain translates to pulse response width or aperture Must properly reset the receiver before the next evaluate phase Often there is some residual ISI or negative ISI you must eat Common-mode gain Most structures have different gain characteristics (and thus sensitivity) across the range of common-modes. Often end up restricting range or adding preamp 47 ISSCC 2004 Next Week Interesting sessions in high-speed I/O highlighted Be prepared to talk on at least 2 papers from these sessions 48 24