Robust I/O circuit scheme for world s first over 1.6Gbps LPDDR3

DesignCon 2013 Robust I/O circuit scheme for world s first over 1.6Gbps LPDDR3 Kyoung Hoi Koo, SAMSUNG Electronics. [kiminkoo@samsung.com] Woong Hwan Ryu, SAMSUNG Electronics. Sang Min Lee, SAMSUNG Electronics. Baek Kyu Choi, SAMSUNG Electronics.

Abstract Since today s mobile multimedia Application Processor (AP) requires high-performance low-power signal processing, there is demand for extremely high-bandwidth memory interface for 3D game and high-quality video in large size smart phone and tablet PC. These trends lead to consideration of higher-performance DRAMs than 1066Mbps LPDDR2. Wide IO mobile DRAM [1] has been considered as candidates for over 6.4GB/s channel bandwidth. However, Wide I/O must solve issues such as low stacking yield for higher density and failure analysis modeling of system-in-package (SiP). To achieve world s first 1.6Gbps LPDDR3 interface without pseudo open drain (POD) termination for mobile AP device, following new I/O circuit schemes are required. In this paper, we investigate the speed limiters from conventional DRAM interface system and identify the speed enablers in the area of chip I/O, package, board, and LPDDR3 memory device [2] respectively through chip-to-chip SI/PI analysis to enable robust I/O signaling solutions for world s first 1.6Gbps LPDDR3 interface without POD termination. This results in world s first WQXGA display mobile AP chip using 28nm low power CMOS process and an amazing 30% reduction in power consumption versus our previous 45nm AP chip. Author s Biographies Kyoung-Hoi(Billy) Koo received B.S. and M.S. degrees in electrical engineering from Chungbuk National University, Korea in 1996 and 1998, respectively with focus on high speed I/O transceiver. In 1998, he joined SAMSUNG Electronics where he was designed and developed high-speed peripheral interfaces such as PCI-X, AGP, HSTL, SSTL, LVDS and USB2.0. From 2004 to current, he was responsible for the developing highspeed memory interface circuits for DDR2/DDR3/DDR4 and LPDDR2/LPDDR3. He holds over 10 U.S. and foreign patents, and published 6 papers and conference contributions in analog/digital mixed signal design and high-speed interface area. Dr. Woong Hwan Ryu is an Engineering Department manager at Samsung Electronics Co., Ltd. with responsibility for power/signal integrity and electrical validation enabling for AP/SOC and LSI silicon/platforms. From 2001 to 2011 Dr. Ryu was a senior Engineering Department manager at Intel Corporation where he managed the Signal/Power Integrity Engineering (SPIE) team, which is responsible for pre- and postsilicon signal/power integrity analysis for future memory technology development (MCOE) and SOC Hard IP customers/platforms. Since 2008 Dr. Ryu holds an IEEE Senior Member status. He is the co-author of a book titled "Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design (Prentice Hall Modern Semiconductor Design Series' Sub Series: PH Signal Integrity Library, April 2010)". Dr. Ryu has authored and co-authored more than 90 technical publications in premier journals, international conferences, and Intel internal journals and conferences. Dr. Ryu serves as a reviewer for several IEEE journals and as a technical program committee

member for DesignCon. Dr. Ryu was a best paper award recipient in recognition of my technical contributions to DesignCon2006 and DesignCon2008. He holds a Ph.D. in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST). Sangmin Lee leads a SoC/AP platform integrity & electrical validation at Samsung. He has been responsible for I/O platform enabling activities and design methodology development for high speed memory and serial interfaces. Before joined Samsung, He worked as a senior component design engineer at Intel Corp, where he developed tests and tools for System Validation (SV) of chipsets and processors. Baekkyu Choi received the M.S. in electrical engineering from KAIST (Korea Advanced Institute of Science and Technology) in 2001. He is working for Samsung in the design of various memory interfaces in the specialization of signal power integrity. His professional interests include full channel signal and power integrity modeling and optimum simulation techniques with various interface standards. Acknowledgements The author would like to acknowledge and give special thanks to Baek-Kyu Choi for his support in LPDDR3 memory channel modeling and simulation and also writing contained here. Also following individuals whose dedication was invaluable in enabling works: Seong-Jae Moon for carrying system test and debug with measurement, Seung- Bae Lee for FD characterization with VNA measurement, Chan-Min Jo for performing memory off-chip simulation for PI/SI analysis, Young-Hoon Kim for leading improvement of electrical performance in package, Min-Ho Seo for executing board PI/SI analysis with measurement and simulation, On-Pil Shin for leading SMDK board design and revision. Lastly, I d like to give special appreciation to Dr. Woong-Hwan Ryu who is the technical leader and advisor of electrical council task force for directing the enabling activities.

LPDDR3 Channel Characteristics Typical mobile channel length from AP die to DRAM die is about 10~50mm and opened to terminate for lower power consumption. Channel acts like ~ /4 resonator over 800MHz and 3D effects becomes more crucial as the data rate goes higher. /4 resonator can cause large voltage fluctuation because /4 resonator has a large Quality (Q) factor. When frequency components, which are fitted to resonance frequency, are excited in the channel, the frequency has large gains from resonator, but the other frequencies which are not fitted to resonance have smaller gains. This causes Inter-Symbol-Interference (ISI) effects for the signals [3]. Signal interference between signals like crosstalk can be amplified by channel resonance. Thus, first step of designing mobile channel without termination is checking out the channel condition to avoid channel resonance which comes from channel length and minimizing the second order effects from signal crosstalk LPDDR3 1.6Gbps Signaling Problems in first Sample High frequency RF effects including signal ringing, ISI and crosstalk are observed at first platform sample. Timing and voltage margin is too small to operate 800MHz operations. In POP case, LPDDR3 operation was limited to only 677MHz from system level LPDDR3 functional test. In SCP case, the operation was also limited to only 533MHz from the same system level LPDDR3 functional test due to various signaling problems in the channel. The LPDDR3 memory tests were executed with pattern and random data during READ/WRITE per channel and interleaving between 2 channels. One of signaling phenomenon from data (DQ) and data strobe (DQS) waveforms are higher post-amble ringing level than voltage reference (VREF) during 800MHz read/write memory transactions. After the DQ strobes send the bits, the ringing is occurred and get worse at memory read operation than write operation since weak pulldown scheme helps to suppress DQS signal ringing during write operation. The amplitude of the post-amble ringing increases in proportion to the memory operating frequency. Higher DQS ringing than VREF level can cause the malfunction of logic in the system, so the ringing level must be suppressed to less than VREF. Figure 1 is the oscilloscope capture and shows Post-amble ringing level during memory READ and it had 1.83 volt (V) peak-to-peak and that was over limit VREF to cause a logical failure at next data transfer. Figure 1: TD measurement on DQS/DQ post-amble ringing during READ operation.

Optimization of AP Driver s IO Capacitance (Cio) At the channel end of mobile system, only receiver is placed without any termination to reduce power consumption. Due to a receiver input capacitance at pad, actual channel is terminated by the capacitance. Capacitive termination affects two points of view with time constant and signal attenuation. As signal data rates increase, designers must take into account signal reflection while signal matching becomes more difficult at higher frequencies, due to parasitic component at the receiver end. The receiver end parasitic capacitance (Cio), including silicon devices and interconnects, introduces 1-1.5 pf variation in the recent interfaces. The impact of the receiver end capacitance is frequency dependent signal reflection, which makes wide bandwidth signal distortion inevitable and may cause channel resonance due to impedance discontinuities at receiver and driver. In general, the I/O receiver capacitance should be minimized and silicon resistance should be increased to improve signal integrity at the receiver, as shown in Figure 2 In regard to the effective impedance at extremely high frequencies, the device impedance approximates closely to the receiver end parasitic resistance (Rio) that comes from conductive silicon substrate of IO circuitry. The reflection from the device is dependent on the difference between the transmission line characteristic impedance and the input impedance of the driver. As frequency increases, the sensitivity of the receiver's capacitance on signal integrity becomes dominant. Consequently, special attention should be invested to receiver input capacitance. A Pareto plots for timing margins of LP DDR3 data bus as a function of HVM variables, as shown in Figure 3 the charts indicate that Cio at receiver is one of most sensitive parameters for both data and address signals. Figure 2: An input impedance frequency response of a given device. Cio impact increases as frequency goes up

Figure 3: Pareto plots Indicate Cio is one of most sensitive SI variables for both (a) DATA signal and (B) Address signal At high speed operation, time constant causes reducing timing margin and the signal attenuation is increased due to lowered impedance. In first sample, drivers had 1.96pF input capacitance. With 50Ω channel, time constant was 96ps and that is 15.4% of Unit Interval (UI) at 800MHz operation. Impedances at 800MHz and 2.4GHz are 100Ω and 33.8Ω respectively. Especially 33.8Ω at 2.4GHz is lower than 50Ω. This causes negative reflection which degrades the signal quality. To reduce Cio, we have to know bi-directional IO (DQ, DQS) configuration and its Cio portion. As you can see from the Figure 4, bi-direction IO consists of driver, receiver and ESD protection circuitry. First we analysis the Cio portion for each component. A driver comprises of active device and passive device, and JEDEC recommends using 240Ω based driver impedance such as 30/34/40/48/60/80/120/240Ω. To make 30Ω driver impedance large active device area is needed; this leads to Cio increase. To reduce Cio and achieve 1.6Gbps interface speed, finding an optimal ratio for active device and passive device is required. PAD Driver PAD ESD Cio Receiver PAD Figure 4: Simplified bi-directional buffer schemes

Low Cio in high-speed memory interfaces, especially in the un-terminated channel environment is the main factor to improve signal integrity (SI), but it s not easy to reduce Cio because low driver impedance (large driver size) and high ESD level is required for mobile devices. To reduce Cio, ESD protection size and its layout pattern need to be optimized. Figure 5 (a) shows active (RX), Poly (PC) and M1~M6 layout patterns, to minimize Cio, we reduced ESD protection diode size cathode line metal (M2~M6) length; this help add extra de-caps in order to improve power integrity. Figure 5 (b) depicts M7 metal strips. We cut the M7 patterns to reduce overlay capacitance. With this approach, additional ~0.3pF Cio reduction is achieved only by optimizing the ESD protection circuitry. As a result, total AP Cio was reduced to 1.565pF from 1.96pF. Figure 5: Low Cio ESD protection layout patterns Adoption of Versatile IO Driver/POD Impedance An IO with more linear V-I characteristics improves signal quality by absorbing reflected signal waves and reducing ring-back. A linear buffer allows all reflection to see the same reflection coefficient when the wave returns to the driver. High curvature (a saturated V-I characteristics) means that the reflection coefficient is dependent of voltage; therefore, waves at slightly different voltage will generate vastly different reflections, contributing to uncertainties in flight time and skew. This uncertainty is greatly reduced with more linear buffers. Adding resistors in the output path makes the buffer more linear. A series resistor creates a voltage drop that helps keep the transistor out of the saturation region at larger pad voltages. Series resistance, as shown Figure 6, largely determines the buffer impedance. There is a drawback to this implementation. The series resistance weakens the buffer and a larger buffer is needed to obtain a given driver strength and equivalent impedance. If the driver impedance is too low over-/under-shoot at the

receiver end is increasing; this results in ring-back and settling time problems. Too high driver impedance limits the voltage swing at the receiver; this results in large reduction in timing/voltage margin. Therefore, buffer characteristic parameters chosen for LPDDR3 are optimized considering a balance of improved signal quality and driver strength loss. Figure 6: Linear buffer curves As shown in Figure 7 to determine active device (transistor) and passive device (resistor) portion, we sweep the Rs value and the Tr. width. As Rs increases good linearity is acquired. Our recommendation for 240Ω driver unit impedance Rs value is around 120~140Ω. An optimal Tr. size can be determined after Rs portion is fixed. The driver itself needs to be carefully designed to balance between the rise-fall mismatch. Any delay mismatch reduces data setup and hold margin. One way to reduce rise and fall time variations is to use non-minimal channel length device. R pullup, R pulldown = V(VIH AC) V(VIL AC ) I VIH AC I VIL AC (1) R mismatc h = R pulldown R pullup 100 2 R pulldown + R pullup Once pull-up(pull-down) unit is fixed its counterpart pull-down(pull-up) unit size is fixed using equation (1) and (2). Figure 8 shows two types of driver unit which has a source

termination resistor. To minimize Rmismatch, separated Rs resistor for each pullup and pulldown unit is recommended. Otherwise merged Rs type is good for Cio minimization. In this paper we use separated Rs resistor type driver unit provided good linearity, and also it can reduce the Rmismatch less than 0.1%. Figure 7: Active device and passive device ratio and its Cio values Rs Rs1 Rs2 (a) Figure 8: Source termination configuration in driver unit (a) Merged type (b) Separated type (b)

After unit driver feature is fixed, the next step is to decide the driver impedance combinations. The conventional LPDDR2/LPDDR3 interfaces support 240Ω based driver impedance e.g. 240/120/80/60/48/40/34/30Ω and POD for 240Ω or 120Ω. To save power consumption and increase signal quality for mobile device, we adopt a versatile driver impedance control scheme which has backward compatibility to the conventional LPDDR2/LPDDR3 impedance such as 240/120/80/60/48/40/34/30Ω and also 160/96/69/53/42/37/32/28Ω impedance. To do this, 8ea 240Ω unit drivers and a 480Ω unit driver configuration are proposed in our research. The 480Ω unit driver can easily be implemented using 240Ω unit driver. This versatile driver impedance gives power saving and signal integrity improvement for various mobile devices which uses LPDDR2/LPDDR3 memory. We also provide a different driver impedance control scheme for each DQ/DQS/CA/CLK signals by using separated control block while conventional scheme is using a common control block. This feature also helps increase signal integrity under various package/board environments. Figure 9 shows the proposed unit driver impedance and driver impedance control scheme. Figure 9: Unit driver configurations DRAM Duty Cycle Optimization A specific bit at READ had narrower pulse width and DQS had a large ringing after normal data transfer was found during the first sample measurement. As LPDDR3 does not have DLL circuitry on DRAM side, timing was tuned by IO circuitry only. DRAM Automatic Test Equipment (ATE) test result of the first LPDDR3 sample showed 60-40 mismatch in duty cycle. This mismatched duty reduced the timing margin and caused a large post-amble ringing in DQS. Figure 10 shows the post-amble ringing amplitude with respect to the duty ratio. The ringing was amplified by channel length at 1.2GHz. A wider low duty leads to reduction in voltage ringing due to damping effect.

Figure 10: READ DQS post amble ringing simulation with respect to DQS pulse width Based on simulation results of DQS post-amble ringing vs. duty ratio, DQS s duty cycle was the important factor to determine the ringing level. In the case of correcting duty ratio from 6.5:3.5 in the H: L to 5.5:4.5, the DQS post-amble ringing was stabilized. Although 60-40 duty ratio was satisfied with LPDDR3 spec, DRAM duty was corrected to get more timing margin and reduced the ringing level. Figure 11 shows the DQS duty ration using ATE. After DQS duty ratio was corrected, DQS post amble ringing at READ was stabilized at the second sample platform. The ringing voltage was measured at 0.7Vpp from 2Vpp and it did not cross over the 0-level as shown in Figure 11. Figure 11: DQS and post-amble stabilization with corrected DRAM duty ratio

Fast Dynamic ZQ Calibration For 1.6 Gbps LPDDR3 interface, digitally compensated driver scheme is recommended [4]. Figure 12 shows an example of a digital compensation scheme. The reference generator uses a resistor bridge to select transistor leg sizes, by comparison, against a reference resistor value which is proportional to the target driver impedance. The reference resistor, Rext, can be an external or an internal resistor depending upon tolerance requirements. The legs are enabled until the voltage of the enabled legs equals to that of the reference resistor, Rext. Driver impedance variation can be compensated by using 3bit binary weighted digital compensation techniques. Each leg is binary weighted, allowing for a simpler design, uniform coverage with fewer steps and greater efficiency. One benefit from using digital compensation is that compensation information can be easily distributed across the pad rings as a DC signal. The digital compensation scheme should be carefully designed and evaluated for output impedance error due to quantization and drift of temperature and VDDQ voltage. In order to avoid to such drift, the compensation information to the output buffer requires periodic update to maintain required tracking of temperature and voltage drift. To reduce ZQ calibration time, fast ZQ calibration scheme is adopted in this paper. During the initial power-up period, accurate calibration procedure is going. After initial period is over and memory interfaces start to work, there will be a temperature/voltage discrepancy compared to the initial condition. At that time fast calibration process are working, tunes the driver/termination impedance with in 20 clock cycles using post processing circuit. The post processing circuitry compares the current code which results from the initial calibration and next code which comes from current code +1,+2,-2,-1 in advance, and makes a decision for final code update. Due to fast dynamic calibration, fly-by impedance correction is possible for improving SI. Impedence Tuning Circuit Post Processig Output Driver Pull-up Array PEND FSM Pull-up Array CLK/ START + - Decision Circuit Pull-up Codes Pull-up Array + - VREF START2 PAD + - Pull-down Array + - Decision Circuit Pull-down Codes Pull-down Array NEND FSM RESET REQ_LONG REQ_FORCE REQ_FAST Long Calibration Max. 125 cycle External mode Short Calibration Max. 20 cycle ACK ZQ Weak pull-up Hi-Z Weak pull-up Hi-Z Pull-up Codes Pull-down Codes Calibrated code Forced code Calibrated code Forced code Figure12: Fast ZQ calibration using post processing Calibrated code Calibrated code

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 On-die De-cap Optimization To reduce SSO noise in weak Power Delivery Network (PDN) condition, e.g. POP package environment, On-die de-cap insertion is considered, but adding on-die de-cap increases the chip size. An accurate and fast method for optimizing on-die de-cap is needed. To maintain lower PDN impedance, on-die de-cap optimization was studied by using worst patterns. To shorten the test time, effective test patterns, which boost signal degradations, are necessary for system test and SI simulation. Effective and short test patterns were implemented by using the Peak Distortion Analysis (PDA) method. Basic PDA method uses only single mode pulse response but in this work, pulse responses of even and odd modes were also used to include mode impedance and tpd (time Propagation Delay) variation. When it s on even mode, the channel impedance goes up and the tpd is increased by strong inductive coupling. But when it s at odd mode, channel impedance goes down and tpd is reduced. As channel impedance is changed by signal mode, accurate signal mode effect test patterns should be included. Worst patterns were determined by basic PDA equations in (3) for the each mode [5]. Figure 13 shows the simulated eye opening size under with on-die de-cap and without on-die de-cap. ISI +, V WC1 = ISI (3) 540 530 520 510 500 490 480 470 460 w de-cap w/o de-cap (a) 550 540 530 520 510 500 490 480 w de-cap w/o de-cap A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 (b) Figure13: Eye opening size [ps] (a) DQ signals (b) C/A signals

To increase effective capacitance and reduce shunt resistance [6], on-die de-cap should be placed closely at the output driver which has large power fluctuation and connect to power/ground rail using low resistance inter connect material. Figure 14 depicts proposed on-die de-cap insertion. Based on empirical data, to achieve 1.6Gbps LPDDR3, at least 1000pF on-die de-cap is required per one LPDDR3 channel. To ensure total 1000pF, 300pF additional on-die de-cap is inserted under LPDDR3 IOs. Signal PAD VDDQ supply VSSQ supply Signal PAD VDDQ supply VSSQ supply VDDQ output driver VSSQ VDDQ VSSQ VDDQ VSSQ stacking de-cap unit to increase capacitance Bump connection Place under signal PAD Place under signal VDDQ supply PAD Place under signal VSSQ supply PAD Figure14: Additional on-die de-cap insertion

LPDDR3 Fundamental and its 3 rd Harmonic Frequency noise affects various wireless communication standards such as GSM, GPS, WCDMA, Wi-Fi etc. Especially the 3 rd harmonic frequency of LPDDR3, 2.4GHz, is overlapped to Wi-Fi frequency range. Careful observation for EMI and solutions for reduce EMI level must be considered. EMI level test for various driver impedance and slew-rate options was done using the TEM cell board environment [7]. An optimal driving impedance and slew-rate selection is a key factor for reducing EMI level. In this paper 2.4~3.0V/ns slew-rate is selected considering timing margin and EMI level. Figure 15 shows the EMI level measurement data for various driver impedance and slew-rate option. Figure15: EMI level test results (a) 3 rd harmonic level (b) Time domain waveforms (c) EMI level difference according to driver impedance/slew-rate (d) Slew-rate values

Test Results The world s first LPDDR3 platform which was fabricated using 28nm High-K low power CMOS process achieves 1.6Gbps operation frequency bin. Measured Eye diagram and voltage margin under SMDK board are shown in Figure 16. Typical voltage for logic and LPDDR3 interface is 1.0V and 1.2V, respectably. An LVcc test result shows the successfully 1.6Gbps operation is possible even Vcore=887mV and VDDQ=1.05V. (a) Vcore VDDQ 1200 mv 1150 mv 1100 mv 1050 mv 1000 mv 1000 mv Pass Pass Pass Pass Fail 968 mv Pass Pass Pass Pass Fail 956 mv Pass Pass Pass Pass Fail 950 mv Pass Pass Pass Pass Fail 937 mv Pass Pass Pass Pass Fail 925 mv Pass Pass Pass Pass Fail 918 mv Pass Pass Pass Pass Fail 912 mv Pass Pass Pass Pass Fail 906 mv Pass Pass Pass Pass Fail 893 mv Pass Pass Pass Pass Fail 887 mv Fail Fail Fail Fail Fail (b) Figure16: LPDDR3 interface test results (a) Eye diagram (b) LVcc margin Conclusions In this paper, we presented how we enabled the world s first LPDDR3 1.6Gbps for mobile AP which support WQXGA display and achieved robust signaling solutions without POD termination using 28nm low power CMOS process technology. For enabling works for LPDDR3 1.6Gbps signaling without termination, we analyzed each

SI/PI phenomenon through time- to frequency-domain characterization in a system-level environment. Key solutions for stable 1.6Gbps signaling such as reduction of I/O driver Cio, versatile driver impedance and reinforcement of calibration method for on-time impedance tracking were discussed. Also PDN improvement by lowering impedance along with on-die decoupling capacitor optimization and correction of DRAM duty cycle in LPDDR3 memory device were reviewed. References [1] J. Kim, et al. A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4X128 I/Os using TSV based Stacking, ISSCC Dig. Tech. Papers. pp. 496-497, Feb. 2011. [2] Yong-Cheol Bae, et al. A 1.2V 30nm 1.6Gbp/s/pin 4Gb LPDDR3 SDRAM with Input Skew Calibration and Enhanced Control Scheme, ISSCC Dig. Tech. Papers, pp.44-46, Feb. 2012. [3] Pandit, S. V. & Ryu, W. H., Power Integrity for I/O Interfaces: With Signal integrity/power Integrity Co-design (Prentice Hall Modern Semiconductor Design Series, 2010) [4] AGP Design Guide Revision 2.0, Intel Corporation, 2002. [5] Hall, S. H. & Heck, H. L. Advanced Signal Integrity for High-Speed Digital Designs, IEEE: Wiley, 2008. [6] Swaminathan, M. & Eugin, A. E. Power Integrity Modeling and Design for Semiconductors and Systems: Prentice hall, 2007, pp.37. [7] Seung-Bae Lee, et al. Electromagnetic Interference (EMI) Behavior of System in Package(SIP), Electromagnetic Compatibility (EMC). pp.76-80, Aug. 2004.