ECE 595B Analog IC Design Design Project Fall 2009 Project Proposal Ultra Low Static Power OTA with Slew Rate Enhancement Patrick Wesskamp PUID: 00230-83995
1) Introduction In this design project I plan to create an ultra-low static power OTA for switched capacitor and sample-and-hold designs, which still will be able to deliver high currents into capacitive loads when necessary. Switched capacitor designs are a technique widely used in modern integrated circuits to create, for example, filters for analog signal processing. Basically, by periodically activating switches connected to capacitances equivalent resistors can be formed. Their value is only dependent on the capacitance and the clock frequency. Using these equivalent resistors in active filters, the filter coefficients of such a filter are purely determined by the ratio of the capacitances and the clock frequency. Fortunately, both parameters can be controlled very well in an integrated circuit, whereas time constants created by resistors and capacitances needed for conventional filters can differ of about 20%. [1]. Thus it is possible to create very precise analog filters in integrated circuits with the help of a switched capacitor design. Operational Amplifiers used for this approach have special requirements, as described below. 2) Requirements for Op-Amps in switched capacitor designs In contrast to conventional analog filters, the load of an opamp used in switched capacitor circuits in general is purely capacitive. Thus, the opamp (also called OTA) can have a high output resistance (in the order of several 100kOhm and higher) and there is no need for an output buffer stage. This also implies that during static operation no current has to be driven to the load to maintain the desired output voltage. Also, for many applications a dc gain in the order of 40-80db is sufficient, thus a single stage design can be used. Therefore, the unity gain frequency and the phase margin are determined by the output resistance and the load capacitance and no internal compensation capacitor is needed in most applications. As the opamp is supposed to change the voltage of the attached capacitors to the desired value during one clock cycle, it has to be able to deliver high output currents, thus a high slew rate is required. Also the unity gain bandwidth should be reasonably high, since this will also limit the maximum clock rate for the switches. Especially for lower clock frequencies the static bias current significantly influences the overall power consumption. Thus, for highly integrated circuits working with limited power available as battery powered devices an opamp with very low static power consumption and still sufficient performance is needed.
3) Review of proposed structures in literature To enhance the slew rate of an amplifier without increasing static power consumption there are several approaches reported in literature. Fig. 1: A symmetrical standard OTA cell [3] In a standard single stage OTA (Fig. 1), the maximum achievable output current during slewing is directly proportional to the bias current of the first stage. Thus, by reducing this current for lower power consumption we will also reduce the slew rate and limit the maximum operation frequency. To improve the slew rate of the amplifier there are several techniques reported in literature: As proposed in [2], the bias current can be dynamically adjusted by measuring the difference between the drain currents in the input stage. By increasing the bias current proportional to this difference, the slew rate can be increased. The drawback of this concept is that during slewing the whole amplifier has to manage the larger current, thus limiting design freedom. Additionally, the power consumption of the whole amplifier will increase significantly during slewing operation as all bias currents are affected. In [4] the authors propose a similar technique in which two current subtractors are used to control the bias current adaptation. (Fig. 2) Fig.2: An Adaptive biasing Opamp with enhanced DC-Gain, [4]
Whereas an OTA as shown in Fig.1 usually only has a DC-Gain of about 40dB, this design in Fig. 2 can achieve up to 90dB by using M5 and M6 as a gain enhancement circuit. However, due to the two current subtractors used the static power consumption is three times as high as without the adaptive biasing circuit. The structure in Fig. 2 was designed by the authors to work with a quiescent bias current of 10µA [4]. Because of the positive feedback in the adaptive biasing circuit the Ratio D:1 has to be carefully chosen to ensure the stability of the circuit. (D < 1) Another approach is presented in [5], Fig. 3. Here the authors use a Flipped Voltage Follower (FVF) consisting of transistors M 1A/B and M 2A/B to dynamically increase the bias current. However, as described in [6], the FVF has the big drawback of a very limited input voltage range to ensure that both transistors still operate in saturation. This problem intensifies with reduced threshold voltages. Also, for supply voltages larger than 1.5V an additional level shifter is required, thus again increasing the required quiescent power. Because of these reasons I decided against the use of this concept in my design. Fig. 3 [5] The approaches discussed so far have all focused on dynamically increasing the bias current of the whole amplifier. In [7] the authors use another method to increase the maximum possible output current. Here the difference in the input voltages is measured by an additional stage parallel to the main amplifier. Fig. 4 [7] The current sources I 2 consist each of a p-mos transistor biased in the triode region during static operation. This is achieved by choosing I 2 < I 1. Thus the voltage drop across the current sources is small and transistors M 3a and M 4a will be turned of. During slewing, the input voltages will differ and the current of 2I 1 will only flow in one tail. This results in a larger voltage drop over the associated p-mos current source and one of the output transistors M 3/4A will turn on and deliver a large current into the load. The advantage of this approach is that the enhancement circuit can be designed independently from the main amplifier thus giving more freedom to achieve lower power consumption. However, one problem of this solution still is the relative high W/L ratio of transistors M 3a and M 4a to achieve high output currents whereas the static bias currents remain small. This leads to higher capacitances of these transistors and results in a
finite response time for the enhancement circuit. Thus, to avoid overshoot caused by a too late turn-off of the enhancement circuit the transistor sizes have to be carefully chosen. 4) My design approach In this design project I plan to create an OTA with ultra low static power consumption (in the nanoampere region), which is still suitable for switched capacitor designs and thus having a high slew rate. All so far discussed circuits have a relative simple structure and therefore are suitable for low bias current operation. However, because a high input and output range and the use with medium supply voltages are desired, I will not use the approach shown in Fig. 3 [5]. My design approach will be based on the simply OTA cell shown in Fig. 1, but to support a common-mode input voltage near the negative supply (as often used in switched capacitor filters), a PMOS input structure will be used. A full rail-to-rail input stage would require an additional pair of input transistors and a balancing circuit, thus increasing the power consumption significantly. To increase the DC gain and hence increase the precision in feedback applications I will adapt the gain-enhancement circuit proposed in [4] leading to a gain of 60dB or higher. For the slew rate enhancement circuit I still consider both the techniques proposed in Fig. 2 ([2], [4]) and in Fig. 4 ([7]). The second one has the advantage of independent stages and therefore the ability to achieve higher slew rates, but the response time of the enhancement circuit might lead to an instable operation. Both techniques will be implemented in schematic level and their performance will be compared. In the second part of the project an active RC-Filter and a switched capacitor filter will be designed with the newly developed opamp to prove its suitability for operation. In case the active RC-Filter will suffer from insufficient gain due to a resistive load of the OTA, I will consider implementing a simple output buffer for reducing the output resistance. 5) Goals The main goal of my design approach is to minimize the static power consumption so that the total bias current will be in the nanoampere region. This will be achieved by using the discussed circuit structure, which only requires few active current tails in static operation. The second goal is to still provide a high slew rate for capacitive loads and sufficient precision in feedback switched capacitor applications. This will be achieved by using the proposed slew rate enhancement and gain enhancement circuits, thus allowing high output currents and a high DCgain with very low bias current. To allow operation with reasonable high clock rates, the unity gain frequency and phase margin should be quite high, too. This can be achieved by reducing transistor sizes and thus decreasing parasitic capacitances. Additionally, the output load determines the GBW significantly.
To achieve these goals sacrifices will have to be made concerning noise and input common mode voltage range. Additionally, the opamp will have a very high output resistance thus not suitable for directly driving resistive loads. 6) Design Specifications By using parameters given in the discussed literature, the following performance specifications are defined: Parameter Value Notes Supply Voltage V dd 1.5-2.5V Singly supply Supply Current <400nA @V dd =2.0V, static operation Static Power Consumption <0.8uW @V dd =2.0V Open-Loop Gain A v >60dB Phase Margin 60 or more @10pF load capacitance Unity Gain Frequency 1MHz @10pf load capacitance Minimum Load Capacitance without 1pF compensation Slew Rate +/- 25V/us @10pF load capacitance Peak Output current during slewing +/- 250uA (2500 times bias current of first stage) Settling Time 500ns @0.25%, 10pF load, 0.4V step THD @10kHz 0.9V pp 0.8% PSRR 45dB DC Input noise 100nV/Hz 1/2 Offset Voltage 10mV Input common-mode Voltage range 0V ~ V dd -0.5V Output common-mode Voltage range 0V+10mV ~ V dd -10mV The design will be optimized for power consumption (primary goal) and high slew rate (secondary goal). 7) Applications of the circuit Aside from the already mentioned switched capacitor circuits, the planned OTA can be used in every design requiring low static power consumption and the need to drive capacitive loads. One example is a sample-and-hold circuit, which requires that a buffer capacitor is charged to the level of the input voltage within a limited time frame. During the hold-stage, the amplifier does not have to deliver any current into the load, thus low static bias current will significantly reduce the overall power consumption.
8) References [1] David A. Johns, Ken Martin, Analog integrated circuit design, John Wiley & Sons, Inc. 1997, pp. 394-408 [2] Marc G. Degrauwe, Josef Rijmenants, Eric A. Vittoz, Adaptive Biasing CMOS Amplifiers, IEEE Journal of Solid State-Circuits, Vol. SC-17, No.3, June 1982, pp. 522-528 [3] Juan A. Galan, Antonio J. López-Martín, Ramón G. Carvajal, Jaime Ramírez-Angulo, Carlos Rubia-Marcos, Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54 No.3 March 2007 [4] Francesco Dalena, Vito Giannini, Andrea Baschirotto, A Low-Power adaptive biasing CMOS Operational Amplifier with enhanced DC-Gain, Research in Microelectronics and Electronics 2006, Ph. D. (IEEE Xplore) [5] Antonio J. López-Martín, Sushmita Baswa, Jaime Ramirez-Angulo, Ramón González Carvajal, Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency, IEEE Journal of Solid-State Circuits, Vol. 40, No.5, May 2005 [6] Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio J. López-Martín, Antonio Torralba, Juan Antonio Gómez Galán, Alfonso Carlosena, Fernando Muñoz Chavero, The Flipped Voltage Follower: A Useful Cell for Low-Voltage Low-Power Circuit Design, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 52 No.7 July 2005 [7] K. Nagaraj, CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique, IEEE 1990 Custom Integrated Circuits Conference [8] P. Gray, R. Meyer, MOS Operational Amplifier Design A Tutorial Overview, IEEE Journal of Solid-State Circuits, Vol. SC-17 No. 6, December 1982, pp. 969-982 [9] J. Solomon, The Monolithic Op Amp: A Tutorial Study, IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974, pp. 314-332 [10] Intersil Datasheet CA3080 2MHz, Operational Transconductance Amplifier (OTA) [11] National Semiconductors Datasheet LM13700