Programmable Timing Control Hub for P4

ICS9529 Programmable Timing Control Hub for P4 Recommended Application: CK-48 clock for Intel 845 chipset with P4 processor. Output Features: 3 - Pairs of differential CPU clocks (differential current mode) 4-3V66 @ 3.3V - PCI @ 3.3V - 48MHz @ 3.3V 24-48 MHz selectable output @ 3.3V 2 - REF @ 3.3V, 4.38MHz Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Key Specifications: CPU Output Jitter <5ps 3V66 Output Jitter <25ps CPU Output Skew <ps *MULTISEL/REF VDDREF 2 *FS2/PCICLK *FS3/PCICLK PCICLK2 VDDPCI *FS4/PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9 VDDPCI Vtt_PWRGD# RESET# *FS/48MHz *FS/24_48MHz AVDD48 Pin Configuration 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 ICS9529 48 47 46 45 44 43 42 4 4 39 38 37 36 35 34 33 32 3 3 29 28 27 26 25 48-Pin 3-mil SSOP REF/MULTSEL* VDDCPU CPUCLKT2 CPUCLKC2 PD# CPUCLKT CPUCLKC VDDCPU CPUCLKT CPUCLKC I REF AVDD VDD3V66 3V66_ 3V66_ 3V66_2 3V66_3 SCLK SDATA * Internal Pull-up resistor of 2K to VDD Frequency Table 2 7 6 5 4 FS4 FS3 FS2 FS FS 64D 2/3/3 CPUCL K MHz 3V66 MHz PCICLK MHz 2. 68. 34. 5. 7. 35. 8. 72. 36.. 74. 37. 4. 76. 38. 7. 78. 39. 2. 8. 4. 23. 82. 4. 26. 72. 36. 3. 74.3 37. 36. 68. 34. 4. 7. 35. 44. 72. 36. 48. 74. 37. 52. 76. 38. 56. 78. 39. 6. 8. 4. 64. 82. 4. 7. 68. 34. 75. 7. 35. 8. 72. 36. 85. 74. 37. 9. 76. 38. 66.8 66.8 33.4.2 66.8 33.4 33.6 66.8 33.4 2.4 66.8 33.4. 2. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

ICS9529 General The ICS9529 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC33 or DDR memory. It provides all necessary clock signals for such a system. The ICS9529 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to.mhz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple. Block Diagram PLL2 48MHz 2 TAL OSC / 2 24_48MHz REF (:) PLL Spread Spectrum CPU DIVDER CPUCLKT (2:) 3 CPUCLKC (2:) 3 PD# MULTSEL(:) FS (4:) SDATA SCLK Vtt_PWRGD# Control Logic Config. Reg. PCI DIVDER 3V66 DIVDER 4 PCICLK (9:) 3V66 (3:) RESET# I REF Power Groups Pin Number AVDD 2 47 REF output, Crystal 24 2 48MHz fixed, Fixed PLL 39 43 CPU Outputs, CPU PLL, CPU Master Clock, VDD -- 9, 8 5, 3 PCI outputs 32 29 3V66 outputs 46 36 CPU Outputs, IREF, MULTSEL 64D 2/3/3 2

ICS9529 Pin PIN NUMBER 2, 9, 8, 24, 32, 39, 46 PIN NAME MULTSEL * REF VDD 3 4 2 5, 3, 2, 29, 36, 43, 47 6 7 7, 6, 5, 4, 2,, 8 TYPE DESCRIPTION I N 3.3V LVTTL input for selecting the current multiplier for CPU outputs. O UT 3.3V, 4.38MHz reference clock output. PWR 3.3V power supply IN Crystal input, has internal load cap (33pF) and feedback resistor from 2 O UT Crystal output, nominally 4.38MHz. Has internal load cap (33pF) PWR Ground pins for 3.3V supply F S2 * I N Logic input frequency select bit. Input latched at power on. PCICLK 3.3V PCI clock output F S3 * I N Logic input frequency select bit. Input latched at power on. PCICLK 3.3V PCI clock output F S4 * I N Logic input frequency select bit. Input latched at power on. PCICLK3 PCICLK (9:4, 9 Vtt_PWRGD# 2 RESET# 2) IN 27, 28, 3, 3 3V66 (3:) 22 3.3V PCI clock output 3.3V PCI clock outputs This 5V tolerant LVTTL input is a level sensitive strobe used to determine when FS (4:) and MULTISEL inputs are valid and are ready to be sampled (active low) Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. 3.3V Fixed 66MHz clock outputs for HUB F S * I N Logic input frequency select bit. Input latched at power on. 48MHz O UT 3.3V Fixed 48MHz clock output. F S * I N Logic input frequency select bit. Input latched at power on. 23 24_48MHz 25 SDATA I/ O 26 SCLK IN 33 PWR 34 AVDD PWR 35 I REF 42 PD# 44, 4, 37 CPUCLKC (2:) 45, 4, 38 CPUCLKT (2:) 48 * Internal pull-up MULTSEL * REF resistor of 2K to VDD. Selectable 24 or 48 MHz output 2 Data pin for I C circuitry 5V tolerant 2 Clock pin for I C circuitry 5V tolerant Ground for CORE PLL Power for CORE PLL 3.3V nominal This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Asynchronous active low input pin used to power down the device into a low IN power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. I N 3.3V LVTTL input for selecting the current multiplier for CPU outputs. O UT 3.3V, 4.38MHz reference clock output. 64D 2/3/3 3

ICS9529 Maximum Allowed Current Max 3.3V supply consumption Max discrete cap loads, Condition Vdd = 3.465V All static inputs = Vdd or Powerdown Mode 4mA (PWRDWN# = ) Full Active 36mA CPUCLK Swing Select Functions MULTSEL MULTSEL Board Target Trace/Term Z 6 ohms 5 ohms 6 ohms 5 ohms 6 ohms 5 ohms 6 ohms 5 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Rr = 475 % Iref = 2.32mA Output Current Voh @ Z, Iref=2.32mA = 5*Iref.7V @ 6 = 5*Iref.59V @ 5 = 6*Iref.85V /2 6 = 6*Iref.7V @ 5 = 4*Iref.56V @ 6 = 4*Iref.47V @ 5 = 7*Iref.99V @ 6 = 7*Iref.82V @ 5 3 (DC equiv) 25 (DC equiv) 3 (DC equiv) 25 (DC equiv) 3 (DC equiv) 25 (DC equiv) 3 (DC equiv) 25 (DC equiv) Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA Rr = 22 % Iref = 5mA = 5*Iref.75V @ 3 = 5*Iref.62V @ 2 = 6*Iref.9V @ 3 = 6*Iref.75V @ 2 = 4*Iref.6 @ 2 = 4*Iref.5V @ 2 = 7*Iref.5V @ 3 = 7*Iref.84V @ 2 64D 2/3/3 4

ICS9529 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N + - *See notes on the following page. 64D 2/3/3 5

ICS9529 Byte : Functionality and frequency select register (Default=) (2,7:4) 3 2 7 6 5 4 CPUCLK 3V66 PCICLK FS4 FS3 FS2 FS FS MHz MHz MHz Spread % 2. 68. 34. +/-.25% Center spread 5. 7. 35. +/-.25% Center spread 8. 72. 36. +/-.25% Center spread. 74. 37. +/-.25% Center spread 4. 76. 38. +/-.25% Center spread 7. 78. 39. +/-.25% Center spread 2. 8. 4. +/-.25% Center spread 23. 82. 4. +/-.25% Center spread 26. 72. 36. +/-.25% Center spread 3. 74.3 37. +/-.25% Center spread 36. 68. 34. +/-.25% Center spread 4. 7. 35. +/-.25% Center spread 44. 72. 36. +/-.25% Center spread 48. 74. 37. +/-.25% Center spread 52. 76. 38. +/-.25% Center spread 56. 78. 39. +/-.25% Center spread 6. 8. 4. +/-.25% Center spread 64. 82. 4. +/-.25% Center spread 66.6 +/-.25% Center spread 7. 68. 34. +/-.25% Center spread 75. 7. 35. +/-.25% Center spread 8. 72. 36. +/-.25% Center spread 85. 74. 37. +/-.25% Center spread 9. 76. 38. +/-.25% Center spread 66.8 66.8 33.4 +/-.25% Center spread.2 66.8 33.4 +/-.25% Center spread 33.6 66.8 33.4 +/-.25% Center spread 2.4 66.8 33.4 +/-.25% Center spread to -.6% Down spread. to -.6% Down spread 2. to -.6% Down spread to -.6% Down spread - Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable - Watch dog safe frequency will be selected by latch inputs - Watch dog safe frequency will be programmed by Byte bit (4:) Note Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by 3. 64D 2/3/3 6

ICS9529 Byte : Output Control Register ( = enable, = disable) B it Pin# 7 45,44 CPUT/C2 6 38,37 CPUT/C 5 4,4 CPUT/C 4 - FS4 Read back 3 - FS3 Read back 2 - FS2 Read back - FS Read back - FS Read back Byte 2: Output Control Register ( = enable, = disable) B it Pin# 7-6 7 PCICLK_ 9 5 6 PCICLK_ 8 4 5 PCICLK_ 7 3 4 PCICLK_ 6 2 2 PCICLK_ 5 PCICLK_ 4 PCICLK_ 3 Byte 3: Output Control Register ( = enable, = disable) B it Pin# 7 23 48MHz_ 6 22 48MHz_ 5 - Reset gear shift detect = Enable, = Disable 4-3 - Sel 24_48 MHz; = 24 MHz, = 48 MHz 2 8 PCICLK_ 2 7 PCICLK_ 6 PCICLK_ Byte 4: Output Control Register ( = enable, = disable) B it Pin# 7 - MultiSEL (read back) 6 - MultiSEL (Read back) 5 3 3V66-4 3 3V66-3 48 REF 2 REF 27 3V66_ 3 28 3V66_ 2 Notes:. = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. 64D 2/3/3 7

ICS9529 Byte 5: Programming Edge Rate ( = enable, = disable) B it Pin# 7 - ( ) 6 ( ) 5 ( ) 4 ( ) 3 ( ) 2 ( ) Async. 3V66/PCI control bit Async. 3V66/PCI control bit Asynchronous 3V66/PCI Frequency Selection Table B5 bit B 5 bit = 66.MHz/33.MHz (Async with CPU) MHz/MHz (Sync with CPU) B 5 bit = 75.44MHz/37.72MHz (Async with CPU) 88.MHz/44.MHz (Async with CPU) Byte 6: Vendor ID Register ( = enable, = disable) 7 Revision ID 3 6 Revision ID 2 5 Revision ID 4 Revision ID 3 Vendor ID 3 ( ) 2 Vendor ID 2 ( ) Vendor ID ( ) Vendor ID ( ) Byte 7: Revision ID and Device ID Register Revision ID values will be based on individual device's revision 7 Device ID7 6 Device ID6 5 Device ID5 4 Device ID4 3 Device ID3 2 Device ID2 Device ID Device ID Device ID values will "28H" in this case. be based on individual device Byte 8: Byte Count Read Back Register 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Note: Writing to this register will configure byte count and how many bytes will be read back, default is F H = 5 bytes. 64D 2/3/3 8

ICS9529 Byte 9: Watchdog Timer Count Register 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 8 29ms = 2.3 seconds. Byte : Programming Enable bit 8 Watchdog Control Register 7 Programming Enable bit Program = no programming. Frequencies are selected by HW latches or Byte Enable 2 = enable all I C programing. 6 WD Enable Watchdog Enable bit. This bit will over write WDEN latched value. = disable, = Enable. 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits will configure the safe 2 SF2 frequency corrsponding to Byte 2, 7:4 table SF SF Byte : VCO Frequency M Divider (Reference divider) Control Register 7 Ndiv 8 N divider bit 8 6 Mdiv 6 5 Mdiv 5 4 Mdiv 4 The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 reference divider value. Default at power up is equal to the 2 Mdiv 2 latched inputs selection. Mdiv Mdiv Byte 2: VCO Frequency N Divider (VCO divider) Control Register 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 64D 2/3/3 9

ICS9529 Byte 3: Spread Spectrum Control Register 7 SS 7 6 SS 6 5 SS 5 4 SS 4 3 SS 3 2 SS 2 SS SS The Spread Spectrum (2:) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 4: Spread Spectrum Control Register 7 6 5 4 SS 2 Spread Spectrum 2 3 SS Spread Spectrum 2 SS Spread Spectrum SS 9 Spread Spectrum 9 SS 8 Spread Spectrum 8 Byte 5: Output Divider Control Register 7 CPUDIV3 6 CPUDIV2 5 CPUDIV 4 CPUDIV 3 CPU Div 3 2 CPU Div 2 CPU Div CPU Div CPU2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. CPU(:) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Byte 6: Output Divider Control Register 7 3V66 Div 3 6 3V66 Div 2 5 3V66 Div 4 3V66 Div 3 3V66 Div 3 2 3V66 Div 2 3V66 Div 3V66 Div 3V66(3:2) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. 3V66(:) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. 64D 2/3/3

ICS9529 Byte 7: Output Divider Control Register 7 3V66(3:2)_IN V 3V66(3:2) Phase Inversion bit 6 3V66(:)_IN V 3V66(:) Phase Inversion bit 5 CPU_INV CPUCLK_2 Phase Inversion bit 4 CPU_INV CPUCLK Phase Inversion bit 3 PCI Div 3 2 PCI Div 2 PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. PCI Div Default at power up is latched FS divider. PCI Div Table Table 2 Div (3:2) Div (:) / 2 / 4 / 8 /6 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 7 / 4 / 28 /56 Div (3:2) Div (:) / 4 / 8 / 6 /32 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 9 / 8 / 36 /72 Byte 8: Group Skew Control Register it 7 CPU_Skew These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (:) CPU_Skew = ps = 25ps = 5ps =75ps B 6 5 4 3 CPU_Skew T hese 2 bits delay the CPUCLKC/T (:) CPUCLKC/T2 2 CPU_Skew = ps = 25ps = 5ps = 75ps clock with respect to Byte 9: Group Skew Control Register Programming Sequence 7 ps 6 These 4bits control 5ps 5 CPU-3V66(3:2) 3ps 4 45ps 3 6ps 2 These 4 bits control 75ps CPU-3V66(:) 9ps 64D 2/3/3

ICS9529 Byte 2: Group Skew Control Register Programming Sequence 7 ps 6 These 4bits control 5ps 5 CPU-PCI(9:) 3ps 4 45ps 3 6ps 2 75ps Resreved 9ps Byte 2: Slew Rate Control Register 7 PCICLK_2_Slew PCICLK2 clock slew rate control bits. 6 PCICLK_2_Slew = strong: = normal; = weak 5 PCICLK (:)_Slew PCICLK(:) clock slew rate control bits. 4 PCICLK (:)_Slew = strong: = normal; = weak 3 3V66 (3:2)_Slew 3V66 (2:) clock slew rate control bits. 2 3V66 (3:2)_Slew = strong: = normal; = weak 3V66 (:)_Slew 3V66 (:) clock slew rate control bits. 3V66 (:)_Slew = strong: = normal; = weak Byte 22: Slew Rate Control Register 7 REF Slew REF clock slew rate control bits. 6 REF Slew = strong: = normal; = weak 5 PCI (9:7) Slew PCI (9:7)) clock slew rate control bits. 4 PCI (9:7) Slew = strong: = normal; = weak B it 3 PCI (6:5) Slew PCI (6:5) clock slew rate control bits. B it 2 PCI (6:5) Slew = strong: = normal; = weak B it PCI (4:3) Slew PCI (4:3) clock slew rate control bits. B it PCI (4:3) Slew = strong: = normal; = weak Byte 23: Slew Rate Control Register 7 6 5 4 3 48MHz Slew 48MHz clock slew rate control bits. 2 48MHz Slew = strong: = normal; = weak 24_48MHz Slew 24_48MHz clock slew rate control bits. 24_48MHz Slew = strong: = normal; = weak 64D 2/3/3 2

ICS9529 Absolute Maximum Ratings Supply Voltage................................ 5.5 V Logic Inputs...................................5 V to V DD +.5 V Ambient Operating Temperature................. C to +7 C Case Temperature............................. 5 C Storage Temperature........................... 65 C to +5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7C; Supply Voltage V DD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS -.3.8 V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 ma Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 ma Operating C L = pf; Select @ 66M ma I DD3.3OP Supply Current C L = Full load 36 ma Power Down IREF=2.32 25 ma I Supply Current DD3.3PD IREF= 5mA 45 ma Input frequency F i V DD = 3.3 V; 4.38 MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C out Out put pin capacitance 6 pf C IN & 2 pins 27 36 45 pf Transition Time T trans To st crossing of target Freq. 3 ms Settling Time T s From st crossing to % target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Delay t PZH,t PZH output enable delay (all outputs) ns t PLZ,t PZH output disable delay (all outputs) ns Guarenteed by design, not % tested in production. 64D 2/3/3 3

ICS9529 Electrical Characteristics - CPU.7V Current Mode Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω Voltage High VHigh Statistical measurement on single 66 77 85 Voltage Low VLow ended signal using oscilloscope math function. -5 5 5 mv Max Voltage Vovs Measurement on single ended 756 5 mv Min Voltage Vuds signal using absolute value. -3-7 Crossing Voltage (abs) Vcross(abs) 25 35 55 mv Crossing Voltage (var) d-vcross Variation of crossing over all edges 2 4 mv Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 2MHz nominal 4.9985 5.5 ns 2 2MHz spread 4.9985 5.266 ns 2 MHz nominal 5.9982 6.8 ns 2 Average period Tperiod MHz spread 5.9982 6.32 ns 2 MHz nominal 7.4978 7.523 ns 2 MHz spread 7.4978 5.4 ns 2.MHz nominal 9.997.3 ns 2.MHz spread 9.997.533 ns 2 2MHz nominal 4.8735 ns,2 Absolute min period T absmin MHz nominal/spread 5.8732 ns,2 MHz nominal/spread 7.3728 ns,2.mhz nominal/spread 9.872 ns,2 Rise Time t r V OL =.75V, V OH =.525V 75 332 7 ps Fall Time t f V OH =.525V V OL =.75V 75 344 7 ps Rise Time Variation d-t r 3 25 ps Fall Time Variation d-t f 3 25 ps Measurement from differential Duty Cycle d t3 wavefrom 45 49 55 % Skew t sk3 V T = 5% 8 ps Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 6 5 ps Guaranteed by design, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 4.388MHz 64D 2/3/3 4

ICS9529 Electrical Characteristics - PCICLK T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -33-33 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V 45 55 % Skew t sk V T =.5 V 5 ps Jitter t jcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. Electrical Characteristics - 3V66 T A = - 7 C; V DD = 3.3 V +/-5%; C L =-3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH V OH @ MIN =. V, V OH @ MA = 3.35 V -33-33 ma Output Low Current I OL V OL @ MIN =.95 V, V OL @ MA=.4 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V 45 55 % Skew t sk V T =.5 V 25 ps Jitter tjcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. 64D 2/3/3 5

ICS9529 Electrical Characteristics - 48MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O V O = V DD *(.5) 48.8 MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH V OH @ MIN =. V, V OH @ MA = 3.35 V -29-23 ma Output Low Current I OL V OL @ MIN =.95 V, V OL @ MA=.4 29 27 ma 48DOT Rise Time t r V OL =.4 V, V OH = 2.4 V.5 ns 48DOT Fall Time t f V OH = 2.4 V, V OL =.4 V.5 ns VCH 48 USB Rise Time t r V OL =.4 V, V OH = 2.4 V 2 ns VCH 48 USB Fall Time tf V OH = 2.4 V, V OL =.4 V 2 ns 48 DOT to 48 USB Skew tskew VT=.5V ns Duty Cycle d t V T =.5 V 45 55 % Jitter t jcyc-cyc V T =.5 V 35 ps Guaranteed by design, not % tested in production. Electrical Characteristics - REF T A = - 7 C; V DD = 3.3 V +/-5%; C L =-2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O 4.38 MHz Output Impedance R DSP V O = V DD *(.5) 2 6 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -29-23 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 29 27 ma Rise Time t r V OL =.4 V, V OH = 2.4 V 4 ns Fall Time t f V OH = 2.4 V, V OL =.4 V 4 ns Duty Cycle d t V T =.5 V 45 55 % Jitter t jcyc-cyc V T =.5 V ps Guaranteed by design, not % tested in production. 64D 2/3/3 6

ICS9529 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 64D 2/3/3 7

ICS9529 Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_ is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 PCICLK_F and PCICLK Tpci Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP SYMBOL CONDITIONS MIN TYP MA UNITS 3V66 3V66 3V66 pin to pin skew 5 ps PCI PCI PCI_F and PCI pin to pin skew 5 ps 3V66 to PCI S 3V66-PCI 3V66 leads 33MHz PCI.5 3.5 ns Guarenteed by design, not % tested in production. 64D 2/3/3

ICS9529 INDE AREA N 2 D E A E h x 45 c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A 2.4 2.8.95. A.2.4.8.6 b.2.34.8.35 c.3.25.5. D SEE VARIATIONS SEE VARIATIONS E.3.68.395.42 E 7.4 7.6.29.299 e.635 BASIC.25 BASIC h.38.64.5.25 L.5.2.2.4 N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A 3 mil SSOP Package -C- - SEATING PLANE. (.4) C -34 VARIATIONS D mm. D (inch) N MIN MA MIN MA 48 5.75 6..62.63 Reference Doc.: JEDEC Publication 95, MO-8 Ordering Information Example: 64D 2/3/3 ICS9529yFLF-T ICS y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device