EPC6C EPC6C Enhancement Mode Power Transistor V DSS, V R DS(on), 6 mω I D, 8 A G D S EFFICIENT POWER CONVERSION HAL Gallium Nitride s exceptionally high electron mobility and low temperature coefficient allows very low R DS(on), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE UNIT V DS Drain-to-Source Voltage (Continuous) V Drain-to-Source Voltage (p to, 5 ms pulses at 5 C) V Continuous (T A =, θ JA = 3.4) 8 I D Pulsed (5 C, T PULSE = µs) 75 Gate-to-Source Voltage 6 V GS Gate-to-Source Voltage -4 T J Operating Temperature 4 to 5 T STG Storage Temperature 4 to 5 Thermal Characteristics PARAMETER TYP UNIT RJC Thermal Resistance, Junction to Case RJB Thermal Resistance, Junction to Board 4 RJA Thermal Resistance, Junction to Ambient (Note ) 69 A V C C/W Note : RθJA is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/appnote_thermal_performance_of_egan_fets.pdf for details. EPC6C egan FETs are supplied only in passivated die form with solder bars. Die size:. mm x.6 mm Applications High Speed DC-DC conversion Class-D Audio High Frequency Hard-Switching and Soft-Switching Circuits Benefits Ultra High Efficiency Ultra Low RDS(on) Ultra Low QG Ultra Small Footprint www.epc-co.com/epc/products/eganfets/epc6c.aspx All measurements were done with substrate shorted to source. Static Characteristics (T J = 5 C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BV DSS Drain-to-Source Voltage V GS = V, I D = μa V I DSS Drain-Source Leakage V GS = V, V GS = 8 V 5 5 µa I GSS Gate-to-Source Forward Leakage V GS = 5 V.5 3 ma Gate-to-Source Reverse Leakage V GS = -4 V.5.5 ma V GS(TH) Gate Threshold Voltage V GS = V GS, I D = 3 ma.8.4.5 V R DS(on) Drain-Source On Resistance V GS = 5 V, I D = A 6 mω V SD Source-Drain Forward Voltage I S =.5 A, V GS = V.8 V EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
EPC6C C ISS Dynamic Characteristics (T J = 5 C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Capacitance 36 4 C OSS Output Capacitance V GS = V, V DS = 5 V pf C RSS Reverse Transfer Capacitance 3. 4.8 R G Gate Resistance.4 Ω Q G Total Gate Charge 3.4 4.5 Q GS Gate-to-Source Charge. V DS = 5 V, I D = A Q GD Gate-to-Drain Charge.55 nc Q G(TH) Gate Charge at Threshold.7 Q OSS Output Charge V GS = V, V DS = 5 V 6 4 Q RR Source-Drain Recovery Charge All measurements were done with substrate shorted to source. 75 Figure : Typical Output Characteristics at 5 C 75 Figure : Transfer Characteristics ID Drain Current (A) 6 45 5 V GS = 5 V V GS = 4 V V = 3 V GS V GS = V ID Drain Current (A) 6 45 5 V DS = 3 V.5.5.5 3 V DS Drain-to-Source Voltage (V).5.5.5 3 3.5 4 4.5 5 RDS(on) Drain to Source Resistance (mω) 5 4 Figure 3: R DS(on) vs. V GS for Various Currents I D = 8 A I D = A I D = A I D = 4 A RDS(on) Drain to Source Resistance (mω) 5 4 Figure 4: R DS(on) vs. V GS for Various Temperatures I D = A.5 3 3.5 4 4.5 5.5 3 3.5 4 4.5 5 EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8
EPC6C 6 Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale) 5 C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD Capacitance (pf) 4 Capacitance (pf) C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD 4 6 8 V DS Drain-to-Source Voltage (V) 4 6 8 V DS Drain-to-Source Voltage (V) VGS Gate to Source Voltage (V) 5 4.5 4 3.5 3.5.5.5 Figure 6: Gate Charge I D = A V DS = 5 V ISD Source to Drain Current (A) 36 4 8 6 Figure 7: Reverse Drain-Source Characteristics.5.5.5 3 3.5 Q G Gate Charge (nc).5.5.5 3 3.5 4 4.5 5 V SD Source-to-Drain Voltage (V) Normalized On-State Resistance RDS(on).8.7.6.5.4.3...9.8 Figure 8: Normalized On Resistance vs. Temperature I D = A V GS = 5 V 5 5 75 5 5 T J Junction Temperature ( C ) Normalized Threshold Voltage.4.3...9.8.7.6 Figure 9: Normalized Threshold Voltage vs. Temperature I D = 3 ma 5 5 75 5 5 T J Junction Temperature ( C ) All measurements were done with substrate shortened to source. EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8 3
EPC6C Figure : Gate Current IG Gate Current (ma) 8 6 4 3 4 5 6 Figure : Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance... Duty Factors:.5...5.. Single Pulse Junction-to-Board Notes: Duty Factor = t p /T Peak T J = P DM x Z θjb x R θjb + T B -5-4 -3 - - t p - Rectangular Pulse Duration [s] P DM t p T ZθC, Normalized Thermal Impedance.. Duty Factors:.5...5.. Junction-to-Case. Single Pulse Notes: Duty Factor = t p /T Peak T J = P DM x Z θjc x R θjc + T C. -5-4 -3 - - t p - Rectangular Pulse Duration [s] P DM t p T EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8 4
EPC6C Figure : Safe Operating Area I D - Drain Current (A) Pulse Width ms ms ms μs limited by R DS(on).. V DS - Drain-Source Voltage (V) T J = Max Rated, T C = +5 C, Single Pulse TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7 reel d e f g Loaded Tape Feed Direction 7 reel a b c 6 YYYY ZZZZ Die orientation dot Gate solder bar is under this corner EPC6C (note ) Dimension (mm) target min max a 8. 7.9 8. b.75.65.85 c (see note) 3.5 3.45 3.55 d 4. 3.9 4. e 4. 3.9 4. f (see note)..95.5 g.5.5.6 Die is placed into pocket solder bar side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 6 Die orientation dot Gate Pad bump is under this corner YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking line Lot_Date Code Marking Line 3 EPC6C 6 YYYY ZZZZ EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8 5
EPC6C DIE OUTLINE Solder Bar View c d X f A f X4 3 4 5 6 B DIM MICROMETERS MIN Nominal MAX A 76 6 36 B 6 63 66 c 379 38 385 d 577 58 583 e 35 5 65 f 95 5 g 4 4 4 e g g X3 Side View RECOMMENDED LAND PATTERN (units in µm) The land pattern is solder mask defined. 3 4 5 6 Pad no. is Gate; Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; 8 X3 36 6 63 56 X (685) 85 Max +/- SEATING PLANE Pad no. is Substrate. X4 8 8 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. egan is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/aboutepc/patents.aspx Information subject to change without notice. Revised April, 8 EPC EFFICIENT POWER CONVERSION CORPORATION WWW.EPC-CO.COM COPYRIGHT 8 6