Fabrication and Characterization of Pseudo-MOSFETs as part of the lab course condensed matter physics Summer Term 2016 April 20, 2016 Contents 1 Introduction 2 1.1 short-channel effects (SCE)..................... 2 1.2 aim of the lab course......................... 3 2 The pseudo-mosfet 4 2.1 principle of operation......................... 5 3 Device Fabrication 8 3.1 First Lithography........................... 10 3.2 Mesa etch............................... 10 3.2.1 SF 6 etch............................ 11 3.2.2 O 2 plasma........................... 11 3.3 Second Lithography.......................... 11 3.4 aluminum deposition......................... 12 3.5 Lift-off................................. 13 4 Electrical Measurement and Characterization 13 5 Writing your Report 14 6 Short Questions / Self Test 16 1
1 Introduction In recent years, microelectronics has undergone an enormous evolution with a steadily increasing performance and complexity of integrated circuits that has been made possible by modern CMOS technology. Figure 1 shows a schematic of a conventional n-type bulk-si MOSFET consisting of highly n-type doped source and drain areas within a p-type substrate. In addition, a MOSFET features a gate electrode of length L and width W that is insulated from the bulk-si substrate by an insulator (typically SiO 2 ) of thickness d ox. The two p-n-junctions at the source-channel and channel-drain interfaces (see Fig. 1 (b)) prevent a current from flowing from source to drain. Applying a positive gate voltage V gs, an inversion layer is created at the channel/gate oxide interface since negative charge is injected into the channel from the source/drain contacts. If in addition a source-drain bias is applied, a current flows through the device. The saturation current through a MOSFET is to first order given by the following expression: W I d µ eff L C (V gs V th ) 2 ox (1) 2 where C ox = ε 0 ε ox /d ox is the geometrical oxide capacitance per unit area, µ eff is the effective carrier mobility and V gs,th are the gate and threshold voltages, respectively. Obviously, a higher current (which translates into a faster performing integrated circuit) is obtained when the channel length L is scaled down and/or the effective carrier mobility is increased. In the past, a performance increase of MOSFET devices has almost exclusively been obtained by (down-)scaling the transistor dimensions. However, in the very near future continuing the downscaling will become difficult due to a number of issues. 1.1 short-channel effects (SCE) One of the major obstacles is related to the appearance of so-called short channel effects (SCE), i.e. a loss of electrostatic gate control over the potential in the channel region. Short channel effects arise due to an overlap of the source-channel and channel-drain p-n-junctions yielding a strongly reduced potential barrier as illustrated in Fig. 1 (b). SCE are deleterious since they lead to drastically increased off-state leakage currents and thus to an enormous increase of the power consumption of highly integrated circuits. Therefore, some of the semiconductor industry s main players have replaced the traditional bulk-si substrates with silicon-on-insulator (SOI) technology. SOI substrates consist of a thin silicon layer of thickness d SOI on top of a socalled buried oxide (BOX) of thickness d box. A major benefit of SOI is that short channel effects can be suppressed effectively by scaling down the SOI-layer thickness d SOI. Different types of SOI with ultrathin BOX and/or ultrathin top silicon 2
(a) (b) L V gs z y x W gate source drain n ++ n ++ p-silicon d ox V ds E (a.u.) gate source channel drain drain E L Φ f 0 L λ Figure 1: (a) Schematics of a conventional bulk-si MOSFET. (b) Illustration of the appearance of short channel effects in a scaled device: the white line represents the conduction band along current transport direction in a long-channel device. In a device suffering from SCE, the source-channel and channel-drain p-n-junctions overlap leading to a lowering of the potential barrier in the channel (green solid line). As a result, devices exhibiting SCE show an exponentially increased off-state leakage leading to a drastic increase of power consumption and eventually a loss of the ability to switch the device. layer, strained-silicon-on-insulator and even replacing the silicon completely with Germanium have been investigated intensively in recent years. 1.2 aim of the lab course In order to characterize the SOI-substrates, a fast turn-around characterization method is required. To this end so-called Pseudo-MOSFETs are fabricated for the extraction of e.g. the carrier mobility (explained in detail below). In the present lab-training, such Pseudo-MOSFET devices on SOI will be fabricated and characterized. Concerning their electrical characteristics, Pseudo-MOSFETs are low performance devices and as such they would never be used in practical applications, however they can be used to extract the relevant parameters of their substrate material. Despite the simplicity of their build-up, a variety of parameters could be extracted. Out of those, only the threshold voltage and the inverse subthreshold slope of the fabricated Pseudo-MOSFET and the carrier mobilty of the top silicon layer of the SOI material (see Fig. 2) shall be determined within the scope of this lab course. SOI MATERIAL top-si buried oxide (BOX) bulk- Figure 2: schematics of SOI material 3
2 The pseudo-mosfet In SOI substrates the active silicon layer is separated from a silicon handle wafer by a (rather thick) oxide, called the buried oxide (BOX). The idea of the pseudo- MOSFET is to use this buried oxide as the actual gate oxide and the silicon handle wafer as the gate electrode. In this case, only source and drain contacts have to be defined in order to fabricate a MOSFET structure. The pseudo-mosfet concept allows a quick and straight-forward realization of MOSFETs and is therefore widely used to study SOI material. In order to characterize the SOI material, in particular with respect to mobility, a simple model for the current through a MOSFET is employed: For small V ds the drain current I d increases linearly with drain voltage. In this so called linear regime of the output characteristics (i.e. I d versus drain-source voltage (V ds ) for different gate voltages V gs ) the current is given by I d = f g C ox µ 1 + θ(v gs V th ) (V gs V th )V ds. (2) Again, C ox = ϵ 0ϵ ox d ox is the gate oxide capacitance per unit area and d ox is the buried oxide thickness in the present case. V th is the threshold voltage, i.e. the gate voltage where the device switches from the off- to the on-state and f g is a factor that accounts for the geometry of the device. The factor θ takes series resistances into account, and is considered independent of the gate voltage. Figure 3 (a) and (b) show the output and transfer characteristics of a MOS- FET. An important figure of merit of a MOSFET is the so-called transconductance g m which is the derivative of the drain current with respect to gate voltage: g m = I d(v ds = const.) V gs (3) The quality of the SOI material is reflected in the electronic transport properties of the material, i.e. in the effective carrier mobility µ. In order to determine the mobility µ from the device characteristics we use the so-called I d / g m -method since it provides values for µ which are not influenced by parasitic series resistances. With Eqn. (2) and (3) it is easy to show that f g µc ox V ds (V gs V th ) = I d gm (4) Therefore, measuring I d versus V gs at small drain-source bias, calculating g m and plotting I d / g m versus V gs yields a straight line. The slope of this line is 4
(a) output characteristics (b) 10 0 transfer characteristics 0.8 I d (a.u.) non-saturation saturation 4 V g 3 V g 2 V g 1 V g log(i d ) (a.u.) 10-2 10-4 10-6 10-8 subthreshold swing 0.6 0.4 0.2 I d (a.u.) V ds (a.u.) 0 0.5 1 1.5 2 2.5 3 0 ~Vth V gs (V) Figure 3: Schematic cross section (a), output (b) and transfer (c) characteristics of a MOS- FET. simply f g µc ox V ds from which the mobility µ can be extracted provided that the geometry factor f g is known. In rectangular MOSFETs f g is the ratio of channel width and channel length f g = W/L. However, since in our experiment we deal with circular pseudo-mosfets the geometry factor is a little more complicated. Nevertheless, a closed expression for the ratio between width and length can be computed also in the circular case: f g = pseudo-mosfet as shown in Fig. 10. 2.1 principle of operation 2π ln(r/r) where R, r are radii of the circular One might ask, why the pseudo-mosfet is able to operate despite the simplicity of its buildup. In a conventional MOSFET the doping of source and drain areas leads to the formation of a barrier which can be manipulated by varying the gate voltage. Fig. (4) shows how the barrier is formed. The figure on the left shows the schematic band diagrams of all areas involved and still separated, the right hand side is the result after their connection. Please be aware that the term connecting is only an aid to understanding the principle and doesn t describe the physical process. In the actual device a Fermi level equilibrium is established, causing the conduction and valence band edges in the channel to elevate and thus forming a barrier for electrons in source and drain areas. The height of the barrier is controlled by the electrostatic potential in the channel, which is itself being varied by the gate voltage applied. However, in a pseudo-mosfet only the channel might (but doesn t even need to) be doped, whereas source and drain are plain metal contacts directly de- 5
conduction bands conduction band E C E F E G = 1.12eV E V n + i n + n + i n + SOURCE CHANNEL DRAIN SOURCE CHANNEL DRAIN valence bands valence band Figure 4: Schematic band diagram of a MOSFET in silicon, in the case of separated (a) and continuous (b) areas in the device. E V and E C denote the band edges of valence and conductance band, respectively, E F is the Fermi energy. In case of an average n-type doping (= n + ), E C E F is approx. 40...60 mev, i denotes undoped (= intrinsic) areas. Here, the Fermi level is in the middle of the bandgap. posited onto the silicon. In order to exhibit a behaviour similar to a conventional MOSFET, another effect must be responsible for the voltage controllable current in the device. This effect is the formation of a Schottky barrier, which is created upon the direct connection of a metal to a semiconductor. For a better understanding of this effect schematic band diagrams are of great importance. As soon as the semiconductor is brought into contact with a metal (Aluminum in the case of this lab course), the Fermi niveau of the semiconductor and the Fermi niveau of the metal again establish a thermodynamic equilibrium. The occuring band deformation in consequence leads to the formation of a barrier. Note though, that the actual Schottky barrier is formed directly at the interface between metal and semiconductor. Thus, the spikes in Fig. (5) and (6) at the transition between metal and channel are the actual Schottky barriers. The height of the Schottky barriers is determined by material parameters 1 and can t be influenced by the applied gate voltage. However, the electrostatic potential within the channel can be changed via the gate voltage and in consequence modify the height of the conductance band edge in the channel. On comparing the band diagrams of conventional and pseudo-mosfets the structural similarity is obvious, however the n-channel MOSFET exhibits a similar behaviour as the p-channel pseudo-mosfet and vice versa. 1 Namely the work function Φ m of the metal and electron affinity χ of the semiconductor. In the case of an Al - Si contact the smallest possible barrier height is E B = E g e (Φ m χ) = 1.12 ev (4.26 ev 4.05 ev) = 0.91 ev. This value is purely theoretical, as the actual barrier height is strongly influenced by surface contamination, surface defects, interface layers and imperfections. All these effects will, in practice, lead to a significantly increased barrier height. 6
conduction band conduction band Schottky barrier E C E F E G = 1.12eV E F METAL n + CHANNEL valence band E V METAL n + METAL CHANNEL METAL Figure 5: Schematic band diagram of a pseudo-mosfet with n-channel in silicon, in the case of separated (a) and continuous (b) areas in the device. E V and E C denote the band edges of valence and conductance band, respectively, other indices as before. Another feature of the pseudo-mosfet is its ambipolarity, which means that it can operate with positive and negative gate voltages and shows classical MOSFET characteristics for both regimes. For the measurement evaluation one has to make sure to use the right configuration of gate voltage and source-drainvoltage: the majority carriers are different for different polarities! It can be holes or electrons to be the majority charge carriers contributing to the on-current, therefore the extracted parameters for carrier mobility and transconductance will be those for the respective carrier type. 7
conduction band conduction band E F E G = 1.12eV E C E F Schottky barrier METAL p + CHANNEL valence band E V METAL p + METAL CHANNEL METAL Figure 6: Schematic band diagram of a pseudo-mosfet with p-channel in silicon, in the case of separated (a) and continuous (b) areas in the device. E V and E C denote the band edges of valence and conductance band, respectively, other indices as before. 3 Device Fabrication The fabrication of the devices will be carried out in the clean room facility of the Institute of Semiconductor Electronics. The advisor will instruct the participants how to dress and how to behave in the clean room. In order to avoid contamination participants have to wear gloves at all times when being in the clean room. Protective clothing such as apron, a second pair of gloves with sleeves and a face shield is mandatory when working with hazardous chemicals. Depending on the number, each participant or each pair of participants will get one SOI sample (sized 15 x 15 mm) for the pseudo-mosfets. The fabrication procedure is listed below. During your lab-work, protocol the fabrication process and take as many notes as necessary since this will be attached to the written report as an appendix. 8
1. PREPARED SAMPLES 2. SPIN-ON RESIST & LITHOGRAPHY 3. DEVELOPMENT 4. DRY ETCH IN SF 6 PLASMA Top-Si (SOI) buried oxide (BOX) Resist Resist SOI BOX Resist SOI BOX Resist Mesa BOX 0. INITIAL SUBSTRATE 9. FINAL DEVICE AFTER LIFT OFF Top-Si (SOI) buried oxide (BOX) Al Mesa BOX 5. RESIST REMOVAL 6. SECOND LITHOGRAPHY 7. DEVELOPMENT 8. ALUMINUM DEPOSITION Mesa Resist Mesa Resist Mesa Aluminum Resist Mesa BOX BOX BOX BOX Figure 7: Schematics of the contact formation process 9
The participants will be given prepared samples. These consist of silicon-oninsulator (SOI) material with variable Top-Si (SOI) and oxide (BOX) thicknesses. Follow these steps carefully, advice and additional information will be given throughout the entire course. 3.1 First Lithography bake samples on a hot plate for 5 mins to desorb any water on the surface 5 min @ 120 C let samples cool down for 30 s apply adhesion promoter TI-Prime spin-on TI-Prime, 30 s @ 3000 rpm soft-bake samples, 2 min @ 120 C let samples cool for a minute apply resist (AZ5214E), spin on, 30 s @ 3000 rpm soft-bake resist, 1 min 30 s @ 95 C expose samples using the correct mask develop samples, 35 s in AZ 726 MIF rinse samples in DI water for 5 min 3.2 Mesa etch The first lithography has defined the areas which shall remain unetched in this following process. By using an SF 6 -Plasma the unprotected top silicon areas will become etched away, leaving behind areas of silicon on oxide. These areas are called mesas (pl., sing. mesa) 2. The mesa etch is a common initial step when using SOI material, its purpose is the electrical isolation of adjacent devices on the chip. 2 The name actually describes the geological phenomenon of a flat-topped mountain, another explanation is derived from the spanish word mesa, which means table. Just like the table mountains, the remaining silicon areas look like flat-topped mountains on an area of silicon dioxide, only a little smaller. They also serve as the table for the next process steps, namely depositions, for instance. 10
3.2.1 SF 6 etch The actual etching takes place in a first plasma process using sulphur hexafluoride (SF 6 ). The etching rate of this process is about 50 nm/min and is therefore a matter of minutes, depending on the top silicon layer thickness. 3.2.2 O 2 plasma When using the above process to dry etch silicon, the resist will become exposed to a higher temperature, which causes the resist to harden. This in turn complicates a subsequent resist removal, because solvents (acetone, propanol) will be unable to completely remove the resist mask after the etching if it has hardened. In order to remove the resist directly after the etching, a 40 minute oxygen plasma is used. O 2 plasmas exhibit a very good resist removal capability, the oxygen radicals directly interact with organic solids (and many more chemicals) to form mostly gaseous reaction products which will be pumped away. The oxygen plasma process is therefore also known as plasma ashing. 3.3 Second Lithography After the oxygen plasma process some reaction by-products might have contaminated the surface. Therefore the following cleaning procedure shall be carried out before the second lithography. boil samples in acetone, 5 min boil samples in propanol, 5 min rinse in DI water, 5 min After the cleaning, the second lithography can be carried out. This lithography is a negative tone lithography using the same resist as before, but in a so-called image reversal process. It allows using the same resist for both positive and negative processes. bake samples on a hot plate for 5 mins to desorb any water on the surface 5 min @ 120 C let samples cool down for 30 s apply adhesion promoter TI-Prime spin-on TI-Prime, 30 s @ 3000 rpm soft-bake samples, 2 min @ 120 C 11
let samples cool for 30 s apply resist (AZ5214E), spin on, 30 s @ 3000 rpm soft-bake resist, 1 min 30 s @ 95 C expose samples using the correct mask 2 s @ 15 mw cm 2, 405 nm reverse-bake samples, 2 min @ 115 C flood expose samples, 9 s @ 15 mw cm 2, 405 nm develop samples, 35 s in AZ 726 MIF 3.4 aluminum deposition Working with hydrofluoric acid (HF) requires extreme attention! This acid is one of the most dangerous acids to be used in direct handling. A palmsized area of your body exposed to HF can lead to a lethal injury. Working in a fume hood is mandatory, as well as the use of adequate personal safety equipment when handling this agent. In this case: apron, face shield and acid gloves. Prior to the deposition of aluminum, the so-called native oxide has to be removed, in order to achieve a good electrical contact between aluminum and silicon. The native oxide is a thin (1-4 nm) layer of silicon dioxide which occurs when silicon is exposed to atmosphere. It has excellent properties as an electrical isolator, and it is easy to understand that isolation is undesired when creating metal contacts. The native oxide is removed by a 1% HF solution. Put the samples into a plastic beaker containing HF until the liquid is completely repelled by the sample surface (i.e. the samples become hydrophobic). Afterwards, rinse in DI water for 5 min. Directly after this so-called HF dip the samples have to be put into the evaporation chamber which then needs to become evacuated immediately to prevent a re-oxidization of the sample surface. Once the vacuum has reached the desired process pressure (usually in the range of 10 6 mbar, requires pumping over night) the deposition can be carried out. The target thickness is 100 to 150 nm. 12
3.5 Lift-off After aluminum has been deposited, the entire sample surface is covered with aluminum and the underlying structure can merely be seen. The second lithography has defined exactly those areas who shall be the contacts, the resist structure has openings here and aluminum is in direct contact with the silicon. Everywhere else on the sample surface the aluminum is deposited onto the resist. If the resist is dissolved in a suitable solvent, it can lift the overlying aluminum layer and thereby remove it. This process is called lift-off. Put the samples into aceton and wait until all undesired aluminum has been lifted. Depending on resist sensitivity and aluminum thickness, this process may take up to 20 min. Gently moving and turning the sample holder might assist in this process. If still no lifting can be observed, ultrasonic agitation can be necessaray. Rinse the samples in propanol (approx. 2 min) and blow them dry with nitrogen. 4 Electrical Measurement and Characterization Electrical measurements will be performed with a Semiconductor Parameter Analyser. The sample will be mounted in a probe station as schematically shown in Fig. 8. The following measurements and characterizations should be made: Figure 8: Schematics of the measurement set-up. Measure (all devices) the drain current versus gate voltage (transfer characteristics) over a large gate/ drain voltage range (e.g. ±40V) for various drain voltages. Plot the transfer characteristics on a linear and a log-scale plot. Compare the on-currents, the leakage currents due to the ambipolar behavior and the inverse subthreshold slopes of the different devices. 13
Measure (all devices) the output characteristics over the same drain and gate voltage range. Plot the output characteristics. To increase the device performance it is possible to improve the connection (of the measurement setup) to the gate by using conductive silver paste. Extract the mobility of the fabricated samples using the I d / g m -method. Plot the mobility versus the channel length of the different devices. If you have problems to measure both, output and transfer characteristics, you can derive the missing graph from the available data. Do not forget that the expected voltages for the different regions of the characteristic depend on device geometry. Figure 9: Output and derived transfer characteristic 5 Writing your Report After the characterization you are supposed to write a short report. Since writing reports is often considered as being boring you should write it with the following background: After finishing your MSc degree at RWTH Aachen University you work for an up-and-coming consulting company in the semiconductor industry. Your speciality is the implementation of new materials into existing CMOS production lines and you have been called by the CTO (chief technical officer) - one of your friends - of a foundry that has been producing logic ICs with conventional bulk silicon substrates. The CEO (chief executive officer) of the foundry has only a limited technical background but has to decide between several technology options. To save costs he would like to run the standard bulk silicon process also when producing the next generation CMOS circuits. Furthermore, he suspects that the 14
carrier mobility in SOI is lower compared to bulk and that moving to SOI does not pay off. The CTO on the other hand calculated that the next generation devices would suffer from SCE so severe that they cannot be used for the company s products anymore. He argues that the company has to move from bulk to SOI substrates which, however, implies a severe financial investment into new fabrication tools. The CTO discusses her findings with the CEO who is absolutely not amused and tells your friend that he recently read in the PM! magazine that the mobility in SOI is worse than in bulk and moving to SOI technology would not pay-off since the financial investments would be too cost-intensive. Your friend agrees but replies that the investments are necessary in order to keep-up with the company s competitors and that SOI is the way to go. The CTO is worried that the CEO will ruin the company with launching a new product that will eventually exhibit a worse performance than its predecessors. So, she decides to hire you to perform a technical study on SOI. Based on your experimental results derive a recommendation in the following way: Write a cover letter stating your recommendation, the key benefits (and potential drawbacks) of using SOI technology. Point out to the enclosed material that backs up your recommendation (the technical annex which contains the results of your experimental work). Remember that the CEO has only a limited technical background - he understands dollars not MOS- FETs. Therefore, the style of the letter should be a mixture of businessand technical-like. But most of all it should be convincing! You might want to use this opportunity to give your consulting company a fancy name. Prepare a technical annex. In this annex you should explain and discuss the pseudo-mosfet results. You should also state and explain shortly the method you used to obtain the mobility data and the experimental procedure. To this annex your lab notes could be added. Refer to these notes in the technical annex. Even though you have been hired by your friend to approve his technical recommendation, do not forget to either prove it by your data or even reject it (if this is your result). The report can either be written in German or English. Annex Bibliography M.S. Sze, Physics of Semiconductor Devices, John Wiley& Sons Inc., 1981. 15
3290µm 600µm 600µm 1580µm 1580µm 2250µm 1390µm 6390µm 600µm 5490µm 400µm 1640µm 1640µm 3290µm 1640µm 200µm 390µm 574µm Figure 10: Measures of the circle pattern exposed onto the sample. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998. J.-P. Colinge, -on-insulator Technology: Materials to VLSI, Kluwer Academic Publisher, 2004. 6 Short Questions / Self Test 1. What is the Pseudo-MOSFET used for in the scope of this lab course? 2. What is the difference between first and second lithography? 3. Which vertical edge profile will the SF 6 etching yield? 4. How can the native oxide be removed? 5. Which scale of the y-axis has to be used in order to determine the transconductance g m, linear or log? 6. How does the mobility depend on I D S and g m? 7. Which parameters of your substrate influence the device characteristic? 16
8. What parameters should be measured after device fabrication? 9. How do you measure these parameters? 10. What is the main goal of this experiment? 17