Rev..1 29 August 28 T D Objective data sheet 1. General description 2. Features T A The is a CMOS real time clock and calendar with an integrated temperature compensated crystal oscillator (TCXO) and a 32.768 khz quartz crystal optimized for very high accuracy and very low power consumption. The has a selectable I 2 C-bus and SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function and many other features. Temperature compensated crystal oscillator (TCXO) with integrated capacitors Accuracy: ±3 ppm from 2 C to +7 C Integration of a 32.768 khz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes and seconds Timestamp input pin Timestamp function with interrupt capability Two line bi-directional 1 MHz fast mode plus I 2 C interface 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage pin Battery low detection Power-on reset Oscillator stop detection Open-drain interrupt 1 second or 1 minute interrupt output Programmable watchdog timer with interrupt and reset capability Programmable alarm function with interrupt capability Programmable square wave output pin Clock operating voltage: 1.2 V to 4.2 V Low supply current; typical.65 µa at = 3. V and T amb = 25 C
T D T A 3. Ordering information Table 1. Ordering information Type number Package Name Description Version T/1 SO2 plastic small outline package; 2 leads; body width 7.5 mm SOT163-1 4. Marking Table 2. Marking codes Type number T/1 Marking code T Objective data sheet Rev..1 29 August 28 2 of 68
T D T A 5. Block diagram INT CLKOUT 7 32.768 khz OSCI OSCO TCXO DIVIDER AND TIMER 17 Control_1 Control_2 1 Control_3 2 Seconds 3 BBS V BAT V SS 18 2 19 8 BATTERY BACK UP SWITCH-OVER CIRCUITRY OSCILLATOR MONITOR internal power supply RESET TEMP 1 Hz LOGIC CONTROL Minutes 4 Hours 5 Days 6 Weekdays 7 Months 8 Years 9 Second_alarm A Minute_alarm B SDA/CE SDO SDI SCL 4 3 2 1 SERIAL BUS INTERFACE ADDRESS REGISTER Hour_alarm C Day_alarm D Weekday_alarm E CLKOUT_ctl F Watchdg_ctl 1 Watchdg_val 11 IFS 5 INTERFACE SELECTORS Timestp_ctl Sec_timestp 12 13 TS SCL SDA/CE 6 I 2 C BUS INTERFACE Min_timestp Hour_timestp Day_timestp Mon_timestp Year_timestp 14 15 16 17 18 TEMP TEMPERATURE SENSOR Crystal_aging Internal_reg Internal_reg 19 1A 1B pcf2129-15 Fig 1. Block diagram of Objective data sheet Rev..1 29 August 28 3 of 68
T D T A 6. Pinning information 6.1 Pinning SCL 1 2 SDI 2 19 V BAT SDO 3 18 BBS SDA/CE 4 17 INT IFS TS 5 6 16 15 n.c. n.c. CLKOUT 7 14 n.c. V SS 8 13 n.c. n.c. 9 12 n.c. n.c. 1 11 n.c. pcf2129-1 Top view. For mechanical details, see Figure 49. Fig 2. Pin configuration SO2 Table 3. Pin description Symbol Pin Description Symbol Pin Description SCL 1 combined serial clock input for both I 2 C-bus and SPI-bus; may float when CE inactive SDI 2 serial data input for SPI-bus; may float when CE inactive 2 positive supply voltage V BAT 19 battery supply voltage (backup) SDO 3 serial data output for SPI-bus, push-pull BBS 18 output voltage (battery backed) SDA/CE 4 combined serial data input/output for the I 2 C interface and chip enable input (active LOW) for the SPI-bus IFS 5 interface selector input connect to ground to select the SPI-bus connect to BBS (pin 18) to select the I 2 C interface TS 6 timestamp input (active LOW) with 2 kω internal pull-up resistor INT 17 interrupt output (open-drain; active LOW) n.c. 16 do not connect; do not use as feed through n.c. 15 do not connect; do not use as feed through CLKOUT 7 clock output (open drain) n.c. 14 do not connect; do not use as feed through V SS 8 ground n.c. 13 do not connect; do not use as feed through n.c. 9 not connected; do not use as feed through n.c. 12 not connected; do not use as feed through n.c. 1 not connected; do not use as feed through n.c. 11 not connected; do not use as feed through Objective data sheet Rev..1 29 August 28 4 of 68
T D T A 7. Device protection diagram SCL SDI V BAT BBS SDO INT SDA/CE IFS TS CLKOUT V SS pcf2129-2 Fig 3. Device diode protection diagram 8. Functional description The is a real time clock and calendar (RTC) with an on-chip temperature compensated crystal oscillator (TCXO) and a 32.768 khz quartz crystal integrated into the same package. The address and data are transferred by a selectable 1 MHz fast mode plus I 2 C interface or a 3 line SPI-bus with separate data input and output (see Section 8.18). The maximum speed is 6.5 Mbit/s. The contains 28 8-bit registers, that are used for many different functions, such as clock, alarm, watchdog, timestamp etc. (see Section 8.1). The has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply and automatically switches to the backup battery when a power failure condition is detected (see Section 8.5). Accurate timekeeping is maintained even when the main power supply is interrupted. A battery low detection circuit monitors the status of the battery (see Section 8.7). When the battery voltage goes below a threshold value, a flag is set to indicate that the battery must be replaced. This ensures the integrity of the data during periods of battery backup. 8.1 Register overview The contains 28 8-bit registers (see Table 4 and Figure 4) with an auto-incrementing address register: the built-in address register will increment automatically after each read or write data byte up to the register 1Bh. After register 1Bh the auto-incrementing will wrap around to address h. Objective data sheet Rev..1 29 August 28 5 of 68
T D T A The first three registers (memory address h, 1h and 2h) are used as control registers (see Section 8.2). The memory addresses 3h through to 9h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock can operate in the 24-hour mode or in 12-hour mode with an AM/PM indication (see Section 8.1). Addresses Ah through Eh define the alarm function. It can be selected to generate an interrupt when the alarm occurs (see Section 8.11). The register Fh defines the temperature measurement period and the clock out mode. It can be selected to generate the temperature measurement from every 4 minutes (default) down to every 3 seconds (see Section 8.3.1). CLKOUT frequencies of 32.768 khz (default) down to 1 Hz for use as a system clock, a micro-controller clock etc. can be chosen (see Section 8.15). Address registers 1h and 11h are used for the watchdog timer functions. The watchdog timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours. An interrupt will be generated when the watchdog times out. Address registers 12h to 18h are used for the 1 16 second, second, minute, hour, day, month and year of the timestamp function. When the trigger-event happens the actual time is saved in the timestamp registers (see Section 8.13). Address register 19h is used for the correction of the crystal aging effect (see Section 8.3.2). Address registers 1Ah and 1Bh are for internal use only. The registers Seconds, Minutes, Hours, Days, Weekdays, Months and Years are all coded in BCD (binary coded decimal) format to simplify application use. Other registers are either bit-wise or standard binary. address register h 1h 2h 3h.. 19h 1Ah 1Bh auto-increment wrap around Fig 4. Handling address registers When one of the RTC registers is read the content of all counters is frozen. This prevents a faulty reading of the clock/calendar during a carry condition. Objective data sheet Rev..1 29 August 28 6 of 68
T D T A Table 4. Register overview Bit positions labelled as - are not implemented and will return a when read. Bit positions labelled with must be written with logic. Address Register name Bit 7 6 5 4 3 2 1 h Control_1 EXT_TEST STOP TSF1 POR_OVRD 12_24 MI SI 1h Control_2 MSF WDTF TSF2 AF TSIE AIE 2h Control_3 PWRMNG BTSE BF BLF BIE BLIE 3h Seconds OSF SECONDS ( to 59) 4h Minutes - MINUTES ( to 59) 5h Hours - - AMPM HOURS (1 to 12) in 12 h mode HOURS ( to 23) in 24 h mode 6h Days - - DAYS (1 to 31) 7h Weekdays - - - - - WEEKDAYS 8h Months - - - MONTHS (1 to 12) 9h Years YEARS ( to 99) Ah Second_alarm AEN_S SECOND_ALARM ( to 59) Bh Minute_alarm AEN_M MINUTE_ALARM ( to 59) Ch Hour_alarm AEN_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM ( to 23) in 24 h mode Dh Day_alarm AEN_D - DAY_ALARM (1 to 31) Eh Weekday_alarm AEN_W - - - - WEEKDAY_ALARM Fh CLKOUT_ctl TCR - - - COF 1h Watchdg_ctl WDE TI_TP - - - TF 11h Watchdg_val WATCHDG_VAL 12h Timestp_ctl TSM TSOFF - 1_O_16_SECOND 13h Sec_timestp - SECOND_TIMESTP 14h Min_timestp - MINUTE_TIMESTP 15h Hour_timestp - - AMPM HOUR_TIMESTP (1 to 12) in 12 h mode HOURS ( to 23) in 24 h mode 16h Day_timestp - - DAY_TIMESTP (1 to 31) 17h Mon_timestp - - - MONTH_TIMESTP 18h Year_timestp YEAR_TIMESTP 19h Crystal_aging - - - - AO 1Ah Internal_reg - - - - - - - - 1Bh Internal_reg - - - - - - - - Table 5. Overview of controlbits in the register Control bit Name Default value Reference Register Control_1 EXT_TEST external clock test mode Section 8.2.1 and Section 8.16 STOP stop bit Section 8.2.1 and Section 8.17 TSF1 timestamp flag 1 Section 8.2.1 and Section 8.13 Objective data sheet Rev..1 29 August 28 7 of 68
T D Table 5. Overview of controlbits in the register continued Control bit Name Default value Reference T A POR_OVRD power-on reset (POR) override 1 Section 8.2.1 and Section 8.9.2 12_24 12/24 hour mode Section 8.2.1 and Section 8.1 MI minute interrupt Section 8.2.1 and Section 8.14.1 SI second interrupt Section 8.2.1 and Section 8.14.1 Register Control_2 MSF minute/second flag Section 8.2.2 and Section 8.12.3 WDTF watchdog timer flag Section 8.2.2 and Section 8.12 TSF2 timestamp flag 2 Section 8.2.2 and Section 8.13 AF alarm flag Section 8.2.2 and Section 8.11.1 TSIE timestamp interrupt enable Section 8.2.2 and Section 8.14.4 AIE alarm interrupts enable Section 8.2.2 and Section 8.14.3 Register Control_3 PWRMNG[2:] power management Section 8.2.3 and Section 8.4 BTSE battery timestamp enable Section 8.2.3 and Section 8.13.2 BF battery switch flag Section 8.2.3 and Section 8.5 BLF battery low flag (read only) Section 8.2.3 and Section 8.7 BIE battery switch interrupt enable Section 8.2.3 and Section 8.14.5 BLIE battery low interrupt enable Section 8.2.3 and Section 8.14.6 Register Seconds OSF oscillator stop flag 1 Section 8.8 Registers Second_alarm, Minute_alarm, Hour_alarm, Day_alarm, Weekday_alarm AENx alarm enable active low 1 Section 8.11 Register CLKOUT_ctl TCR[1:] temperature conversion rate Section 8.3.1 COF[2:] clock output function Section 8.15 Register Watchdg_ctl WDE watchdog enable Section 8.12 TI_TP timer interrupt/timer pulse TF[1:] timer frequency 11 Register Timestp_ctl TSM timestamp mode Section 8.13 TSOFF timestamp off Register Crystal_aging AO[3:] aging offset bits 1 Section 8.3.2 Objective data sheet Rev..1 29 August 28 8 of 68
T D 8.2 Control registers T A has 28 8-bit registers. The first 3 registers with the addresses h, 1h and 2h are used as control registers. 8.2.1 Register Control_1 Table 6. 8.2.2 Register Control_2 Register Control_1 (h) bits description Bit Symbol Value Description Reference 7 EXT_TEST normal mode Section 8.16 6 - unused 1 external clock test mode 5 STOP RTC source clock runs Section 8.17 1 RTC divider chain flip-flops are asynchronously set to logic ; the RTC clock is stopped (CLKOUT at 32.768 khz, 16.384 khz or 8.192 khz is still available) 4 TSF1 no timestamp interrupt is generated Section 8.13 1 flag set when TS input is driven to an intermediate level between the power supply and ground; flag must be cleared to clear interrupt 3 POR_OVRD power-on reset override facility is disabled; set to logic for normal operation 1 power-on reset override is enabled Section 8.9.2 2 12_24 24 hour mode is selected Table 17 1 12 hour mode is selected 1 MI minute interrupt is disabled Section 8.14.1 1 minute interrupt is enabled SI second interrupt is disabled Table 7. 1 second interrupt is enabled Register Control_2 (1h) bits description Bit Symbol Value Description Reference 7 MSF no minute or second interrupt generated Section 8.12 1 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 6 WDTF no watchdog timer interrupt or reset generated Section 8.12 1 flag set when watchdog timer interrupt or reset generated; the flag cannot be cleared by programming (read-only) 5 TSF2 no timestamp interrupt is generated; flag set when TS input is driven to ground; flag must be cleared to clear interrupt 1 flag set when TS input is LOW; flag must be cleared to clear interrupt Section 8.13 Objective data sheet Rev..1 29 August 28 9 of 68
T D Table 7. Register Control_2 (1h) bits description continued T A Bit Symbol Value Description Reference 4 AF no alarm interrupt generated Section 8.11.1 1 flag set when alarm triggered; flag must be cleared to clear interrupt 3 - unused; write with logic - 2 TSIE no interrupt generated from timestamp flag Section 8.14.4 1 interrupt generated from timestamp flag set 1 AIE no interrupt generated from the alarm flag Section 8.14.3 1 interrupt generated when alarm flag set - unused; write with logic - 8.2.3 Register Control_3 Table 8. [1] Values see Table 11. Register Control_3 (2h) bits description Bit Symbol Value Description Reference 7 to 5 PWRMNG [1] this bits control the battery switch-over, the battery low detection and the extra power fail detection functions 4 BTSE no timestamp when the battery switch-over occurs (default) 1 time-stamped when the battery switch-over occurs Section 8.4 Section 8.13.2 3 BF no battery switch-over interrupt generated Section 8.5 1 flag set when battery switch-over occurs, flag must be cleared to clear interrupt 2 BLF battery status OK; no battery low interrupt generated 1 battery status low; flag cannot be cleared using the interface Section 8.7 1 BIE no interrupt generated from the battery flag (BF) Section 8.14.5 1 interrupt generated when BF is set BLIE no interrupt generated from battery low flag (BLF) 1 interrupt generated when BLF is set Section 8.14.6 Objective data sheet Rev..1 29 August 28 1 of 68
T D 8.3 Temperature compensated crystal oscillator T A Tuning fork quartz crystals have a square law temperature dependency. In the the frequency drift caused by temperature dependency is corrected by adjusting the load capacitance of the crystal oscillator. The load capacitance is changed by switching between two load capacitance values using a programmable duty cycle. This results in a linear relationship between the frequency drift and the duty cycle of the modulation frequency. Every chip is calibrated in order to produce, at the measured temperature, the correct duty cycle which compensates for the frequency shift. The resulting accuracy is shown in Figure 5. Df/f typical limits ± 5 ppm -4-2 25 6 7 85 temperature ( C) ± 3 ppm 1aag74 Fig 5. TCXO frequency accuracy 8.3.1 Temperature measurement The has a temperature sensor circuit used to perform the temperature compensation of the frequency. The temperature is measured immediately after power-up and then periodically with a period set by the temperature conversion rate bits TCR[1:] in the register Fh. Table 9. TCR[1:] Bit 1 Bit Temperature measurement period 4 min (default) 1 2 min 1 1 min 1 1 3 seconds 8.3.2 Crystal aging correction Temperature measurement period The has an aging offset register Crystal_aging (19h) to correct the crystal aging effects. The accuracy of the frequency of a quartz crystal depends on the aging. Crystal suppliers usually specify the first year aging, typically ±3 ppm. The aging offset register adds an offset, positive or negative, in the temperature compensation circuits which allows to correct the aging effect. The change in ppm per LSB is different at different temperatures. At 25 C, the aging offset bits AO[3:] allow a frequency correction of typically 1 ppm per LSB, from 7 ppm to +8 ppm. Objective data sheet Rev..1 29 August 28 11 of 68
T D Table 1. Frequency correction at 25 C, typical AO[3:] [1] ppm +8 1 +7 2 +6 3 +5 4 +4 5 +3 6 +2 7 +1 8 (default) 9 1 1 2 11 3 12 4 13 5 14 6 15 7 T A [1] Values shown in decimal. 8.4 Power management functions The has three power supply pins: - the main power supply input pin V BAT - the battery backup input pin BBS - a pin for a battery backed output voltage equal to the internal power supply The has two power management functions implemented: Battery switch-over function Battery low detection function Objective data sheet Rev..1 29 August 28 12 of 68
T D T A The power management functions are controlled by the control bits PWRMNG[2:] in register Control_3 (2h): Table 11. PWRMNG[2:] Bit 2 Bit 1 Bit [1] Default condition. Power management functions control bits Function [1] battery switch-over function is enabled in standard mode, [2] When the battery switch-over function is disabled, the works only with the power supply ; V BAT must be put to ground and the battery low detection function is disabled. 8.5 Battery switch-over function battery low detection function is enabled, extra power fail detection function is enabled 1 battery switch-over function is enabled in standard mode, battery low detection function is disabled, extra power fail detection function is disabled 1 1 battery switch-over function is enabled in direct switching mode, battery low detection function is enabled, extra power fail detection function is enabled 1 1 battery switch-over function is enabled in direct switching mode, battery low detection function is disabled, extra power fail detection function is disabled 1 1 1 [2] battery switch-over function is disabled - only one power supply ( ), battery low detection function is disabled, extra power fail detection function is disabled The has a backup battery switch-over circuit which monitors the main power supply and automatically switches to the backup battery when a power failure condition is detected. One of two operation modes can be selected: Standard mode: the power failure condition happens when: < V BAT AND < V th(sw)bat (battery switch threshold voltage). Direct switching mode: the power failure condition happens when < V BAT. Direct switching from to V BAT without requiring to drop below V th(sw)bat. When a power failure condition occurs and the power supply switches to the battery the following sequence occurs: 1. The battery switch flag, bit BF (register Control_3) is set to logic 1. 2. An interrupt is generated if the control bit, BIE (register Control_3), is enabled (see Section 8.14.5). 3. If the control bit BTSE (register Control_3), is set to logic 1, the timestamp registers store the time and date when the battery switch occurred (see Section 8.13.2). 4. The battery switch flag, bit BF is cleared via an interface: the flag must be cleared (bit BF = ) to clear the interrupt. Objective data sheet Rev..1 29 August 28 13 of 68
T D The interface is disabled in battery backup operation: T A Interface inputs are not recognized, preventing extraneous data being written to the device Interface outputs are high impedance 8.5.1 Standard mode If > V BAT OR > V th(sw)bat then the internal power supply is. If < V BAT AND < V th(sw)bat then the internal power supply is V BAT. V th(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. Backup battery operation V BBS V BBS V BAT Internal power supply (= VBBS) V BAT V th(sw)bat (= 2.5 V) V th(sw)bat (= 2.5 V) (= V) clear via interface BF INT BF INT V BAT V BBS V th(sw)bat mgw9_power_failure_2 Fig 6. Battery switch-over behavior in standard mode and with bit BIE set to logic 1 (enabled) Objective data sheet Rev..1 29 August 28 14 of 68
T D 8.5.2 Direct switching mode If > V BAT the internal power supply is. If < V BAT then the internal power supply is V BAT. T A The direct switching mode is useful in systems where is higher than V BAT at all times. The direct switching mode is not recommended if the and V BAT values are similar (e.g. = 3.3 V, V BAT 3. V). When the monitoring of and V th(sw)bat is not performed, the power consumption is reduced compared to the standard mode, see Figure 7: Backup battery operation V BBS V BBS V BAT Internal power supply (= VBBS) V BAT V th(sw)bat (= 2.5 V) V th(sw)bat (= 2.5 V) (= V) clear via interface BF INT BF INT V BAT V BBS V th(sw)bat mgw9_power_failure_3 Fig 7. Battery switch-over behavior in direct switching mode and with bit BIE set to logic 1 (enabled) 8.5.3 Battery switch-over disabled: only one power supply ( ) When the battery switch-over function is disabled: The power supply is applied on the pin The V BAT pin must be connected to ground The internal power supply, available at the output pin BBS is equal to The battery flag (bit BF) is always logic Objective data sheet Rev..1 29 August 28 15 of 68
T D T A 8.5.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 8. comparators logic switches V CC _ON V th(sw)bat LOGIC _ON V th(sw)bat V CC V BAT _ON V BBS (internal power supply) 1aag61_3 Fig 8. Battery switch-over circuit, simplified block diagram The internal power supply, available at the output pin BBS is equal to or V BAT. It has to be assured that there are decoupling capacitors on the pins, V BAT and BBS. 8.6 BBS output pin The has an output pin, BBS. The V BBS voltage is equal to the internal power supply and depends on the selected battery switch-over function mode: Table 12. Output pin BBS Battery switch-over function mode Conditions V BBS standard > V BAT or > V th(sw)bat < V BAT and < V th(sw)bat V BAT direct switching > V BAT disabled < V BAT only available, V BAT must be put to ground V BAT The output pin BBS can be used as a supply for battery backup devices such as SRAM (see Figure 47). Objective data sheet Rev..1 29 August 28 16 of 68
T D T A Figure 9 shows the driving capability. V BBS Driving Capability -1 (VBBS - VDD) [mv] -2-3 -4-5 -6-7 VDD = 3 V VDD = 2 V -8 1 2 3 4 5 6 7 8 I BBS [ma] Fig 9. Driving capability of V BBS : (V BBS ) vs. output load current I BBS 8.7 Battery low detection function The has a battery low detection circuit which monitors the status of the battery V BAT. When V BAT drops below the threshold value V th(bat)low (typically 2.5 V) a flag (bit BLF) is set to indicate that the battery is low and that it must be replaced. A low battery will not ensure data integrity during periods of backup battery operation. Monitoring of the battery voltage also occurs during battery operation. When V BAT drops below the threshold value V th(bat)low, the following sequence occurs (see Figure 1): 1. The battery low flag, bit BLF (register Control_3), is set to logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 8.14.6). 3. The bit BLF remains set to logic 1 until the replacement battery is installed. Bit BLF cannot be cleared using an interface. Objective data sheet Rev..1 29 August 28 17 of 68
T D T A = V BBS Internal power supply (= VBBS) = V BBS V BAT V BAT V th(bat)low (= 2.5 V) V th(bat)low (= 2.5 V) V BAT BLF INT BLF INT V BAT V BBS V th(bat)low mgw9_power_failure_9 Fig 1. Battery low detection behavior with bit BLIE set to logic 1 (enabled) 8.8 Oscillator stop detection function The has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, the reset occurs and the oscillator stop flag (bit OSF) is set to logic 1. The oscillator is not running and bit OSF is set to logic 1 under the following conditions: Power-up: the oscillator is not running, the chip is in reset (bit OSF = 1). When the oscillator starts running and is stable, the chip exits from reset and the flag OSF is cleared (bit OSF = ) via the interface (see Section 8.9.1). Power supply failure: when the power supply of the chip ( or V BAT ) drops below a certain value, typically 1. V, the oscillator stops running and reset occurs. When the power supply returns to normal, the oscillator starts running again, the chip exits from reset and bit OSF = 1. (See Figure 11.) Objective data sheet Rev..1 29 August 28 18 of 68
T D T A V BBS V BAT V BBS V th(sw)bat (= 2.5 V) V LOW (= 1.2V) V BBS Battery discharge Internal power supply V BBS V BAT V SS V SS 1 OSF Theoretical state of the signals since there is no power pcf2129_power_failure V BAT V BBS V th(sw)bat V LOW V SS Fig 11. Power failure event due to battery discharge: reset occurs and OSF is set to logic 1 The oscillator stop flag (bit OSF), set to logic 1, indicates that the oscillation has stopped and the chip reset has occurred since the flag was last cleared (OSF = ). In this case the integrity of the clock information is not guaranteed. The OSF flag is cleared using the interface. 8.9 Reset function The has the power-on reset (POR) and power-on reset override (POR_OVRD) functions implemented. 8.9.1 Power-on-reset The power-on reset is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-up and stable crystal resonance (see Figure 12). This time may be in the range of 2 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (bit OSF = 1). Objective data sheet Rev..1 29 August 28 19 of 68
T D T A chip in reset chip not in reset oscillation internal reset t 1aaf897 Fig 12. Power on reset The SPI-bus is initialized whenever the chip enable line pin CE is inactive. Table 13. Register reset value Bits labeled as - are not implemented. Bits labeled as X are undefined at power-up and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 h Control_1-1 1h Control_2 2h Control_3 3h Seconds 1 X X X X X X X 4h Minutes - X X X X X X X 5h Hours - - X X X X X X 6h Days - - X X X X X X 7h Weekdays - - - - - X X X 8h Months - - - X X X X X 9h Years X X X X X X X X Ah Second_alarm 1 X X X X X X X Bh Minute_alarm 1 X X X X X X X Ch Hour_alarm 1 - X X X X X X Dh Day_alarm 1 - X X X X X X Eh Weekday_alarm 1 - - - - X X X Fh CLKOUT_ctl - - - 1h Watchdg_ctl - - - 1 1 11h Watchdg_val X X X X X X X X 12h Timestp_ctl - X X X X X 13h Sec_timestp - X X X X X X X 14h Min_timestp - X X X X X X X 15h Hour_timestp - - X X X X X X 16h Day_timestp - - X X X X X X 17h Mon_timestp - - - X X X X X 18h Year_timestp X X X X X X X X Objective data sheet Rev..1 29 August 28 2 of 68
T D T A Table 13. Register reset value continued Bits labeled as - are not implemented. Bits labeled as X are undefined at power-up and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 19h Crystal_aging - - - - 1 1Ah Internal_reg X X X X X X X 1Bh Internal_reg After power-on reset, the following mode is entered: 32.768 khz CLKOUT active Power on reset override available to be set 24 hour mode is selected Battery switch-over is enabled Battery low detection is enabled 8.9.2 Power-On Reset override The power on reset (POR) duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. OSCILLATOR osc stopped = stopped, 1 = running reset SCL SDA/CE reset override CLEAR = override inactive 1 = override active POR_OVRD = clear override mode 1 = override possible 1aaf898_2 Fig 13. Power-on reset system The setting of this mode requires that the bit POR_OVRD bit in register Control_1 (h) be set to logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 14. All timings shown are required minimums. Objective data sheet Rev..1 29 August 28 21 of 68
T D T A power up 8 ms SDA / CE minimum 5 ns minimum 2 ns SCL Reset override mgr1_3 Fig 14. POR override sequence, valid for both I 2 C-bus and SPI-bus Once the override mode is entered, the device immediately stops being reset and set-up operation can commence i.e. entry into the external clock test mode via the I 2 C-bus or the SPI-bus access. The override mode is cleared by writing a logic to bit POR_OVRD. POR_OVRD must be set to logic 1 before a re-entry into the override mode is possible. Setting bit POR_OVRD to logic during normal operation has no effect except to prevent accidental entry into the POR override mode. 8.1 Time and date function The majority of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the register Minutes: Table 14. Minutes value in decimal BCD example Upper-digit Digit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 3 2 2 2 1 2 2 3 2 2 2 1 2 1 1 2 1 : 9 1 1 1 1 : 58 1 1 1 59 1 1 1 1 Objective data sheet Rev..1 29 August 28 22 of 68
T D Table 15. Register Seconds (3h) bits description Bit Symbol Value Description 7 OSF clock integrity is guaranteed T A 1 clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to SECONDS to 59 [1] this register holds the current seconds coded in BCD format [1] Values shown in decimal. Table 16. Register Minutes (4h) bits description Bit Symbol Value Description 7 - - unused 6 to MINUTES to 59 [1] [1] Values shown in decimal. this register holds the current minutes coded in BCD format Table 17. Register Hours (5h) bits description Bit Symbol Value Description 7, 6 - - unused 12 hour mode [1] 5 AMPM indicates AM 4 to HOURS to 12 [2] 24 hour mode [1] 5 to HOURS to 23 [2] [1] Hour mode is set by the bit 12_24 in register Control_1. [2] Values shown in decimal. 1 indicates PM this register holds the current hours coded in BCD format for 12 hour mode this register holds the current hours coded in BCD format for 24 hour mode Table 18. Register Days (6h) bits description Bit Symbol Value Description 7, 6 - - unused 5 to DAYS [1] 1 to 31 [2] [1] The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year. [2] Values shown in decimal. this register holds the current day coded in BCD format Objective data sheet Rev..1 29 August 28 23 of 68
T D Table 19. Register Weekdays (7h) bits description Bit Symbol Value Description 7 to 3 - - unused [1] These bits may be re-assigned by the user. [2] Values shown in decimal. T A 2 to WEEKDAYS [1] to 6 [2] this register holds the current weekday value, see Table 2 Although the association of the weekdays counter to the actual weekday is arbitrary, the will assume Sunday is and Monday is 1 for the purposes of determining the increment for calendar weeks. Table 2. Weekday assignments [1] Day Upper-digit Digit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Sunday X X X X X Monday X X X X X 1 Tuesday X X X X X 1 Wednesday X X X X X 1 1 Thursday X X X X X 1 Friday X X X X X 1 1 Saturday X X X X X 1 1 [1] Bits marked with X can be or 1; don t care. Table 21. Register Months (8h) bits description Bit Symbol Value Description 7 to 5 - - unused 4 to MONTH 1 to 12 [1] this register holds the current month coded in BCD format, see Table 22 [1] Values shown in decimal. Table 22. Month assignments [1] Month Upper-digit Digit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit January X X X 1 February X X X 1 March X X X 1 1 April X X X 1 May X X X 1 1 June X X X 1 1 July X X X 1 1 1 August X X X 1 September X X X 1 1 Objective data sheet Rev..1 29 August 28 24 of 68
T D Table 22. Month assignments [1] Month Upper-digit Digit T A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit October X X X 1 November X X X 1 1 December X X X 1 1 [1] Bits marked with X can be or 1; don t care. Table 23. Register Years (9h) bits description Bit Symbol Value Description 7 to YEARS to 99 [1] this register holds the current year coded in BCD format [1] Values shown in decimal. Figure 15 describes the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 1aaf91 Fig 15. Data flow for the time function 8.11 Alarm function When one or more of these registers are loaded with a valid second, minute, hour, day or weekday and its corresponding alarm enable not bit (AENx) is logic, then that information is compared with the current second, minute, hour, day and weekday (see Figure 16). Objective data sheet Rev..1 29 August 28 25 of 68
T D Table 24. Register Second_alarm (Ah) bits description Bit Symbol Value Description 7 AEN_S second alarm is enabled 6 to SECOND_ALARM to 59 [1] 1 second alarm is disabled T A this register holds the second alarm information coded in BCD format [1] Values shown in decimal. Table 25. Register Minute_alarm (Bh) bits description Bit Symbol Value Description 7 AEN_M minute alarm is enabled 6 to MINUTE_ALARM to 59 [1] [1] Values shown in decimal. 1 minute alarm is disabled this register holds the minute alarm information coded in BCD format Table 26. Register Hour_alarm (Ch) bits description Bit Symbol Value Description 7 AEN_H hour alarm is enabled [1] Values shown in decimal. 1 hour alarm is disabled 6 - - unused 24 hour mode 5 to HOUR_ALARM to 23 [1] 12 hour mode this register holds the hour alarm information coded in BCD format when in 24 hour mode. 5 AMPM to 1 this register holds the hour alarm information coded in 4 to HOUR_ALARM 1 to 12 [1] BCD format when in 12 hour mode Table 27. Register Day_alarm (Dh) bits description Bit Symbol Value Description 7 AEN_D day alarm is enabled [1] Values shown in decimal. 1 day alarm is disabled 6 - - unused 5 to DAY_ALARM 1 to 31 [1] this register holds the day alarm information coded in BCD format Objective data sheet Rev..1 29 August 28 26 of 68
T D T A Table 28. Register Weekday_alarm (Eh) bits description Bit Symbol Value Description 7 AEN_W weekday alarm is enabled 1 weekday alarm is disabled 6 to 3 - - unused 2 to WEEKDAY_ALARM to 6 [1] this register holds the weekday alarm information [1] Values shown in decimal. check now signal MINUTE ALARM MINUTE TIME = MINUTE AEN example MINUTE AEN = 1 1 HOUR AEN HOUR ALARM = HOUR TIME DAY AEN set alarm flag, AF (1) DAY ALARM = DAY TIME WEEKDAY AEN WEEKDAY ALARM WEEKDAY TIME = 1aaf92 Generation of interrupts from the alarm function is described under the interrupt section, Section 8.14.3. 8.11.1 Alarm flag (1) Only when all enabled alarm settings are matching. Fig 16. Alarm function block diagram When all enabled comparisons first match, the alarm flag, bit AF, is set. Bit AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AENx at logic 1 are ignored. Objective data sheet Rev..1 29 August 28 27 of 68
T D T A minutes counter 44 45 46 minute alarm 45 AF INT when AIE = 1 1aaf93 Example where only the minute alarm is used and no other interrupts are enabled. Fig 17. AF timing Figure 8 shows an example for clearing bit AF but leaving bit MSF and bit TF unaffected. Clearing the flags is made by a write command, therefore bits 6, 2, 1 and must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. To prevent the timer flags being overwritten while clearing bit AF, a logic AND is performed during a write access. Writing a logic 1 will cause the flag to maintain it s value, whilst writing a logic will cause the flag to be reset. The following tables show what instruction must be sent dot clear the appropriate flag. Table 29. Register Flag location in register Control_2 Bit 7 6 5 4 3 2 1 Control_2 MSF - TSF AF - - - Table 3. Example to clear only AF (bit 4) in register Control_2 Register Bit 7 6 5 4 3 2 1 Control_2 1-1 - - - 8.12 Timer functions The has a watchdog timer, used to detect when the micro-controller is out of control, and two predefinded timers, used to generate an interrupt once per second or once per minute. To control the timer functions and output, the registers Control_2 (1h), Watchdg_ctl (1h) and Watchdg_val (11h) are used (see Table 31 and Table 32). Table 31. Register Watchdg_ctl (1h) bits description Bit Symbol Value Description 7 WDE watchdog timer disabled (default) 1 watchdog timer enabled; the interrupt pin INT is activated when timed-out 6 - unused; must be written with logic Objective data sheet Rev..1 29 August 28 28 of 68
T D Table 31. Register Watchdg_ctl (1h) bits description continued Bit Symbol Value Description T A 5 TI_TP the interrupt pin INT is configured to generate a permanent active signal when the flag, bit MSF is set 4 to 2 - unused 1 the interrupt pin INT is configured to generate a pulsed signal when the flag, bit MSF is set (see Figure 19) 1 to TF[1:] 496 Hz watchdog timer source clock 1 64 Hz watchdog timer source clock 1 1 Hz watchdog timer source clock 1 1 1 6 Hz watchdog timer source clock Table 32. 8.12.1 Watchdog timer function [1] Bits marked with X can be or 1; don t care. Register Watchdg_val (11h) bits description Bit Symbol Value Description 7 to WATCHDG_VAL to FF Table 33. Programmable watchdog timer [1] WDE TF[1:] Watchdog timer source clock frequency timer = n The has a watchdog timer with four selectable source clocks, and with interrupt capability, used to detect when the micro-controller is out of control. The watchdog timer function is enabled by setting the control bit WDE (register Watchdg_ctl) to logic 1. When the watchdog timer function is enabled (WDE = 1), the 8 bit timer in register Watchdg_val (11h) determines the watchdog timer value (n =...255). The two bits TF[1:] in register Watchdg_ctl (1h) determine one of the four source clock frequencies for the watchdog timer: 4.96 khz, 64 Hz, 1 Hz or 1 6 Hz. Units timer period Minimum watchdog timer duration (n = 1) Units n = -------------------------------------------------------------- Source ClockFrequency Maximum watchdog timer duration (n = 255) 1 496 Hz 244 µs 62.256 ms 1 64 Hz 15.625 ms 3.984 s 1 1 Hz 1 s 255 s 1 1 1 6 Hz 6 s 153 s Units The watchdog timer counts down from the software programmed 8 bit binary value n in register Watchdg_val (11h). When the counter reaches 1 the watchdog timer flag, bit WDTF, is set to logic 1 and an interrupt is generated (see Figure 18). Objective data sheet Rev..1 29 August 28 29 of 68
T D T A MCU watchdog timer value n = 1 n WDTF INT 1aag62 Fig 18. Watchdog with interrupt capability The counter does not automatically reload. When WDE is set to logic and the micro-controller unit (MCU) loads a watchdog timer value n, the flag WDTF is reset, INT is cleared and the watchdog timer starts again. Loading the counter with will reset the flag WDTF, clear the interrupt INT and stop the watchdog timer. Bit WDTF is read only. A read of the register Control_2 (1h) will automatically reset the flag WDTF. 8.12.2 Predefined timers: second and minute interrupt The has two predefined timers which are used to generate an interrupt either once per second or once per minute. The timers can be enabled independently of each other by the MI and SI bits (register Control_1). When either the seconds or the minutes counter increments according to the currently enabled interrupt, the minute/second flag (bit MSF, register Control_2) is set to logic 1. The interrupt can be generated as a pulsed signal every second or minute or as a permanently active signal which follows the condition of the MSF flag, according to the programming of the TI_IP bit (register Watchdg_ctl). The pulse generator for the minute or second interrupt operates from an internal 64 Hz clock. It is independent of the watchdog timer (see Section 8.14.1). 8.12.3 Timer flags When the watchdog timer counter reaches 1, the watchdog timer flag, bit WDTF is set to logic 1. Similarly when a minute or second interrupt occurs the minute/second flag, bit MSF, is set to logic 1. The watchdog timer flag, WDTF, is read only. Writing a logic or logic 1 on bit WDTF has no effect. The minute/second flag, MSF, can be directly cleared using the interface. To prevent one flag being overwritten while clearing another a logic AND is performed during the write access. Writing a logic 1 causes the flag to maintain it s value whilst writing a logic causes the flag to reset. Objective data sheet Rev..1 29 August 28 3 of 68
T D T A The following tables show what instruction must be sent to clear the appropriate flag. Table 34. Flag location in Control_2 Register Bit 7 6 5 4 3 2 1 Control 2 MSF WDTF TSF AF - - - Table 35. Example to clear only MSF (bit 7) Register Bit Clearing the alarm flag (bit AF) operates in exactly the same way, but is described in section Section 8.11.1. 8.13 Timestamp function 7 6 5 4 3 2 1 Control 2 X 1 1 - - - The has an active LOW timestamp input pin TS, supplied with an on-chip pull-up resistor (2 kω) to the power supply of the device. It also has a timestamp detection circuit which can detect two different events: TS input on the pin is driven to an intermediate level between the power supply and ground TS input on the pin is driven to ground When the TS input pin is driven to an intermediate level between the power supply and ground the following sequence occurs: 1. The current date and time are stored in the timestamp registers. 2. The timestamp flag, bit TSF1, is set. 3. It can be selected to generate an interrupt on the INT pin if the TSIE bit is active. The TSF1 flag can be cleared by using the interface; clearing the flag will clear the interrupt. When the TS input pin is driven to ground the following sequence occurs: 1. The current date and time are stored in the timestamp registers. 2. The timestamp flags TSF1 and TSF2 are set. 3. It can be selected to generate an interrupt on the INT pin if the TSIE bit is active. The TSF1 and TSF2 flags can be cleared by using the interface; clearing both flags will clear the interrupt. The timestamp function has two different modes selected by the control bit TSM (time stamp mode): If TSM = (default) in subsequent trigger events without clearing the timestamp flags, the last event is stored If TSM = 1 in subsequent trigger events without clearing the timestamp flags, the first event is stored Objective data sheet Rev..1 29 August 28 31 of 68
T D T A The timestamp function also depends on the control bit BTSE (battery switch timestamp enable) in register Control_3 (2h), see Section 8.13.2. Table 36. Register Timestp_ctl (12h) bits description Bit Symbol Value Description 7 TSM in subsequent events without clearing the timestamp flags, the last event is stored (default) 1 in subsequent events without clearing the timestamp flags, the first event is stored 6 TSOFF timestamp function active (default) 5 - - unused 1 timestamp function disabled 4 to 1_O_16_TIMESTP this register holds the 1 16 second timestamp information coded in BCD format Table 37. Register Sec_timestp (13h) bits description Bit Symbol Value Description 7 - - unused 6 to SECOND_TIMESTP to 59 [1] [1] Values shown in decimal. this register holds the second timestamp information coded in BCD format Table 38. Register Min_timestp (14h) bits description Bit Symbol Value Description 7 - - unused 6 to MINUTE_TIMESTP to 59 [1] [1] Values shown in decimal. this register holds the minute timestamp information coded in BCD format Table 39. Register Hour_timestp (15h) bits description Bit Symbol Value Description 7 to 6 - - unused 24 hour mode 5 to HOUR_TIMESTP to 23 [1] 12 hour mode [1] Values shown in decimal. this register holds the hour timestamp information coded in BCD format when in 24 hour mode 5 AMPM to 1 indicates am (set to ) or pm (set to 1) 4 to HOUR_TIMESTP to 11 [ 1] this register holds the hour timestamp information coded in BCD format when in 12 hour mode Objective data sheet Rev..1 29 August 28 32 of 68
T D Table 4. Register Day_timestp (16h) bits description Bit Symbol Value Description 7 to 6 - - unused 5 to DAY_TIMESTP 1 to 31 [1] [1] Values shown in decimal. T A this register holds the day timestamp information coded in BCD format Table 41. Register Mon_timestp (17h) bits description Bit Symbol Value Description 7 to 5 - - unused 4 to MONTH_TIMESTP 1 to 12 [1] [1] Values shown in decimal. this register holds the month timestamp information coded in BCD format Table 42. [1] Values shown in decimal. See Section 8.14.4 for a description of interrupt generation from the timestamp function. 8.13.1 Timestamp flag Register Year_timestp (18h) bits description Bit Symbol Value Description 7 to YEAR_TIMESTP to this register holds the year timestamp information coded 99 [1] in BCD format When a negative edge on the TS input pin is detected, the timestamp flag, bit TSF1, is set. TSF1 remains set until cleared by the software. Once TSF1 is cleared it will only be set again when a new negative edge on TS is detected. When the TS input is driven to ground the timestamp flag, bit TSF2, is set. TSF2 remains set until cleared by the software. Once TSF2 is cleared it will only be set again when TS is driven to ground once again. 8.13.2 Dependency between Battery switch-over and timestamp The timestamp function depends on the control bit BTSE (battery switch timestamp enable) in register Control_3 (2h): Table 43. Battery switch-over and timestamp BTSE BF Description - default; the battery switch-over does not affect the timestamp registers If a battery switch-over event occurs: 1 the timestamp registers store the time and date when the switch-over occurs; BF is set to logic 1 1 the timestamp registers are not modified; in this condition subsequent battery switch-over events or falling edges on the TS signal are not registered Objective data sheet Rev..1 29 August 28 33 of 68
T D 8.14 Interrupt output, INT T A has an interrupt output INT which is open drain, active LOW. Interrupts may be sourced from different places: Second/minute timer Watchdog timer Alarm Timestamp Battery switch-over Battery low detection SECONDS COUNTER MINUTES COUNTER SI MI MSF: MINUTE SECOND FLAG SET CLEAR to interface: read MSF PULSE GENERATOR 1 1 SI/MI from interface: clear MSF TRIGGER CLEAR TI_TP INT pin WDE = 1 WATCHDOG COUNTER WDTF: WATCHDOG TIMER FLAG SET CLEAR to interface: read WDTF WDE = MCU loading watchdog counter set alarm flag, AF from interface: clear AF set timestamp flag, TSF from interface: clear TSF set battery flag, BF from interface: clear BF set battery low flag, BLF from battery low detection circuit: clear BF AF: ALARM FLAG SET CLEAR TSF: TIMESTAMP FLAG SET CLEAR BF: BATTERY FLAG SET CLEAR BLF: BATTERY LOW FLAG SET CLEAR to interface: read AF to interface: read TSF to interface: read BF to interface: read BLF AIE TSIE BIE BLIE pcf212-7-ch When SI, MI, WDE, AIE, TSIE, BIE, BLIE are all disabled, INT will remain high impedance. Fig 19. Interrupt block diagram Objective data sheet Rev..1 29 August 28 34 of 68
T D T A The control bit TI_TP is used to configure the interrupts generated from the second/minute timer as pulsed signals or as permanently active signals which follow the status of the corresponding flags MSF and CDTF. All the other interrupt sources generate a permanently active interrupt signal which follows the status of the corresponding flags. The flags must be cleared to clear the interrupt. The flags MSF, CDTF, AF, TSF and BF are cleared using an interface. The flags, bit WDTF and bit BLF are read only and cannot be cleared by using an interface. The flag WDTF is cleared by loading a value in the watchdog timer register (11h). The flag BLF is cleared automatically from the battery low detection circuit when the battery is replaced. When the interrupt sources are all disabled INT remains as a high impedance. 8.14.1 Minute/Second interrupts The minute and second interrupts are pre-defined timers for generating periodic interrupts. The timers can be enabled independently from one another by MI and SI bits (Bit 1 and of the control register h), however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Table 44. The minute/second flag, bit MSF, is set to logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt (see Table 44). The MSF flag can be read and cleared by the interface. Table 44. Minute interrupt, MI Effect of bits MI and SI on INT generation and on bit MSF Second interrupt, SI Result on INT Result on MSF no interrupt generated MSF never set 1 an interrupt once per minute MSF set when minutes counter increments 1 an interrupt once per second MSF set when seconds counter increments 1 1 an interrupt once per second MSF set when seconds counter increments The interrupt may be generated as a pulsed signal every second/minute or as a permanently active signal which follows the condition of MSF. Bit TI_TP is used to control this mode selection (see Figure 2 and Figure 21). Objective data sheet Rev..1 29 August 28 35 of 68
T D T A seconds counter 58 59 59 1 minutes counter 11 12 INT when SI enable MSF when SI enable INT when only MI enabled MSF when only MI enabled 1aag72 Fig 2. INT example for SI and MI when TI_TP = In the example shown in Figure 2, bit TI_TP = and the MSF flag is cleared after an interrupt. seconds counter 58 59 59 1 minutes counter 11 12 INT when SI enabled MSF when SI enabled INT when only MI enabled MSF when only MI enabled 1aaf95 Fig 21. INT example for SI and MI when TI_TP = 1 In Figure 21 bit TI_TP = 1 and the MSF flag is not cleared after an interrupt. The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 1 64 seconds in duration. If the MSF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 22. Instructions for clearing bit MSF are given in Section 8.12.3. Objective data sheet Rev..1 29 August 28 36 of 68