RV-8803-C7. Datasheet_DRAFT. Date: September 2014 Revision N : /59 Headquarters: Micro Crystal AG Mühlestrasse 14 CH-2540 Grenchen Switzerland

Transcription

1 RV-8803-C7 Datasheet_DRAFT Date: September 2014 Revision N : /59 Headquarters: Micro Crystal AG Mühlestrasse 14 CH-2540 Grenchen Switzerland Tel. Fax Internet sales@microcrystal.com

2 TABLE OF CONTENTS 1. OVERVIEW GENERAL DESCRIPTION APPLICATIONS BLOCK DIAGRAM PINOUT PIN DESCRIPTION... 7 FUNCTIONAL DESCRIPTION... 8 DEVICE PROTECTION DIAGRAM REGISTER ORGANIZATION REGISTER OVERVIEW CLOCK REGISTERS CALENDAR REGISTERS ALARM REGISTERS PERIODIC COUNTDOWN TIMER CONTROL REGISTERS EXTENSION REGISTER FLAG REGISTER CONTROL REGISTER OSC OFFSET CONTROL REGISTER CAPTURE BUFFER/EVENT CONTROL REGISTERS REGISTER RESET VALUES SUMMARY DETAILED FUNCTIONAL DESCRIPTION POWER ON RESET (POR) POWER MANAGEMENT CLOCK SOURCES PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION COMPLETE PERIODIC COUNTDOWN TIMER DIAGRAM USE OF THE PERIODIC COUNTDOWN TIMER INTERRUPT PERIODIC TIME UPDATE INTERRUPT FUNCTION COMPLETE PERIODIC TIME UPDATE DIAGRAM USE OF THE PERIODIC TIME UPDATE INTERRUPT ALARM INTERRUPT FUNCTION COMPLETE ALARM DIAGRAM USE OF THE ALARM INTERRUPT EXTERNAL EVENT INTERRUPT FUNCTION USE OF THE EXTERNAL EVENT INTERRUPT SERVICING INTERRUPTS DIGITAL ARCHITECTURE SUMMARY TEMPERATURE COMPENSATION /59

3 COMPENSATION FREQUENCY DRIFT OFFSETX CORRECTION CLOCKING SCHEME MEASURING THE 1024 HZ TIME ACCURACY AT CLKOUT PIN MEASURING THE 1 HZ FREQUENCY ACCURACY AT CLKOUT PIN MEASURING THE 1 HZ FREQUENCY ACCURACY AT INT PIN MEASURING 1 HZ WITH THE PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION MEASURING 1 HZ WITH THE PERIODIC TIME UPDATE INTERRUPT FUNCTION FREQUENCY ACCURACY 1 HZ EXAMPLE I 2 C INTERFACE BIT TRANSFER START AND STOP CONDITIONS DATA VALID SYSTEM CONFIGURATION ACKNOWLEDGE SLAVE ADDRESS WRITE OPERATION READ OPERATION AT SPECIFIC ADDRESS READ OPERATION ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS OPERATING PARAMETERS OSCILLATOR PARAMETERS XTAL FREQUENCY VS. TEMPERATURE CHARACTERISTICS POWER ON AC ELECTRICAL CHARACTERISTICS BACKUP AND RECOVERY I 2 C AC ELECTRICAL CHARACTERISTICS APPLICATION INFORMATION OPERATING RV-8803-C7 WITH BACKUP CAPACITOR OPERATING RV-8803-C7 AS A CLOCK SOURCE (32 khz NOT TEMP. COMP.) RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING) PACKAGE DIMENSIONS AND SOLDER PAD LAYOUT MARKING AND PIN #1 INDEX PACKING INFORMATION CARRIER TAPE PARTS PER REEL REEL 7 INCH FOR 12 mm TAPE HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS /59

4 12. DOCUMENT REVISION HISTORY /59

5 RV-8803-C7 Highly accurate with I 2 C Interface 1. OVERVIEW Register compatible to Epson RX-8803SA/LC khz built-in Tuning Fork crystal oscillator Factory calibrated, temperature compensated (1 Hz) I 2 C (up to 400 khz) serial interface Alarm interrupts for date, weekday, hour and minute settings Periodic countdown timer interrupt function Periodic time update interrupt function (Seconds, minutes) Clock output with OE ( khz / 1024 Hz / 1 Hz) Automatic leap year calculation (2000 to 2099) Wide interface voltage range: 1.5 to 5.5V Wide time-keeping voltage range: 1.5 to 5.5V Very high frequency accuracy at 1 Hz: o ± 1.5 ppm 0 to +50 C o ± 3.0 ppm -40 to +85 C Very low current consumption: 250 na (V DD = 3.0V) External event interrupt function Operating temperature range: -40 to +85 C Ultra small and compact C7 package size, RoHS-compliant and 100% leadfree: 3.2 x 1.5 x 0.8 mm 1.1. GENERAL DESCRIPTION The RV-8803-C7 is a highl accurate real-time clock/calendar module due to an integrated temperature compensation circuitry. The built-in Thermometer and Digital Temperature Compensation circuitry (DTCXO) provide improved frequency accuracy on the 1 Hz clock by compensating the frequency deviation over the full temperature range based on precise, factory calibrated correction values. The RV-8803-C7 has the smallest package and the lowest current consumption among all temperature compensated RTC modules APPLICATIONS The RV-8803-C7 RTC module combines key functions with outstanding performance in an ultra-small ceramic package: Factory calibrated Temperature Compensation Ultra Low Power consumption Smallest RTC module (embedded XTAL) in an ultra-small 3.2 x 1.5 x 0.8 mm leadfree ceramic package. These unique features make this product perfectly suitable for many applications: Communication: Wireless Sensors and tags, Handsets, Communications equipment Automotive: Navigation & Tracking Systems / Dashboard / Tachometers / Engine Controller / Car Audio & Entertainment Systems Metering: E-Meter / Heating Counter / Smart Meters / PV Converter Outdoor: ATM & POS systems / Surveillance & Safety systems / Ticketing Systems Medical: Glucose Meter / Health Monitoring Systems Safety: Security & Camera Systems / Door Lock & Access Control Consumer: Gambling Machines / TV & Set Top Boxes / White Goods Automation: Data Logger / Home & Factory Automation / Industrial and Consumer Electronics 5/59

6 2. BLOCK DIAGRAM 6/59

7 2.1. PINOUT C7 Package: #1 SDA #8 SCL #2 CLKOUT #7 EVI #3 V DD #6 INT #4 CLKOE #5 V SS PIN DESCRIPTION Symbol Pin # Description SDA 1 I 2 C Serial Data; open-drain; requires pull-up resistor CLKOUT 2 Clock Output controlled by CLKOE. If CLKOE =1, the CLKOUT pin drives the square wave of khz, 1024 Hz or 1Hz (Default value is khz). When CLKOE = 0, the CLKOUT pin is high impedance V DD 3 Power Supply Voltage CLKOE 4 Input to enable the CLKOUT pin. If CLKOE =1, the CLKOUT pin is in output mode. When CLKOE = 0, the CLKOUT pin is stopped V SS 5 Ground INT 6 Interrupt Output; open-drain; requires pull-up resistor; Used to output alarm, countdown timer, time update and external event interrupt signals EVI 7 External Event Interrupt Input SCL 8 I 2 C Serial Clock Input; open-drain; requires pull-up resistor 7/59

8 2.3. FUNCTIONAL DESCRIPTION The RV-8803-C7 is a high accurate, ultra-low power CMOS based Real-Time-Clock Module with embedded khz Crystal. The high accuracy and high stability is achieved by the built-in Digital Temperature Compensation circuitry (DTCXO) with a frequency accuracy of ± 3.0 ppm on the 1 Hz clock across the temperature range from -40 C to +85 C. The compensation of the 1 Hz frequency deviation over the full temperature range is obtained by inhibition of khz oscillator pulses and fractional parts from the 10 MHz RC oscillator. The factory calibrated correction values are located in the EEPROM and therefore not accessible for the user. An offset correction that shifts the frequency vs. temperature curve vertically is also integrated. Therefore a factory calibrated correction value is located in the OFFSETX field. The user has access to this field. The RV-8803-C7 provides standard Clock & Calendar function including seconds, minutes, hours (24), weekdays, date, months, years (with leap year calculation) and interrupt functions for an External Event, Periodic Countdown Timer, Periodic Time Update and Alarm. Beside the standard RTC functions, it includes an integrated Temperature Sensor, an External Event Input and User RAM and offers an I 2 C-bus (2-wire Interface). Up to 13 bytes/registers of general purpose ultra-low leakage RAM enable the storage of key parameters. The registers are accessed by selecting a register address and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the address automatically incrementing after each byte DEVICE PROTECTION DIAGRAM 8/59

9 3. REGISTER ORGANIZATION Registers are accessed by selecting a register address and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the address automatically incrementing after each byte. The following tables Register Definitions (00h to 0Fh), (10h to 1Fh) and (20h to 2Fh) summarize the function of each register. In the table Register Definitions (00h to 0Fh) and (10h to 1Fh) the GPx bits (where x is between 0 and 5) are 6 register bits which may be used as general purpose storage. These bits are not described in the sections below. All of the GPx bits are cleared when the RV-8803-C7 powers up, and they can therefore be used to allow software to determine if a true Power On Reset has occurred or hold other initialization data. The registers are compatible to Epson RX-8803SA/LC. Address 00h to 0Fh: Basic time and calendar register Adds RAM Address 10h to 1Fh: Extension register Adds 1/100 Seconds counter Address 20h to 2Fh: Extension register Capture buffer and Event control When writing or reading a specific function value into/from the Address range 00h to 0Fh the value will be automatically updated in the Address range 10h to 1Fh and vice versa REGISTER OVERVIEW Register Definitions, Address 00h to 0Fh (Basic time and calendar register): Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h Seconds h Minutes h Hours h Weekday h Date h Month h Year h RAM RAM data 08h Minutes Alarm AE_M h Hours Alarm AE_H GP Ah Weekday Alarm AE_WD Date Alarm GP Bh Timer Counter Ch Timer Counter 1 GP5 GP4 GP3 GP Dh Extension Register TEST WADA USEL TE FSEL TSEL 0Eh Flag Register UF TF AF EVF VL2F VL1F 0Fh Control Register CSEL UIE TIE AIE EIE RESET 9/59

10 Register Definitions, Address 10h to 1Fh (Extension register ): Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10h 1/100 S (Read Only) h Seconds h Minutes h Hours h Weekday h Date h Month h Year h Minutes Alarm AE_M h Hours Alarm AE_H GP Ah Weekday Alarm AE_WD Date Alarm GP Bh Timer Counter Ch Timer Counter 1 GP5 GP4 GP3 GP Dh Extension Register TEST WADA USEL TE FSEL TSEL 1Eh Flag Register UF TF AF EVF VL2F VL1F 1Fh Control Register CSEL UIE TIE AIE EIE RESET Register Definitions, Address 20h to 2Fh (Extension register ): Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20h 1/100 S CP (Read Only) h SEC CP (Read Only) h-2Bh RAM RAM data (10 Bytes) 2Ch Xtal Offset OFFSETX 2Dh-2Eh RAM RAM data (2 Bytes) 2Fh Event Control ECP EHL ET ERST 10/59

11 3.2. CLOCK REGISTERS 10h - 1/100 Seconds (Read Only) This register holds the count of hundredths of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 99. Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10h 1/100 S (Read Only) h Reset Bit Symbol Value Description 7:0 1/100 S (Read Only) 00 to 99 Holds the count of hundredths of seconds, coded in BCD format. 00h, 11h - Seconds This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h, 11h Seconds h, 11h Reset Bit Symbol Value Description 7 0 Read only. Always 0. 6:0 Seconds 00 to 59 Holds the count of seconds, coded in BCD format. 01h, 12h - Minutes This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01h, 12h Minutes h, 12h Reset Bit Symbol Value Description 7 0 Read only. Always 0. 6:0 Minutes 00 to 59 Holds the count of minutes, coded in BCD format. 02h, 13h - Hours This register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to 23. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 02h, 13h Hours h, 13h Reset Bit Symbol Value Description 7:6 0 Read only. Always 0. 5:0 Hours 00 to 23 Holds the count of hours, coded in BCD format. 11/59

12 3.3. CALENDAR REGISTERS 03h, 14h - Weekday This register holds the current day of the week, and has to be set independently by the user. It uses a particular format. Do not set 1 to more than one day at the same time. Also note with caution that any setting other than the seven shown below should be made as it may interfere with normal operation. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 03h, 14h Weekday h, 14h Reset Bit Symbol Value Description 7 0 Read only. Always 0. 6:0 Weekday 0 to 6 Holds the weekday counter value, coded in a particular format. Weekday Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sunday Monday Tuesday Wednesday Thursday Friday Saturday h, 15h Date This register holds the current date of the month, in two binary coded decimal (BCD) digits. Values will range from 01 to 31. Leap years are correctly handled from 2000 to Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 04h, 15h Date h, 15h Reset Bit Symbol Value Description 7:6 0 Read only. Always 0. 5:0 Date 01 to 31 Holds the current date of the month, coded in BCD format. 05h, 16h - Month This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 05h, 16h Month h, 16h Reset Bit Symbol Value Description 7:5 0 Read only. Always 0. 4:0 Month 01 to 12 Holds the current month, coded in BCD format. 12/59

13 06h, 17h - Year This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 06h, 17h Year h, 17h Reset Bit Symbol Value Description 7:0 Year 00 to 99 Holds the current year, coded in BCD format. 07h - RAM This register holds the bits for general purpose use. Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 07h RAM RAM data 07h Reset Bit Symbol Value Description 00 to 7:0 RAM User RAM FF 13/59

14 3.4. ALARM REGISTERS 08h, 18h Minutes Alarm This register holds the Minutes Alarm Enable bit AE_M and the alarm value for minutes, in two binary coded decimal (BCD) digits. Values will range from 00 to 59. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h, 18h Minutes Alarm AE_M h, 18h Reset Bit Symbol Value Description 7 AE_M 0 or 1 Minutes Alarm Enable bit 0: Minutes Alarm is enabled 1: Minutes Alarm is disabled 6:0 Minutes Alarm 00 to 59 Holds the alarm value for minutes, coded in BCD format. 09h, 19h Hours Alarm This register holds the Hours Alarm Enable bit AE_H and the alarm value for hours, in two binary coded decimal (BCD) digits. Values will range from 00 to 23. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 09h, 19h Hours Alarm AE_H GP h, 19h Reset Bit Symbol Value Description 7 AE_H 0 or 1 Hours Alarm Enable bit 0: Hours Alarm is enabled 1: Hours Alarm is disabled 6 GP0 0 or 1 Register bit for general purpose use. 5:0 Hours Alarm 00 to 23 Holds the alarm value for hours, coded in BCD format. 14/59

15 0Ah, 1Ah Weekday/Date Alarm This register holds the Weekday/Date Alarm Enable bit AE_WD and If the WADA bit is 0, it holds the alarm value for the day of the week, coded in a particular format. If the WADA bit is 1, it holds the alarm value for the date, in two binary coded decimal (BCD) digits. Values will range from 01 to 31. Weekday Alarm (WADA = 0) Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ah, 1Ah Weekday Alarm AE_WD Ah, 1Ah Reset Bit Symbol Value Description 7 AE_WD 0 or 1 Weekday/Date Alarm Enable bit 0: Weekday/Date Alarm is enabled 1: Weekday/Date Alarm is disabled 6:0 Weekday Alarm 0 to 6 Holds the weekday alarm value, coded in a particular format. Weekday Alarm Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sunday 0 or Monday 0 or Tuesday 0 or Wednesday 0 or Thursday 0 or Friday 0 or Saturday 0 or Date Alarm (WADA = 1) Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ah, 1Ah Date Alarm AE_WD GP Ah, 1Ah Reset Bit Symbol Value Description 7 AE_WD 0 or 1 Weekday/Date Alarm Enable bit 0: Weekday/Date Alarm is enabled 1: Weekday/Date Alarm is disabled 6 GP1 0 or 1 Register bit for general purpose use. 5:0 Date Alarm 01 to 31 Holds the alarm value for the date, coded in BCD format. 15/59

16 3.5. PERIODIC COUNTDOWN TIMER CONTROL REGISTERS 0Bh, 1Bh Timer Counter 0 This register is used to set the lower 8 bits of the preset value for the periodic countdown timer. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh, 1Bh Timer Counter Bh, 1Bh Reset Bit Symbol Value Description 7:0 Timer Counter 0 00h to FFh The preset value for the Periodic Countdown Timer (lower 8 bit). 0Ch, 1Ch Timer Counter 1 This register is used to set the upper 4 bits of the preset value for the periodic countdown timer. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ch, 1Ch Timer Counter 1 GP5 GP4 GP3 GP Ch, 1Ch Reset Bit Symbol Value Description 7 GP2 0 or 1 Register bit for general purpose use. 6 GP3 0 or 1 Register bit for general purpose use. 5 GP4 0 or 1 Register bit for general purpose use. 4 GP5 0 or 1 Register bit for general purpose use. 3:0 Timer Counter 1 0h to Fh The preset value for the Periodic Countdown Timer (upper 4 bit). 16/59

17 3.6. EXTENSION REGISTER 0Dh, 1Dh Extension Register This register is used to specify the target for the Alarm function and the Periodic Time Update interrupt function and to select or set operations for the Periodic Countdown timer. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Dh, 1Dh Extension Register TEST WADA USEL TE FSEL TSEL 0Dh, 1Dh Reset Bit Symbol Value Description 7 TEST 0 This is a manufacturer s test bit. Its value should always be 0. Avoid writing a 1 to this bit when writing in this register. Zero for normal operation. 6 WADA 0 or 1 Weekday Alarm / Date Alarm selection bit. This bit is used to specify either the Weekday or Date as the source for the Alarm interrupt function. 0 = Weekday is the source for the alarm interrupt function Default value 1 = Date is the source for the alarm interrupt function 5 USEL 0 or 1 Update Interrupt Select bit. This bit is used to specify either Second update or Minute update for the update generation timing of the Periodic Time Update interrupt function. 0 = Second update (Auto reset time t RTN = 500 ms) Default value 1 = Minute update (Auto reset time t RTN = 15.6 ms) 4 TE 0 or 1 Timer Enable bit. This bit controls the start/stop setting for the Periodic Countdown Timer interruption function. 0 = Stop of the Periodic Countdown Timer interrupt function Default value 1 = Start of the Periodic Countdown Timer interrupt function (a countdown starts from a pre-set value) 3:2 FSEL 00 to 11 CLKOUT frequency selection. Set the output frequency on the CLKOUT pin. See table below. 1:0 TSEL 00 to 11 Timer source frequency selection. Set the countdown period (source clock) for the Periodic Countdown Timer interrupt function. With this setting the Auto reset time t RTN and the effect of the RESET bit is also defined. See table below. FSEL Value Hz Default value Hz 10 1 Hz Hz CLKOUT frequency TSEL Value Timer source frequency Countdown period t RTN RESET bit Hz Default value μs 122 μs The RESET bit has no effect Hz ms 15.6 ms If the RESET bit = 1, the 10 1 Hz 1 s 15.6 ms interrupt function is 11 1/60 Hz 60 s 15.6 ms stopped. 17/59

18 3.7. FLAG REGISTER 0Eh, 1Eh Flag Register This register holds a variety of status bits. The register may be written at any time to clear or set any status flag. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Eh, 1Eh Flag Register UF TF AF EVF VL2F VL1F 0Eh, 1Eh Reset Bit Symbol Value Description 7:6 0 Read only. Always 0. 5 UF 0 or 1 Update Flag. If set to 0 beforehand, indicates the occurrence of an update interrupt event. It can be cleared by writing a 0 to the bit. For details, see PERIODIC TIME UPDATE INTERRUPT FUNCTION. 4 TF 0 or 1 Timer Flag. If set to 0 beforehand, indicates the occurrence of a Periodic Countdown Timer interrupt event. It can be cleared by writing a 0 to the bit. For details, see PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION. 3 AF 0 or 1 Alarm Flag. If set to 0 beforehand, indicates the occurrence of an alarm interrupt event. It can be cleared by writing a 0 to the bit. For details, see ALARM INTERRUPT FUNCTION. 2 EVF 0 or 1 External Event Flag. If set to 0 beforehand, indicates the occurrence of an external interrupt event. It can be cleared by writing a 0 to the bit. 1 VL2F 0 or 1 Voltage Low Flag 2. Set if the voltage crosses V LOW2 voltage and the data in the device are no longer valid. It can be cleared by writing a 0 to the bit. The flag is automatically set to 1 at power on reset (POR) and has to be cleared by writing a 0 to the bit. - Writing a 0: The VL2F bit is cleared to prepare for a next low voltage detection. - Writing a 1: The VL2F bit is invalid. - Reading a 0: No data loss detected. - Reading a 1: Data loss detected. All registers must be initialized 0 VL1F 0 or 1 Voltage Low Flag 1. Set if the voltage crosses V LOW1 voltage and the temperature compensation is stopped. It can be cleared by writing a 0 to the bit. The flag is automatically set to 1 at power on reset (POR) and has to be cleared by writing a 0 to the bit. - Writing a 0: The VL1F bit is cleared to prepare for a next low voltage detection. - Writing a 1: The VL1F bit is invalid. - Reading a 0: Temperature compensation is effective. - Reading a 1: Temperature compensation stop is detected. 18/59

19 3.8. CONTROL REGISTER 0Fh, 1Fh Control Register This register is used to control the interrupt event output from the INT pin and the stop/start status of clock and calendar operations. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Fh, 1Fh Control Register CSEL UIE TIE AIE EIE RESET 0Fh, 1Fh Reset Bit Symbol Value Description 7:6 CSEL 0 Unused, but has to be 0 to avoid extraneous leakage. 5 UIE 0 or 1 4 TIE 0 or 1 3 AIE 0 or 1 Time Update Interrupt Enable. Defines if an interrupt signal on INT pin has to be generated when a Periodic Time Update event occurs. When 1, an interrupt signal is generated on INT pin when a Periodic Time Update event occurs. The low-level output signal is automatically cleared after t RTN = 500 ms (Second update) or t RTN = 15.6 ms (Minute update). When 0, no interrupt signal is generated on INT pin when a Periodic Time Update event occurs or the signal is cancelled on INT pin. Countdown Timer Interrupt Enable. Defines if an interrupt signal on INT pin has to be generated when a Periodic Countdown Timer event occurs When 1, an interrupt signal is generated on INT pin when a Periodic Countdown Timer event occurs. The low-level output signal is automatically cleared after t RTN = 122 µs (TSEL = 00) or t RTN = 15.6 ms (TSEL = 01, 10, 11). When 0, no interrupt signal is generated on INT pin when a Periodic Countdown Timer event occurs or the signal is cancelled on INT pin. Alarm Interrupt Enable. Defines if an interrupt signal on INT pin has to be generated when an Alarm event occurs. When 1, an interrupt signal is generated on INT pin when an Alarm event occurs. This setting is retained until the AF bit value is cleared to 0 (no automatic cancellation). When 0, no interrupt signal is generated on INT pin when an Alarm event occurs or the signal is cancelled on INT pin. 2 EIE 0 or 1 External Event Interrupt Enable. Defines if an interrupt signal on INT pin has to be generated when an External Event on EVI pin occurs. When 1, an interrupt signal is generated on INT pin when an External Event on EVI pin occurs. This setting is retained until the EVF bit value is cleared to 0 (no automatic cancellation). When 0, no interrupt signal is generated on INT pin when an External Event on EVI pin occurs. 1 0 Read only. Always 0. 0 RESET 0 or 1 When the RESET bit is set to 1, values (less than seconds) of the counter in the clock and calendar circuitry are reset, and the clock also stops. 19/59

20 3.9. OSC OFFSET CONTROL REGISTER 2Ch Xtal Offset Register This register holds the OFFSETX field for the digital offset correction at the 1 Hz clock level. This register is initialized with a factory value which calibrates the Xtal Oscillator. See also chapter OFFSETX CORRECTION. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2Ch Xtal Offset OFFSETX 2Ch Reset 0 0 Preconfigured (Factory Calibrated) Bit Symbol Value Description 7:6 0 Read only. Always 0. 5:0 OFFSETX to The amount of the effective frequency offset. This is a two's complement number with a range of -2^6 to +2^6-1 adjustment steps (Factory Calibrated). The correction value of one LSB corresponds to 1/(32768*128) = ppm. OFFSETX Unsigned value Two s complement Correction value in ppm : : : : : : : : /59

21 3.10.CAPTURE BUFFER/EVENT CONTROL REGISTERS 20h - 1/100 S CP (Read Only) This register holds a captured (copied) value of the 1/100 Seconds register, in two binary coded decimal (BCD) digits. The values are from 00 to 99. Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20h 1/100 S CP (Read Only) h Reset Bit Symbol Value Description 7:0 1/100 S CP (Read Only) 00 to 99 Holds a captured value of the 1/100 Seconds register, coded in BCD format. 21h - SEC CP (Read Only) This register holds a captured (copied) value of the Seconds register, in two binary coded decimal (BCD) digits. The values are from 00 to 59. Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 21h SEC CP (Read Only) h Reset Bit Symbol Value Description 7 0 Read only. Always 0. 6:0 SEC CP (Read Only) 00 to 59 Holds a captured value of the Seconds register, coded in BCD format. 2Fh Event Control This register controls the event detection on the EVI pin. Depending of the EHL bit a high or a low signal can be detected. Moreover a glitch filtering can be applied to the EVI signal by setting the value of the ET field (subsampling). Addresses Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2Fh Event Control ECP EHL ET ERST 2Fh Reset Bit Symbol Value Description 7 ECP 0 or 1 Event Capture Enable. When 1, an External Event detected on pin EVI will cause a capture of the seconds and the 1/100 seconds, i.e. they are copied into the SEC CP and 1/100 S CP registers. When 0, capture does not operate. 6 EHL 0 or 1 High/Low detection Select. When 1, the high level is regarded as the External Event Interrupt on pin EVI. When 0, the low level is regarded as the External Event Interrupt on pin EVI. 5:4 ET 00 to 11 Event Filtering Time set. Applies a filtering to the EVI pin by subsampling the EVI signal. See ET values below. 3:1 0 Read only. Always 0. 0 ERST 0 or 1 Event Reset. When 1, in case of an event detection the counters of seconds and 1/100 seconds are set to 0. Moreover, the 1/100 S CP and SEC CP registers are also set to 0, whatever the ECP value is. After the event detection, the ERST bit is reset to 0. ET Value 00 No filtering ms sampling rate ms sampling rate ms sampling rate Sampling rate 21/59

22 3.11.REGISTER RESET VALUES SUMMARY Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10h 1/100 S (Read Only) h, 11h Seconds h, 12h Minutes h, 13h Hours h, 14h Weekday h, 15h Date h, 16h Month h, 17h Year h RAM h, 18h Minutes Alarm h, 19h Hours Alarm Ah, 1Ah Weekday Alarm / Date Alarm Bh, 1Bh Timer Counter Ch, 1Ch Timer Counter Eh, 1Eh Flag Register Fh, 1Fh Control Register h 1/100 S CP (Read Only) h SEC CP (Read Only) h-2Bh RAM Ch Xtal Offset 0 0 Preconfigured (Factory Calibrated) 2Dh-2Eh RAM Fh Event Control /59

23 4. DETAILED FUNCTIONAL DESCRIPTION 4.1. POWER ON RESET (POR) The power on reset (POR) is generated at start-up of V DD (see POWER ON AC ELECTRICAL CHARACTERISTICS). All registers including the Counter Registers are initialized to their reset values POWER MANAGEMENT The circuit is always on. The digital part is always on, but some functions are clock gated (like I 2 C). The analog blocks are switched of when not used (for example the RC oscillator for the thermometer). By default, at power up, the circuit will always go to the lower power consumption mode (power-off). Detecting an activity on the I 2 C will wake-up the digital part of the circuit CLOCK SOURCES There are tree clock sources: 1. The built-in khz crystal is the main clock source for the digital part. After thermal compensation and division, this low-power quartz oscillator is the time reference of the RV-8803-C7. 2. A fully integrated RC oscillator with about 10 MHz is used for temperature measurement and thermal compensation. 3. The I 2 C clock on the SCL pin provides an independent clock for the I 2 C part, which allows a continuous access to the registers without the need of any other clocks PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION The Periodic Countdown Timer interrupt function generates an interrupt event periodically at any period set from μs to 4095 minutes. When an interrupt event is generated, the INT pin goes to the low level and the TF flag is set to 1 to report that an event has occurred. The output on the INT pin is only effective if the TIE bit in the Control Register is set to 1. The low-level output signal on the INT pin is automatically cleared after the Auto reset time t RTN. t RTN = 122 µs (TSEL = 00) or t RTN = 15.6 ms (TSEL = 01, 10, 11). Periodic Countdown Timer Interrupt Example: 23/59

24 4.4.1.COMPLETE PERIODIC COUNTDOWN TIMER DIAGRAM Complete Diagram of the Periodic Countdown Timer interrupt function: The Periodic Countdown Timer starts from the pre-set value when writing a 1 to the TE bit. The TSEL field determines the source frequency and the Auto reset time t RTN. t RTN = 122 µs (TSEL = 00) or t RTN = 15.6 ms (TSEL = 01, 10, 11). A Periodic Countdown Timer interrupt event starts a countdown based on the countdown period (source clock). When the count value reaches 000h, an interrupt event occurs. After the interrupt, the counter is automatically reloaded with the pre-set value, and starts again the countdown. When a Periodic Countdown Timer interrupt occurs, the TF bit is set to 1. The TIE bit is 0 or 1. The TF bit retains 1 until it is cleared to 0 by software. If the TIE bit is 1 and a periodic countdown interrupt occurs, the INT pin output goes low. The INT pin output remains low during the Auto reset time t RTN, and then it is automatically cleared to 1. When a 0 is written to the TE bit, the Periodic Countdown Timer function is stopped and the INT pin is cleared after the Auto reset time t RTN. If the INT pin is low, its status does not change when the TF bit value is cleared to 0. If the INT pin is low, its status changes as soon as the TIE bit value is cleared to 0. 24/59

25 4.4.2.USE OF THE PERIODIC COUNTDOWN TIMER INTERRUPT The following registers, fields and bits are related to the Periodic Countdown Timer interrupt function: Timer Counter 0 Register (0Bh, 1Bh) (see PERIODIC COUNTDOWN TIMER CONTROL REGISTERS) Timer Counter 1 Register (0Ch, 1Ch) (see PERIODIC COUNTDOWN TIMER CONTROL REGISTERS) TE bit and TSEL field (see EXTENSION REGISTER, 0Dh, 1Dh) TF bit (see FLAG REGISTER, 0Eh, 1Eh) TIE bit (see CONTROL REGISTER, 0Fh, 1Fh) Before entering any timer settings for the Periodic Countdown Timer interrupt, it is recommended to write a 0 to the TIE and TE bits to prevent inadvertent hardware interrupts. When the RESET bit value is 1, the Periodic Countdown Timer interrupt function operates only partially (operation continues if the source clock setting is 4096 Hz, otherwise, operation is stopped). When the Periodic Countdown Timer interrupt function is not used, thetimer Counter registers 0Bh, 1Bh and 0Ch, 1Ch can be used as RAM bytes. The Timer source frequency selection field TSEL is used to set the countdown period (source clock) for the Periodic Countdown Timer interrupt function (four settings are possible). Procedure to use the Periodic Countdown Timer interrupt: 1. Write 0 in TIE, TE and TF bits. 2. Choose the timer source clock and write the corresponding value in the TSEL field. 3. Choose the interrupt period based on the timer source clock, and write the corresponding preset value to the registers Timer Counter 0 (0Bh,1Bh) and Timer Counter 1 (0Ch,1Ch). Interrupt period: Timer counter setting (0Bh,1Bh), (0Ch,1Ch) Interrupt perriod TSEL = 00 (4096 Hz) TSEL = 01 (64 Hz) TSEL = 10 (1 Hz) TSEL = 11 (1/60 Hz) μs ms 1 s 1 min μs ms 2 s 2 min : : : : : ms ms 41 s 41 min ms s 205 s 205 min ms s 410 s 410 min ms s 2048 s 2048 min : : : : : 4095 (FFFh) s s 4095 s 4095 min 4. Set the TIE bit to 1 if you want to get a hardware interrupt on INT pin. 5. Set the TE bit from 0 to 1 to start the countdown timer. The countdown starts at the rising edge of the SCL signal after Bit 0 of the Address D is transferred. The following figure shows the countdown start timing. 25/59

26 Start timing of the Periodic Countdown Timer: Address D SCL SDA TE FSEL(1) FSEL(0) TSEL(1) TSEL(0) ACK Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Internal Timer INT event period Rising edge of the SCL 26/59

27 4.5. PERIODIC TIME UPDATE INTERRUPT FUNCTION The Periodic Time Update interrupt function generates an interrupt event periodically at one-second or one-minute intervals, according to the selected timing clock. When an interrupt event is generated, the INT pin goes to the low level and the UF flag is set to 1 to report that an event has occurred. The output on the INT pin is only effective if the UIE bit in the Control Register is set to 1. The low-level output signal on the INT pin is automatically cleared after the Auto reset time t RTN. t RTN = 500 ms (Second update) or t RTN = 15.6 ms (Minute update). Periodic Time Update Interrupt Example: COMPLETE PERIODIC TIME UPDATE DIAGRAM Complete Diagram of the Periodic Time Update interrupt function: A Periodic Time Update interrupt event occurs when the internal clock value matches either the second or the minute update time. The USEL bit determines whether it is the second or the minute period and the Auto reset time t RTN. t RTN = 500 ms (Second update) or t RTN = 15.6 ms (Minute update). When a Periodic Time Update interrupt occurs, the UF bit is set to 1. The UIE bit is 0 or 1. The UF bit retains 1 until it is cleared to 0 by software. If the UIE bit is 1 and a Periodic Time Update interrupt occurs, the INT pin output goes low. The INT pin output remains low during the Auto reset time t RTN, and then it is automatically cleared to 1. If the INT pin is low, its status does not change when the UF bit value is cleared to 0. If the INT pin is low, its status changes as soon as the UIE bit value is cleared to 0. 27/59

28 4.5.2.USE OF THE PERIODIC TIME UPDATE INTERRUPT The following bits are related to the Periodic Time Update interrupt function: USEL bit (see EXTENSION REGISTER, 0Dh, 1Dh) UF bit (see FLAG REGISTER, 0Eh, 1Eh) UIE bit (see CONTROL REGISTER, 0Fh, 1Fh) Before entering any other settings, it is recommended to write a 0 to the UIE bit to prevent inadvertent hardware interrupts. When the RESET bit value is 1, the Periodic Time Update interrupt function event does not occur. The Periodic Time Update interrupt function cannot be fully stopped, but by writing a 0 in the UIE bit, it prevents the occurrence of a hardware interrupt on the INT pin. Procedure to use the Periodic Time Update interrupt: 1. Write 0 in UIE and UF bits. 2. Choose the timer source clock and write the corresponding value in the USEL bit. 3. Set the UIE bit to 1 if you want to get a hardware interrupt on INT pin. 4. The first interrupt will occur after the next event, either second or minute change. 28/59

29 4.6. ALARM INTERRUPT FUNCTION The alarm interrupt function generates an interrupt for alarm settings such as date, weekday, hour or minute settings. When an interrupt event is generated, the INT pin goes to the low level and the AF flag is set to 1 to report that an event has occurred. Alarm Interrupt Example: COMPLETE ALARM DIAGRAM Complete Diagram of the alarm interrupt function: A date, weekday, hour or minute alarm interrupt event occurs when the selected Alarm register match the respective counter. The WADA bit determines whether it is the date or weekday. When an alarm interrupt event occurs, the AF bit value is set to 1. The AIE bit is 0 or 1. The AF bit retains 1 until it is cleared to 0 by software. If the AIE bit is 1 and an alarm interrupt occurs, the INT pin output goes low. If the AIE value is changed from 1 to 0 while the INT pin output is low, the INT pin status immediately changes its status. While the AF bit value is 1, the INT status can be controlled by the AIE bit. If the INT pin is low, its status changes as soon as the AF bit value is cleared from 1 to 0. If the AIE bit value is 0 when an alarm interrupt occurs, the INTpin status does not go low. 29/59

30 4.6.2.USE OF THE ALARM INTERRUPT The following registers and bits are related to the alarm interrupt function: Minutes Register (01h, 12h) (see CLOCK REGISTERS) Hours Register (02h, 13h) (see CLOCK REGISTERS) Weekday Register (03h, 14h) (see CALENDAR REGISTERS) Date Register (04h, 15h) (see CALENDAR REGISTERS) Minutes Alarm Register (08h, 18h) (see ALARM REGISTERS) Hours Alarm Register (09h, 19h) (see ALARM REGISTERS) Weekday/Date Alarm Register (0Ah, 1Ah) (see ALARM REGISTERS) AE_M bit (see ALARM REGISTERS, 08h, 18h) AE_H bit (see ALARM REGISTERS, 09h, 19h) AE_WD bit (see ALARM REGISTERS, 0Ah, 1Ah) WADA bit (see EXTENSION REGISTER, 0Fh, 1Fh) AF bit (see FLAG REGISTER, 0Eh, 1Eh) AIE bit (see CONTROL REGISTER, 0Fh, 1Fh) Before entering any timer settings for the alarm interrupt, it is recommended to write a 0 to the AIE bit to prevent inadvertent hardware interrupts. When the RESET bit value is 1, the alarm interrupt function event does not occur. When the alarm interrupt function is not used, the Alarm registers 08h,18h to 0Ah,1Ah can be used as RAM bytes. When the AIE bit is set to 1 and the Alarm registers are being used as RAM registers, INT may be changed to low level unintentionally. Procedure to use the alarm interrupt: 1. Write 0 in AIE and AF bits. 2. Choose the weekday alarm or date alarm by setting the WADA bit. 3. Write the desired alarm settings in registers 08h,18h to 0Ah,1Ah. The three bits, AE_M, AE_H and AE_WD, are used to select the corresponding register that has to be taken into account for match or not. 4. Set the AIE bit to 1 if you want to get a hardware interrupt on INT pin. 30/59

31 4.7. EXTERNAL EVENT INTERRUPT FUNCTION The external event interrupt function generates an interrupt when an external event on EVI pin is detected (high or low level detection). When an interrupt event is generated, the INT pin goes to the low level, the seconds and 1/100 seconds may be captured and copied into the SEC CP and 1/100 S CP registers and the EVF flag is set to 1 to report that an event has occurred USE OF THE EXTERNAL EVENT INTERRUPT The following registers and bits are related to the external event interrupt function: 1/100 S CP Register (20h) (see CLOCK REGISTERS) SEC CP Register (21h) (see CLOCK REGISTERS) ECP bit, EHL bit, ET field and ERST bit (see CLOCK REGISTERS, 2Fh) EVF bit (see FLAG REGISTER, 0Eh, 1Eh) EIE bit (see CONTROL REGISTER, 0Fh, 1Fh) Before entering any timer settings for the alarm interrupt, it is recommended to write a 0 to the EIE bit to prevent inadvertent hardware interrupts. Procedure to use the external event interrupt: 1. Write 0 in EIE and EVF bits. 2. Set the ECP bit to 1 if you want to capture the seconds and 1/100 seconds. 3. Choose high or low level detection on pin EVI by setting the EHL bit. 4. Set filtering to the EVI pin with the ET field 5. Set the ERST bit to 1 if you want to reset the seconds, 1/100 seconds and SEC CP, 1/100 S CP registers to 0 in case of an event detection. After the event detection, the ERST bit is reset to Set the EIE bit to 1 if you want to get a hardware interrupt on INT pin SERVICING INTERRUPTS The INT pin can indicate four types of interrupts. It outputs the OR'ed result of these interrupt outputs. When an interrupt is detected, (when the INT pin is at low level), the EVF, TF, UF and AF flags must be read to determine which interrupt event has occurred. To keep the INT pin from changing to low level, clear the EIE, TIE, UIE and AIE bits. To check whether an event has occurred without outputting any interrupts via the INT pin, software has to poll the EVF, TF, UF and AF interrupt flags. 31/59

32 4.9. DIGITAL ARCHITECTURE SUMMARY The following Figure illustrates the overall architecture of the pin inputs and outputs of the RV-8803-C7. Digital Architecture Summary: 32/59

33 5. TEMPERATURE COMPENSATION By compensating the frequency drift and integrating an offset correction, the 1 Hz frequency of the RV-8803-C7 has a high stability over the whole temperature range (± 3.0 ppm for -40 to +85 C). The compensation of the 1 Hz frequency deviation over the full temperature range is obtained by inhibition of khz oscillator pulses with fractional parts from the 10 MHz RC oscillator COMPENSATION FREQUENCY DRIFT The RV-8803-C7 is a RTC with an integrated Xtal oscillator. In order to compensate the frequency drift due to the temperature, the RTC is factory calibrated. The calibration is done by measuring the 32768Hz frequency at the CLKOUT pin at several temperatures and calculating the calibration coefficients. For an Nth order calibration, the frequencies at N+ 1 temperatures are measured. One temperature is used as reference, typically the room temperature T A = 25 C. As the RV-8803-C7 is a 4th order calibrated DTCXO, 5 measurements are done. All measured temperatures come from the internal Thermometer. The configuration with all coefficients is written in the internal EEPROM and is not accessible for the user OFFSETX CORRECTION The offset correction is purely digitally and has only the effect of shifting the frequency vs. temperature curve vertically. It has no effect on the frequency vs. temperature characteristics of the final frequency. The offset adjustment is done at the 1 Hz clock level. This function uses a offset value, OFFSETX (Factory Calibrated), which contains a two's complement number with a range of -2^6 to +2^6-1 adjustment steps. The minimal correction step (one LSB) is +/-1/(32768*128) = +/ ppm. The maximum correction range is roughly +/-7.4 ppm. Note that the signed offset value OFFSETX corresponds to the actual offset value of the measured frequency. The user has access to this field. See also OSC OFFSET CONTROL REGISTER. Examples: If Hz is measured when the 1 Hz clock is selected, the offset is Hz, which is Hz / 10-6 Hz = +1.2 ppm. The positive offset value is then calculated as follows: +1.2 ppm / ppm = +5.03, the integral part is +5. In binary, OFFSETX = If Hz is measured when the 1 Hz clock is selected, the offset is Hz, which is Hz / 10-6 Hz = -5.1 ppm. The negative offset value is then calculated as follows: -5.1 ppm / ppm = , the integral part is -21. The unsigned value is then = +43. In binary, OFFSETX = /59

34 5.3. CLOCKING SCHEME Clocking Scheme with CLKOUT, Interrupts and Alarms: 34/59

35 5.4. MEASURING THE 1024 HZ TIME ACCURACY AT CLKOUT PIN (1805) Cycles of the 1024 Hz clock level are gated (negative calibration) or replaced by khz level pulses (positive calibration) within every 32 second calibration period. Each step modifies the clock frequency by 1.0 ppm, with a maximum adjustment of ~+xxx/-yyy ppm. The pulses which are added to or subtracted from the 1024 Hz clock level are spread evenly over each 32 second period using the temperature compensation algorithm. This insures that the maximum cycle-to-cycle jitter in any clock of a frequency 1024 Hz caused by calibration will be no more than one khz period. 35/59

36 5.5. MEASURING THE 1 HZ FREQUENCY ACCURACY AT CLKOUT PIN The simplest method to verify the frequency accuracy of the Temperature Compensation Unit (TCP) is by measuring the compensated 1 Hz frequency at the CLKOUT pin. If the 1 Hz frequency is selected, the temperature is always measured and compensated by the RV-8803-C7. 1. Select the 1 Hz frequency at CLKOUT: a. Set the FSEL field to 10 = 1 Hz (see EXTENSION REGISTER, 0Dh, 1Dh). b. Set the CLKOUT pin into output mode by setting the CLKOE pin to high level. 2. Measuring equipment and setup: a. Use a high-precision universal counter to observe the frequency stability on CLKOUT pin. b. Correct setup: If measuring the 1 Hz clock, only one period must be measured to verify the frequency accuracy. Trigger on the rising edge of the hybrid signal. 1 Hz frequency accuracy at CLKOUT pin (hybrid signal): CLKOUT Output is active HIGH. When measuring the frequency accuracy it is mandatory to trigger on the rising edge of the CLKOUT signal. The positive edge is created by the internal 10 MHz RC oscillator (+/- 0.1 ppm per correction step). The falling edge of the CLKOUT signal is generated when the RV-8803-C7 clears the signal after 500 ms. The negative edge is created by the khz Xtal (+/ ppm per correction step) and must not be used to test the frequency accuracy. 36/59

37 5.6. MEASURING THE 1 HZ FREQUENCY ACCURACY AT INT PIN The Periodic Countdown Timer Interrupt function or the Periodic Time Update Interrupt function can also be used to verify the frequency accuracy of the Temperature Compensation Unit (TCP) by measuring the compensated 1 Hz frequency at the INT output pin. However these two procedures are more sophisticated than using the CLKOUT pin. The following two chapters describe the two methods. If the 1 Hz frequency is selected, the temperature is always measured and compensated by the RV-8803-C MEASURING 1 HZ WITH THE PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION 1. Select the Periodic Countdown Timer Interrupt function with the frequency 1 Hz at the INT output pin: a. Write 0 to TIE, TE and TF bits b. Choose TSEL = 10 = 1 Hz, t RTN = 15.6 ms (see EXTENSION REGISTER, 0Dh, 1Dh) c. Write 1 into 0Bh, 1Bh d. Write 0 into 0Ch, 1Ch e. Set TIE bit to 1 to enable the INT pin f. Set TE form 0 to 1 to start the countdown timer (see USE OF THE PERIODIC COUNTDOWN TIMER INTERRUPT) 2. Measuring equipment and setup: a. Use a high-precision universal counter to observe the frequency stability on INT output pin. b. Correct setup: If measuring the 1 Hz clock only one period must be measured (frequency accuracy). Trigger on the falling edge of the hybrid signal. 1 Hz frequency accuracy at INTpin with the Periodic Countdown Timer Interrupt function (hybrid signal): INT Output is active LOW. When measuring the frequency accuracy it is mandatory to trigger on the falling edge of the INT signal. The negative edge is created by the internal 10 MHz RC oscillator (+/- 0.1 ppm per correction step). The rising edge of the INT signal is generated when the RV-8803-C7 clears the signal after the auto reset time t RTN = 15.6 ms. The positive edge is created by the khz Xtal (+/ ppm per correction step) and must not be used to test the frequency accuracy. 37/59

38 5.6.2.MEASURING 1 HZ WITH THE PERIODIC TIME UPDATE INTERRUPT FUNCTION 1. Select the Periodic Time Update Interrupt function with the frequency 1 Hz at the INT output pin: a. Write 0 to UIE and UF bits b. Choose USEL = 0 = 1 Hz, t RTN = 500 ms (Default value) (see EXTENSION REGISTER, 0Dh, 1Dh) c. Set UIE bit to 1 to enable the INT pin. d. The first interrupt will occur after the next event. 2. Measuring equipment and setup: a. Use a high-precision universal counter to observe the frequency stability on INT output pin b. Correct setup: If measuring the 1 Hz clock only one period must be measured (frequency accuracy). Trigger on the falling edge of the hybrid signal. 1 Hz frequency accuracy at INTpin with the Periodic Time Update Interrupt function (hybrid signal): INT Output is active LOW. When measuring the frequency accuracy it is mandatory to trigger on the falling edge of the INT signal. The negative edge is created by the internal 10 MHz RC oscillator (+/- 0.1 ppm per correction step). The rising edge of the INT signal is generated when the RV-8803-C7 clears the signal after the auto reset time t RTN = 500 ms. The positive edge is created by the khz Xtal (+/ ppm per correction step) and must not be used to test the frequency accuracy. 38/59