SIMULATION STUDY OF BALLISTIC CARBON NANOTUBE FIELD EFFECT TRANSISTOR

SIMULATION STUDY OF BALLISTIC CARBON NANOTUBE FIELD EFFECT TRANSISTOR RAHMAT SANUDIN IEEE NATIONAL SYMPOSIUM ON MICROELECTRONICS 2005 21-24 NOVEMBER 2005 KUCHING SARAWAK

Simulation Study of Ballistic Carbon Nanotube Field-Effect Transistor Rahmat Sanudin 1 and Razali Ismail 2 'Department of Electronic Engineering, Faculty of Electrical & Electronic Engineering, Kolej Universiti Teknologi Tun Hussein Onn, 86400 Batu Pahat, Johor, MALAYSIA, department of Microelectronics and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor, MALAYSIA. Email: 1 rahmats@kuittho.edu.my, 2 razali@fke.utm.my Abstract Carbon nanotube is predicted as the most promising carbon nanostructure for future digital electronic application due to its superior electrical characteristics. One of the examples is the employment of CNT in fieldeffect transistor. Carbon nanotube field-effect transistors (CNFET) are extensively studied as a possible replacement for silicon MOSFET. Simulation study of ballistic transport of CNFET is carried out in this paper as a mean to measure performance limit of this device. I-V characteristic of ballistic CNFET is simulated through MATLAB program using surface-potentialbased model. The simulation result is presented and then compared with current silicon transistor technology. It is found that CNFET is comparable to silicon MOSFET. I. INTRODUCTION SCALING process of MOSFET over several decades is seen as a successful achievement but the process will eventually reach its limit in future. Although the size of present day MOSFET is reaching nanometre scale, but other new nanoelectronic devices have been suggested to replace MOSFET as the heart of digital applications in the future [1]. Among the nanoelectronic devices that are being developed includes single-electron transistors (SET), resonant tunnelling devices (RTD) and carbon nanotube field-effect transistor (CNFET). These devices are not only offering smaller size in device geometry but are also superior in terms of device performance [2]. For example, SET has the scalability in semiconductor current and high potential in memoiy density [3] whereas RTD provides multi-state switching behaviour [4]. Nevertheless, carbon nanotubes (CNT) are considered as the most promising carbon nanostructures material in realising the nanoelectronic transistors which was discovered by Sumio Iijima in 1991 [5]. CNT are hollow cylinders that composed of one or more concentric layers of carbon atoms in lattice arrangement. The structure of CNT can be viewed as a sheet of graphite rolled to form a tube and the bond at the end of sheet forms the close of the tube [6]. Depending on its chirality (rolling direction), CNT can have either semiconducting or metallic behaviour. Semiconducting CNT have gained attraction since the first demonstration of its application in transistor by Tans et. al. in 1997 [7]. Semiconducting CNT are used as channel in field-effect transistors, which is the same role of silicon channel in MOSFET. The obvious reason of suitability of CNT for digital applications is not only of its small size but also due to its superior electrical characteristic such as resistance to electromigration and its ability to stand very high current density of up to 10 9 A/cm 2. The characteristics of CNT can be summarised in Table 1 below [8]. TABLE 1 Electrical and mechanical properties of CNT Electrical conductivity Electrical transport Energy gap Maximum current density Thermal conductivity Diameter Length Gravimetric surface E-modulus Metallic or semiconducting Ballistic transport (no scattering) Ee (ev) ~ 1/d (nm) ~10 1U AW 6000 W/km 1-100 nm Up to millimetres > 1500 m7g 1000 GPa Since the first experiment of CNFET by Tans et. al. in 1997, the investigation of characteristics

of CNFET has evolved tremendously in order to measure its performance. One of the characteristic of CNT that contribute to highperformance of CNFET is the one-dimensional carrier transport [6]. This type of transport helps to suppress the scattering effect in CNT and thus promotes ballistic transport in transistor channel. This characteristic makes CNFET as a ballistic device, which is suitable for high-performance circuit design. This paper investigates the I-V characteristics of CNFET through simulation and then compares its performance with MOSFET. N. BALLISTIC CNFET A. Theory of Ballistic CNFET The structure of CNFET is almost the same as silicon MOSFET where there are source and drain terminals attached to either ends of CNT, and gate terminals that attached on the CNT with the CNT itself acts as transistor channel. The CNFET structure has evolved from back-gated structure [9], to top-gated structure [6], and recently vertical structure [10] has been introduced. This progress shows that the performance of CNFET has been improved continuously over the years. Besides, this progress is driven by the interest in replacing MOSFET as the heart of digital applications in the future. Basically, there are two types of CNFET that is being under research; Schottky-barrier CNFET (SB-CNFET) and MOSFET-like CNFET. SB- MOSFET, as shown in Fig. 1(a), has structure of source and drain terminals made of metal attached to CNT, and this device works on the principle of direct tunnelling through the Schottky barrier at source-channel junction [11], [12]. The gate voltage determines the barrier width and thus it controls the trans-conductance of the device. The second type of MOSFET is known as MOSFET-like CNFET since the structure resembles the structure of MOSFET with heavily-doped source and drain terminals as shown in Fig. 1(b). This device operates on the principle of modulating the barrier height with respect to gate voltage. Gate voltage determines the charge induced in the channel and thus has total control on drain current. The MOSFET-like device can reach the near ballistic limit operation as shown by Guo et. al. [13]. Metal Higklydoped Gate 00 Intrinsic CNT p ZrO, Gate flo Fig. 1 (a) Diagram of SB-CNFET, (b) Diagram of MOSFET-like CNFET In this paper, the MOSFET-like CNFET is taken as model for simulation for ballistic transport in CNFET. This model is used to define the I-V characteristic of ballistic CNFET and a performance comparison with MOSFET will be made based on the I-V characteristic. B. Simulation model of Ballistic CNFET The simulation model used in this paper is based on the model that is described below [14]. The gate voltage, V G, induces the charge in the channel and to control Ihe top of energy band between source and drain. Current flow from source to drain is made possible by lowering source-drain barrier. The current can be calculated at the top of the barrier since the current is the same throughout the channel. At top of the barrier, electrons coming from source fill up the +k states whereas electrons from drain fill up the -k states, as depicted in Fig. 2. Er; qv;;, \ Elk) Fig. 2 Illustration of electrons filling up k-states at the top of barrier

The model for ballistic CNFET consists of three capacitors, which represented three terminals on potentials at top of barrier. As shown in Fig. 3, the shaded region indicates mobile charge at top of the barrier. The mobile charge is determined by the local density of states at top of the barrier, location of source and drain levels, E Ft and E F2, and self-consistent potential at top of the barrier, Uscf. U,= - q(a<n G + a D V D + a s Vs) (3)» ^ C ^ n ^ 9 where a G = a D = -f-, a s = C s Cj. c 2 Next, potential due to mobile charge is computed as U p =^-(N,+ N 2 )-N 0 (4) CO where N 0 = J D(E)f(E - E F )de -co Finally, U scf is found by adding both equations (3) and (4) Fig. 3 The model for ballistic CNFET The computation steps based on surface potential-based model [14] is as follows: i) Consider a value of V G> V D, V s and E F!. For simplicity, V s is grounded as potential reference. ii) Compute the total charge on nanotube channel. The charge at top of the barrier contributedfromsource and drain are given as U scf = U, + U r 2 = -q(a G V G +a D V D +a s V s )+ (N,+ NJ-No (5) iv) Drain current is computed by using the formula ID [ln(l+exp(, / - U scf )) h -ln(l+exp{e F2 -UsM (6) where k B is Boltzman constant, T is operating temperature and h is Planck's constant. - 2 J f(e u. -00 N 2 = m ) f ( E + Ui O0 E F1 ) de (1) E F2 )de (2) where N, represents positive velocity states filled by source and N 2 represents negative velocity states filling by drain, E F i(f2> is the source (drain) Fermi level, f(e) is the probability that a state with energy E is occupied, D(E) is the nanotube density of states (DOS) at top of the barrier and U sq f is self-consistent potential at the top of the barrier. For simplicity, assume source Fermi level as the reference, thus E Ft = 0 and E F2 = -?VDS where q is electronic charge. iii) U sq f must be evaluated in order to solve for charge density at top of the barrier. U SC f can be solved by using superposition. First, Laplace potential is calculated using (v) Byrepeatingstep (i)-(i v ) f r a set of (V G, V D ) points, the ID(VG, V d ) characteristics can be determined. III. SIMULATION RESULT AND ANALYSIS Simulation model described in the previous section is implemented using MATLAB in order to observe the I-V characteristic of CNFET. Fig. 4(a) shows the Ip-V D curve and Fig. 4(b) illustrates the I D -V G curve characteristics for n- type CNFET. The result obtained is based on lnm diameter of CNT and the oxide thickness is 1.5nm. In Figure 4(a), at any given gate voltage, the drain current saturates as the drain voltage gets larger. The drain current shown in Figure 4(a) saturates when the drain voltage is large since the negative instates is not occupied.

D Graph ld vs VQ for different VG first subband in nanotube band structure. Hence, based on this comparison, CNFET shows no clear advantage over silicon MOSFET, in particular for low-voltage application, although previous work on CNFET had proved better performance of CNFET [15], [16]. The result presented in this paper only show that CNFET performance is on a par with silicon MOSFET. 15 10 5 0 0.2 0.4 0.6 0.8 1 Vp[Volt] (a) Fig. 4 (a) Plot of I D VS. V d for different V G (b) Plot of I D VS. V g for different V D In order to evaluate the performance of CNFET in digital electronic system, it is crucial to compare them with silicon MOSFET. It is more appropriate to compare both devices in terms of quantity that is dimensionless or with the same dimension. In this case, on-off current ratio at specified bias is taken as the yardstick to compare the performance between CNFET and MOSFET. For CNFET, the on-current at 0.6V D as depicted in Figure 4(a) is 11 (lia and from Figure 4(b), log is about 4x10" 5 na. Thus, the WW = 2.75xl0 5, which is comparable to lonm ballistic double-gate MOSFET as reported in [14] (I n = 1400fiA/ im and W = 5xlO" 3 na/jim at o.6v D, WW = 2.8x10 s ). CNFET has lower on-off current ratio compared to silicon MOSFET because at 0.6V, the charge only occupies the <b> RV. CONCLUSION This paper investigates the I-V characteristics of ballistic CNFET by means of simulation approach. The model used for simulation in this paper is a simple analytical model as described by Rahman et. al. [14], The result obtained in the simulation is then used to compare the performance between CNFET and MOSFET. This analysis is important to gauge the performance of CNFET for future digital application given its small size. It is found that from the I-V characteristics, this device is comparable to MOSFET in terms of on-off current ratio produced at a specified bias voltage. Although the result shows that CNFET is comparable to silicon MOSFET, better performances of CNFET have been reported in previous work. Its performance can be improved further since more research is still going on to improve CNFET's capability. Thus, it is possible for CNFET to be widely used in digital electronic application in future. REFRENCES [1] M. T. Bohr, "Nanotechnology Goals and Challenges for Electronic Applications", IEEE Transactions on Nanotechnology. vol.1, no.l, pp. 56-62 (2002). [2] D. Goldhaber-Gordon et. al., "Overview of Nanoelectronic Devices", Proceedings of The IEEE, vol. 85, no. 4, pp. 521-540 (1997). [3] S. M. Goodnick and J. Bird, "Quantum Effect and Single-Electron Devices", IEEE Transactions on Nanotechnology, vol. 2, no. 4, pp. 368-383 (2003). [4] Y. Taur, "CMOS design near the limit of scaling", IBM J. Ref. & Dev., vol. 46, no. 2, pp. 213-220 (2002). [5] M. S. Dresselhaus, G. Dresselhaus and P. Avouris, Eds., Carbon Nanotubes: Synthesis, Structure, Properties and Applications. Berlin, Germany: Springer-Verlag, 2001.

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