Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17
Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 ) 2.3 2.3 5.8 5.8 12.8 12.8 µ (cm 2 /V s) 550 250 460 160 400 100 µc ox (µa/v 2 ) 127 58 267 93 511 128 V t0 (V) 0.7-0.7 0.5-0.6 0.4-0.4 V DD (V) 5 5 2.5 2.5 1.3 1.3 V A (V/µm) 25 20 5 6 5 6 C ov (ff/µm) 0.2 0.2 0.3 0.3 0.36 0.33 Oxide thickness is decreasing Capacitance increases Increases electric field (V/d) 18
Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 ) 2.3 2.3 5.8 5.8 12.8 12.8 µ (cm 2 /V s) 550 250 460 160 400 100 µc ox (µa/v 2 ) 127 58 267 93 511 128 V t0 (V) 0.7-0.7 0.5-0.6 0.4-0.4 V DD (V) 5 5 2.5 2.5 1.3 1.3 V A (V/µm) 25 20 5 6 5 6 C ov (ff/µm) 0.2 0.2 0.3 0.3 0.36 0.33 Reduced device geometry increases transistors/unit area (L 2 ) increases total power dissipation channel length modulation more pronounced increases device speed (i = C dv/dt) 19
Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 ) 2.3 2.3 5.8 5.8 12.8 12.8 µ (cm 2 /V s) 550 250 460 160 400 100 µc ox (µa/v 2 ) 127 58 267 93 511 128 V t0 (V) 0.7-0.7 0.5-0.6 0.4-0.4 V DD (V) 5 5 2.5 2.5 1.3 1.3 V A (V/µm) 25 20 5 6 5 6 C ov (ff/µm) 0.2 0.2 0.3 0.3 0.36 0.33 Reduced operating voltage reduces power consumption (CV 2 ) V t is a larger portion of V DD 20
Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) 500 900 2 2 I S (A) 5 x 10-15 2 x 10-15 6 x 10-18 6 x 10-18 β 0 200 50 100 50 V A (V) 130 50 35 30 V CE0 (V) 50 60 8 18 t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) 200 300 400 200 Good performance pnp transistors are harder to fabricate on IC than npn (b and forward transit time) 21
Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) 500 900 2 2 I S (A) 5 x 10-15 2 x 10-15 6 x 10-18 6 x 10-18 β 0 200 50 100 50 V A (V) 130 50 35 30 V CE0 (V) 50 60 8 18 t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) 200 300 400 200 f T = 400 600 MHz f T = 10 25 GHz 22
Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) 500 900 2 2 I S (A) 5 x 10-15 2 x 10-15 6 x 10-18 6 x 10-18 β 0 200 50 100 50 V A (V) 130 50 35 30 V CE0 (V) 50 60 8 18 t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) 200 300 400 200 Higher speed technology coupled with lower C-E breakdown voltage 23
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 Lecture 12 1
MOSFET vs. BJT current-voltage characteristic 1.5 10 3 i C ( v) i D ( v) 1 10 3 500 0 2 4 6 8 10 v The drain current of a MOSFET follows a square law relationship The collector current of a BJT follows an exponential relationship This means that the BJT can control a current that varies over ~5 orders of magnitude, compared to MOSFET current that varies as v OV 2 (0.1 0.3 V), or about 1 order of magnitude. 2
MOSFET vs. BJT design parameters Significant parameter MOSFET W/L BJT A E (E-B junction area) Range 1.0 500 10:1 3
MOSFET vs. BJT design tradeoffs Available parameters MOSFET I D, V OV, W, L BJT I C, V BE, I S Useful parameters Pick any 3 I C (V BE is related and not very adjustable) 4
Differential and Multistage Amplifiers Ch 8 5
Noise issues with single ended systems Noise, interference Ground loops, offset reference 6
Noise issues with single ended systems Noise, interference Large effective antenna 7
DC offset issues with single ended systems offset reference 8
Differential benefits + - Differential signal Independent of ground reference + - 9
Differential benefits Differential amplification lends itself to twisted pair wiring + - Alternate loops cancel Small antenna loops + - 10
MOS differential pair MOSFETs are biased for saturation mode operation (not triode region) Resistive loads (for now) Ideal current source 11
Common-mode input voltage Assume identical MOSFETs, identical drain resistors 12
Common-mode input voltage Range of common mode voltage is limited: I V + V + V + V V V + V R 2 V CS ss CS t OV CM DD t D 13
Differential input voltage For all current to flow through Q 1 : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 14
Differential input voltage For all current to flow through Q 1 : This determines limits of v id : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 2V v 2V OV id OV 15
Differential input voltage For all current to flow through Q 1 : This determines limits of v id : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 2V v 2V OV id OV Both transistors are in saturation, even though one is not conducting 16
Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t v = v v = v v id GS1 GS 2 G1 G2 17
Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t v = v v = v v id GS1 GS 2 G1 G2 1 W i i = k v 2 L I = i + i ' D1 D2 n id D1 D2 18
Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t i D1 v = v v = v v id GS1 GS 2 G1 G2 I I vid vid /2 = + 1 2 VOV 2 VOV 2 1 W i i = k v 2 L I = i + i ' D1 D2 n id D1 D2 i D1 I I vid vid /2 = 1 2 VOV 2 VOV 2 19
Large signal operation 20
Large signal operation Nonlinear operating characteristics 21
Large signal operation Limited linear operating range v id /2 << V OV 22