54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Similar documents
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS

74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES

74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 JANUARY 1990 REVISED APRIL 1993

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS

54AC11533, 74AC11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54AHC123A, SN74AHC123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54HC04, SN74HC04 HEX INVERTERS

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997

SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS


SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN75158 DUAL DIFFERENTIAL LINE DRIVER

MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER

ua9637ac DUAL DIFFERENTIAL LINE RECEIVER

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

CDC391 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994

ORDERING INFORMATION PACKAGE

CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

ORDERING INFORMATION PACKAGE

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS


SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER

SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SN QUADRUPLE HALF-H DRIVER

SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS

SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

PCA8550 NONVOLATILE 5-BIT REGISTER WITH I 2 C INTERFACE

SN74AHC1G04 SINGLE INVERTER GATE

SN75150 DUAL LINE DRIVER

ORDERING INFORMATION PACKAGE

CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER

SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER

CDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995

SN54HC590A, SN74HC590A 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS SCLS039C DECEMBER 1982 REVISED MAY 1997

SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

ORDERING INFORMATION PACKAGE SOT (SC-70) DCK

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

SN75150 DUAL LINE DRIVER

SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

ORDERING INFORMATION PACKAGE

MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A QUADRUPLE LINE RECEIVERS

SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS

MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS

NE556, SA556, SE556, SE556C DUAL PRECISION TIMERS

LM139, LM139A, LM239, LM239A, LM339, LM339A, LM339Y, LM2901 QUAD DIFFERENTIAL COMPARATORS

ULN2804A DARLINGTON TRANSISTOR ARRAY

SN75468, SN75469 DARLINGTON TRANSISTOR ARRAYS

SN75374 QUADRUPLE MOSFET DRIVER

TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC

RC4136, RM4136, RV4136 QUAD GENERAL-PURPOSE OPERATIONAL AMPLIFIERS

Transcription:

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 00-mA Typical Latch-Up Immunity at 12 C Package Optio Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset ( or ) or clear ( or 2CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are traferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 4ACT11109, 4ACT11109 The 4ACT11109 is characterized for operation over the full military temperature range of C to 12 C. The 4ACT11109 is characterized for operation from 40 C to C. EPIC is a trademark of Texas Itruments Incorporated. FUTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H H H H L L L H H H H L Toggle H H L H Q0 Q0 H H H H H L H H L X X Q0 Q0 This configuration is notable; that is, it will not persist when either PRE or CLR retur to the inactive (high) level. 4ACT11109...J PACKAGE 4ACT11109...D OR N PACKAGE (TOP VIEW) GND 1 2 4 1 1 1 12 11 10 9 4ACT11109... FK PACKAGE (TOP VIEW) VCC 4 2 1 20 19 1 1 1 1 9 10 11 12 1 GND 2CLR No internal connection V CC 2CLR PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 199, Texas Itruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2 2 1

logic symbol 2CLR 1 1 1 1 10 9 11 S C1 R 2 This symbol is in accordance with ANSI/IEEE Std 91-194 and IEC Publication 1-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0. V to V Input voltage range, V I (see Note 1).......................................... 0. V to V CC + 0. V Output voltage range, V O (see Note 1)....................................... 0. V to V CC + 0. V Input clamp current, I IK (V I < 0 or V I > V CC )............................................... ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC )........................................... ±0 ma Continuous output current, I O (V O = 0 to V CC )............................................. ±0 ma Continuous current through V CC or GND................................................. ±100 ma Storage temperature range....................................................... C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditio 4ACT11109 4ACT11109 MIN MAX MIN MAX VCC Supply voltage 4.. 4.. V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0. 0. V VI Input voltage CC CC V VO Output voltage CC CC V IOH High-level output current 24 24 ma IOL Low-level output current 24 24 ma t/ v Input traition rise or fall rate 0 10 0 10 / V TA Operating free-air temperature 12 40 C 2 2 POST OFFICE BOX 0 DALLAS, TEXAS 2

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = 0 µa IOH = 24 ma TA = 2 C 4ACT11109 4ACT11109 MIN TYP MAX MIN MAX MIN MAX 4. V 4.4 4.4 4.4. V.4.4.4 4. V.94... V 4.94 4. 4. IOH = 0 ma. V. IOH = ma. V. IOL =0µA IOL =24mA 4. V 0.1 0.1 0.1. V 0.1 0.1 0.1 4. V 0. 0. 0.44. V 0. 0. 0.44 IOL = 0 ma. V 1. IOL = ma. V 1. II VI = VCC or GND. V ±0.1 ±1 ±1 µa ICC VI = VCC or GND, IO = 0. V 4 0 40 µa ICC One input at.4 V, Other inputs at VCC or GND. V 0.9 1 1 ma Ci VI = VCC or GND V. pf Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than or VCC. timing requirements over recommended operating free-air temperature range, V CC = V ± 0. V (unless otherwise noted) (see Figure 1) TA = 2 C 4ACT11109 4ACT11109 MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 100 0 100 0 100 MHz tw tsu Pulse duration Setup time before CLK PRE or CLR low... CLK high or low Data high or low... PRE or CLR inactive 2 2 2 th Hold time, data after CLK 0 0 0 V V switching characteristics over recommended operating free-air temperature range, V CC = V ± 0. V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TA = 2 C 4ACT11109 4ACT11109 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 100 12 100 100 MHz PRE or CLR CLK QorQ Q QorQ Q 1... 1. 9. 1. 9.2 1. 10. 1. 12. 1. 11. 1.. 1. 9. 1. 9.1 1... 1. 9 1.. POST OFFICE BOX 0 DALLAS, TEXAS 2 2

operating characteristics, V CC = V, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance per flip-flop CL = 0 pf, f = 1 MHz 1 pf PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 0 pf (see Note A) 00 Ω Input LOAD CIRCUIT Timing Input (see Note B) Data Input tsu th Input (see Note B) In-Phase Output Out-of-Phase Output NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 0 Ω, tr =, tf =. C. The outputs are measured one at a time with one input traition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2 4 POST OFFICE BOX 0 DALLAS, TEXAS 2

IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. ILUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 199, Texas Itruments Incorporated