SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

Size: px

Start display at page:

Download "SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS"

Amelia May
5 years ago
Views:

1 Multiplexed I/O Ports Provide Improved Bit Deity Four Modes of Operation: old (Store) Shift Right Shift eft oad Data Operate With Outputs Enabled or at igh Impedance -State Outputs Drive Bus ines Directly Can Be Cascaded for n-bit Word engths Direct Overriding Clear Applicatio: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These -bit universal shift/storage registers feature multiplexed I/O ports to achieve full -bit data handling in a single 20-pin package. Two function-select (, ) inputs and two outputenable (OE, ) inputs can be used to choose the modes of operation listed in the function table. SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS SN4AS299...J PACKAGE SN74AS DW OR N PACKAGE (TOP VIEW) G/Q G E/Q E C/Q C A/Q A Q A OE G/Q G E/Q E C/Q C A/Q A Q A CR GND Synchronous parallel loading is accomplished by taking both and high. This places the -state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CR) input is low. Taking either OE or high disables the outputs, but has no effect on clearing, shifting, or storing data. The SN4AS299 is characterized for operation over the full military temperature range of C to 2 C. The SN74AS299 is characterized for operation from 0 C to 70 C V CC S Q /Q F/Q F D/Q D B/Q B CK SN4AS FK PACKAGE (TOP VIEW) OE CR GND V CC CK B/Q B S Q /Q F/Q F D/Q D PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 994, Texas Itruments Incorporated POST OFFICE BO 60 DAAS, TEAS 726

2 SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS FUNCTION TABE INPUTS I/O PORTS OUTPUTS MODE CR OE CK S A/QA B/QB C/QC D/QD E/QE F/QF G/QG /Q QA Q Clear old Shift Right Shift eft oad a b c d e f g h a h NOTE: a...h = the level of the steady-state input at inputs A through, respectively. This data is loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. logic symbol QB0 QB0 QAn QAn QC0 QC0 QD0 QD0 QE0 QE0 QF0 QF0 QG0 QG0 Qn Qn Q0 Q0 Q0 Q0 CR OE CK G R & EN 0 M 0 C4/ /2 A/QA 7,4D,4D QA B/QB,,4D Z C/QC D/QD E/QE F/QF G/QG /Q S ,,4D 2, 2,4D Z6 Z2 7 Q This symbol is in accordance with ANSI/IEEE Std 9-94 and IEC Publication POST OFFICE BO 60 DAAS, TEAS 726

3 SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS logic diagram (positive logic) (shift right serial input) 9 Six Identical Channels Not Shown S (shift left serial input) CK 2 QA CR 9 D R C D R C 7 Q OE A/QA /Q I/O ports not shown: B/QB (), C/QC (6), D/QD (4), E/QE (), F/QF (), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I : All inputs V I/O ports V Operating free-air temperature range, T A : SN4AS C to 2 C SN74AS C to 70 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. POST OFFICE BO 60 DAAS, TEAS 726

4 SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS recommended operating conditio SN4AS299 SN74AS299 MIN NOM MA MIN NOM MA VCC Supply voltage V VI igh-level input voltage 2 2 V VI ow-level input voltage V IO IO igh-level output current ow-level output current QA or Q QA Q 2.6 QA or Q 4 QA Q 2 24 TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN4AS299 SN74AS299 MIN TYP MA MIN TYP MA VIK VCC = 4. V, II =.. V VO VO II All outputs VCC = 4. V to. V, IO = 0.4 VCC 2 VCC 2 QA Q VCC =4V 4. QA or Q VCC =4V 4. QA Q VCC =4V 4. A Any others VCC =V. IO = 2.4. V IO = IO = IO = IO = IO = VI =. V VI = 7 V II VCC =. V, VI = 2.7 V µa II IO,,, S Any others QA or Q QA Q VCC =. V, VI =04V 0.4 V VCC =V. V, VO = 2.22 V Outputs high 2 2 ICC VCC =. V Outputs low Outputs disabled All typical values are at VCC = V, TA = 2 C. For I/O ports (QA Q), the parameters II and II include the off-state output current. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. V 4 POST OFFICE BO 60 DAAS, TEAS 726

5 SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN4AS299 SN74AS299 MIN MA MIN MA fclock Clock frequency (at 0% duty cycle) Mz tw tsu th Pulse duration Setup time before CK CK high or low CR low 2 0 or 2 20 Serial or parallel data igh 6 ow 6 Inactive-state setup time before CK CR old time after CK Inactive-state setup time is also referred to as recovery time. switching characteristics (see Figure ) PARAMETER FROM (INPUT) or 0 0 Serial or parallel data 0 0 TO (OUTPUT) VCC = 4. V to. V, C = 0 pf, R = 00 Ω, R2 = 00 Ω, TA = MIN to MA SN4AS299 SN74AS299 MIN MA MIN MA fmax 7 0 Mz tp tp tp tp tp CK QA Q CK QA or Q CR QA Q QA or Q tpz OE, QA Q tpz tpz , QA QQ tpz tpz OE, QA Q tpz 4 tpz 6 2, QA Q tpz For conditio shown as MIN or MA, use the appropriate value specified under recommended operating conditio. POST OFFICE BO 60 DAAS, TEAS 726

6 SN4AS299, SN74AS299 -BIT UNIVERSA SIFT/STORAGE REGISTERS WIT -STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION SERIES 4AS/74AS AND 4AS/74AS DEVICES VCC 7 V R = R = R2 R From Output Under Test C (see Note A) R Test Point From Output Under Test C (see Note A) Test Point From Output Under Test C (see Note A) R R2 Test Point OAD CIRCUIT FOR BI-STATE TOTEM-POE OUTPUTS OAD CIRCUIT FOR OPEN-COECTOR OUTPUTS OAD CIRCUIT FOR -STATE OUTPUTS Timing Input igh-evel Pulse Data Input tsu th ow-evel Pulse tw VOTAGE WAVEFORMS SETUP AND OD TIMES VOTAGE WAVEFORMS PUSE DURATIONS Output Control (low-level enabling) Waveform Closed (see Note B) tpz tpz tpz VO tpz Waveform 2 VO Open (see Note B) 0 V VOTAGE WAVEFORMS ENABE AND DISABE TIMES, -STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) tp tp tp VO VO tp VO VO VOTAGE WAVEFORMS PROPAGATION DEAY TIMES NOTES: A. C includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch is open. D. All input pulses have the following characteristics: PRR Mz, tr = tf = 2, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure. oad Circuits and Voltage Waveforms 6 POST OFFICE BO 60 DAAS, TEAS 726

7 IMPORTANT NOTICE Texas Itruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applicatio using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applicatio ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTORIZED, OR WARRANTED TO BE SUITABE FOR USE IN IFE-SUPPORT APPICATIONS, DEVICES OR SYSTEMS OR OTER CRITICA APPICATIONS. Inclusion of TI products in such applicatio is understood to be fully at the risk of the customer. Use of TI products in such applicatio requires the written approval of an appropriate TI officer. Questio concerning potential risk applicatio should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 99, Texas Itruments Incorporated

SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS -State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,