WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These octal positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CL) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock () pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When is at either the high or low level, the D input signal has no effect at the output. The SN4ALS27 is characterized for operation over the full military temperature range of C to 2 C. The SN74ALS27 is characterized for operation from 0 C to 70 C. SN4ALS27...J PACKAGE SN74ALS27... DW O N PACKAGE (TOP VIEW) CL Q 2D 2Q Q D 4D 4Q GND 2 4 6 7 0 20 7 6 4 2 4 2 20 6 7 7 6 4 0 2 V CC Q D 7D 7Q 6Q 6D D Q SN4ALS27... FK PACKAGE (TOP VIEW) 2D 2Q Q D 4D Q CL 4Q GND V CC Q D Q D 7D 7Q 6Q 6D FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CL D Q L X X L H H H H L L H H or L X Q0 PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 4, Texas Instruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 logic symbol CL 2D D 4D D 6D 7D D 4 7 4 7 2 6 2 6 Q 2Q Q 4Q Q 6Q 7Q Q This symbol is in accordance with ANSI/IEEE Std -4 and IEC Publication 67-2. logic diagram (positive logic) 2D D 4D D 6D 7D D 4 7 4 7 CL 2 Q 2Q 6 Q 4Q 2 Q 6Q 6 7Q Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC........................................................................ 7 V Input voltage, V I............................................................................ 7 V Operating free-air temperature range, T A : SN4ALS27............................. C to 2 C SN74ALS27................................. 0 C to 70 C Storage temperature range....................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 recommended operating conditions SN4ALS27 SN74ALS27 MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.. 4.. V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0. V IOH High-level output current 2.6 ma IOL Low-level output current 2 24 ma fclock Clock frequency 0 0 0 MHz CL low 0 0 tww Pulse duration high 6. 4 ns low 6. 4 tsu Setup time before Data 0 0 CL inactive state th Hold time, data after 0 0 ns TA Operating free-air temperature 2 0 70 C UNIT ns electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS SN4ALS27 SN74ALS27 MIN TYP MAX MIN TYP MAX VIK VCC = 4. V, II = ma.. V VOH VCC = 4. V to. V, IOH = 0.4 ma VCC 2 VCC 2 VCC =4V 4. VOL VCC =4V 4. IOH = ma 2.4. V IOH = 2.6 ma 2.4.2 IOL = 2 ma 0.2 0.4 0.2 0.4 IOL = 24 ma 0. 0. II VCC =. V, VI = 7 V 0. 0. ma IIH VCC =. V, VI = 2.7 V 20 20 µa IIL VCC =. V, VI = 0.4 V 0.2 0.2 ma IO VCC =. V, VO = 2.2 V 20 2 0 2 ma ICCH VCC =. V 20 20 ma ICCL VCC =. V 2 2 ma All typical values are at VCC = V, TA = 2 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT V POST OFFICE BOX 60 DALLAS, TEXAS 726
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 switching characteristics (see Figure ) PAAMETE FOM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, L = 00 Ω, TA = MIN to MAX SN4ALS27 SN74ALS27 MIN MAX MIN MAX fmax 0 MHz tphl CL Any Q 4 24 4 ns tplh 2 20 2 2 Any Q tphl 7 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 PAAMETE MEASUEMENT INFOMATION SEIES 4ALS/74ALS AND 4AS/74AS DEVICES VCC 7 V L = = 2 S L From Output Under Test CL (see Note A) L Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) 2 Test Point LOAD CICUIT FO BI-STATE TOTEM-POLE OUTPUTS LOAD CICUIT FO OPEN-COLLECTO OUTPUTS LOAD CICUIT FO -STATE OUTPUTS Timing Input High-Level Pulse Data Input tsu th Low-Level Pulse tw VOLTAGE WAVEFOMS SETUP AND HOLD TIMES VOLTAGE WAVEFOMS PULSE DUATIONS Output Control (low-level enabling) Waveform S Closed (see Note B) tpzl tphz tplz VOL tpzh Waveform 2 VOH S Open (see Note B) 0 V VOLTAGE WAVEFOMS ENABLE AND DISABLE TIMES, -STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) tplh tphl tphl VOH VOL tplh VOH VOL VOLTAGE WAVEFOMS POPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: P MHz, tr = tf = 2 ns, duty cycle = 0%. E. The outputs are measured one at a time with one transition per measurement. Figure. Load Circuits and Voltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726
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MECHANICAL DATA MPDI002A JANUAY EVISED OCTOBE N (-PDIP-T**) 6 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** 4 6 20 A A MAX 0.77 (,6) 0.77 (,6) 0.20 (2,7) 0.7 (24,77) 6 A MIN 0.74 (,2) 0.74 (,2) 0.0 (2,) 0.40 (2,) 0.260 (6,60) 0.240 (6,0) 0.070 (,7) MAX 0.0 (0,) MAX 0.020 (0,) MIN 0.0 (7,7) 0.20 (7,7) 0.200 (,0) MAX 0.2 (,) MIN Seating Plane 0.00 (2,4) 0 0.02 (0,) 0.0 (0,) 0.00 (0,2) M 0.00 (0,2) NOM 4/ PIN ONLY 404004/C 0/ NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 (20-pin package is shorter than MS-00). POST OFFICE BOX 60 DALLAS, TEXAS 726
MECHANICAL DATA MSOI00D JANUAY EVISED DECEMBE DW (-PDSO-G**) 6 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.00 (,27) 0.020 (0,) 0.04 (0,) 0.00 (0,2) M 6 0.4 (0,6) 0.400 (0,) 0.2 (7,) 0.2 (7,4) 0.00 (0,2) NOM Gage Plane A 0 0.00 (0,2) 0.00 (,27) 0.06 (0,40) 0.04 (2,6) MAX 0.02 (0,0) 0.004 (0,0) Seating Plane 0.004 (0,0) DIM PINS ** 6 20 24 2 A MAX 0.40 (0,4) 0.0 (2,) 0.60 (,4) 0.70 (,0) A MIN 0.400 (0,6) 0.00 (2,70) 0.600 (,24) 0.700 (7,7) 4040000/ C 07/6 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,). D. Falls within JEDEC MS-0 POST OFFICE BOX 60 DALLAS, TEXAS 726