WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These octal positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CL) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock () pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When is at either the high or low level, the D input signal has no effect at the output. The SNALS2 is characterized for operation over the full military temperature range of C to 2 C. The SNALS2 is characterized for operation from 0 C to 0 C. SNALS2...J PACKAGE SNALS2... DW O N PACKAGE (TOP VIEW) CL Q Q D D Q GND 2 9 0 20 9 2 2 20 9 9 0 2 V CC Q D D Q D Q SNALS2... FK PACKAGE (TOP VIEW) Q D D Q CL Q GND V CC Q D Q D D Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CL D Q L X X L H H H H L L H H or L X Q0 PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 logic symbol CL D D D D D 2 9 2 9 Q Q Q Q Q Q This symbol is in accordance with ANSI/IEEE Std 9-9 and IEC Publication -2. logic diagram (positive logic) D D D D D CL 2 Q Q 9 Q 2 Q Q 9 Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC........................................................................ V Input voltage, V I............................................................................ V Operating free-air temperature range, T A : SNALS2............................. C to 2 C SNALS2................................. 0 C to 0 C Storage temperature range....................................................... C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 0 DALLAS, TEXAS 2
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 recommended operating conditions SNALS2 SNALS2 MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage.... V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0. 0. V IOH High-level output current 2. ma IOL Low-level output current 2 2 ma fclock Clock frequency 0 0 0 MHz CL low 0 0 tw Pulse duration high. ns low. tsu Setup time before Data 0 0 CL inactive state ns th Hold time, data after 0 0 ns TA Operating free-air temperature 2 0 0 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS SNALS2 SNALS2 MIN TYP MAX MIN TYP MAX VIK VCC =. V, II = ma.. V VCC =. V to. V, IOH = 0. ma VCC 2 VCC 2 VCC =V. VOL VCC =V. IOH = ma 2.. V IOH = 2. ma 2..2 IOL = 2 ma 0.2 0. 0.2 0. IOL = 2 ma 0. 0. II VCC =. V, VI = V 0. 0. ma IIH VCC =. V, VI = 2. V 20 20 µa IIL VCC =. V, VI = 0. V 0.2 0.2 ma IO VCC =. V, VO = 2.2 V 20 2 0 2 ma ICCH VCC =. V 20 20 ma ICCL VCC =. V 9 29 9 29 ma All typical values are at VCC = V, TA = 2 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT V POST OFFICE BOX 0 DALLAS, TEXAS 2
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 switching characteristics (see Figure ) PAAMETE FOM (INPUT) TO (OUTPUT) VCC =. V to. V, CL = 0 pf, L = 00 Ω, TA = MIN to MAX SNALS2 SNALS2 MIN MAX MIN MAX fmax 0 MHz tphl CL Any Q 2 ns tplh 2 20 2 2 Any Q tphl For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns POST OFFICE BOX 0 DALLAS, TEXAS 2
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 PAAMETE MEASUEMENT INFOMATION SEIES ALS/ALS AND AS/AS DEVICES VCC V L = = 2 S L From Output Under Test CL (see Note A) L Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) 2 Test Point LOAD CICUIT FO BI-STATE TOTEM-POLE OUTPUTS LOAD CICUIT FO OPEN-COLLECTO OUTPUTS LOAD CICUIT FO -STATE OUTPUTS Timing Input High-Level Pulse Data Input tsu th Low-Level Pulse tw VOLTAGE WAVEFOMS SETUP AND HOLD TIMES VOLTAGE WAVEFOMS PULSE DUATIONS Output Control (low-level enabling) Waveform S Closed (see Note B) Waveform 2 S Open (see Note B) tpzl tpzh tphz tplz VOL VOLTAGE WAVEFOMS ENABLE AND DISABLE TIMES, -STATE OUTPUTS 0 V Input In-Phase Output Out-of-Phase Output (see Note C) tplh tphl tphl VOL tplh VOL VOLTAGE WAVEFOMS POPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: P MHz, tr = tf = 2 ns, duty cycle = 0%. E. The outputs are measured one at a time with one transition per measurement. Figure. Load Circuits and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 2
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